1 /* $NetBSD: if_bwfm_pci.h,v 1.2 2021/08/26 21:33:36 andvar Exp $ */ 2 /* $OpenBSD: if_bwfm_pci.h,v 1.2 2018/01/05 23:30:16 patrick Exp $ */ 3 /* 4 * Copyright (c) 2010-2016 Broadcom Corporation 5 * Copyright (c) 2017 Patrick Wildt <patrick (at) blueri.se> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* Registers */ 21 #define BWFM_PCI_BAR0_WINDOW 0x80 22 #define BWFM_PCI_BAR0_REG_SIZE 0x1000 23 24 #define BWFM_PCI_ARMCR4REG_BANKIDX 0x40 25 #define BWFM_PCI_ARMCR4REG_BANKPDA 0x4C 26 27 #define BWFM_PCI_PCIE2REG_INTMASK 0x24 28 #define BWFM_PCI_PCIE2REG_MAILBOXINT 0x48 29 #define BWFM_PCI_PCIE2REG_MAILBOXMASK 0x4C 30 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_0 0x0100 31 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_1 0x0200 32 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 0x10000 33 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 0x20000 34 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 0x40000 35 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 0x80000 36 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x100000 37 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x200000 38 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x400000 39 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x800000 40 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H_DB \ 41 (BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \ 42 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \ 43 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \ 44 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \ 45 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \ 46 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ 47 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ 48 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1) 49 50 #define BWFM_PCI_PCIE2REG_CONFIGADDR 0x120 51 #define BWFM_PCI_PCIE2REG_CONFIGDATA 0x124 52 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX 0x140 53 54 #define BWFM_PCI_CFGREG_STATUS_CMD 0x004 55 #define BWFM_PCI_CFGREG_PM_CSR 0x04C 56 #define BWFM_PCI_CFGREG_MSI_CAP 0x058 57 #define BWFM_PCI_CFGREG_MSI_ADDR_L 0x05C 58 #define BWFM_PCI_CFGREG_MSI_ADDR_H 0x060 59 #define BWFM_PCI_CFGREG_MSI_DATA 0x064 60 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL 0x0BC 61 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL_ASPM_ENAB 0x3 62 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL2 0x0DC 63 #define BWFM_PCI_CFGREG_RBAR_CTRL 0x228 64 #define BWFM_PCI_CFGREG_PML1_SUB_CTRL1 0x248 65 #define BWFM_PCI_CFGREG_REG_BAR2_CONFIG 0x4E0 66 #define BWFM_PCI_CFGREG_REG_BAR3_CONFIG 0x4F4 67 68 #define BWFM_RAMSIZE 0x6c 69 #define BWFM_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 70 71 #define BWFM_SHARED_INFO 0x000 72 #define BWFM_SHARED_INFO_MIN_VERSION 5 73 #define BWFM_SHARED_INFO_MAX_VERSION 6 74 #define BWFM_SHARED_INFO_VERSION_MASK 0x00FF 75 #define BWFM_SHARED_INFO_DMA_INDEX 0x10000 76 #define BWFM_SHARED_INFO_DMA_2B_IDX 0x100000 77 #define BWFM_SHARED_CONSOLE_ADDR 0x14 78 #define BWFM_SHARED_MAX_RXBUFPOST 0x22 79 #define BWFM_SHARED_MAX_RXBUFPOST_DEFAULT 255 80 #define BWFM_SHARED_RX_DATAOFFSET 0x24 81 #define BWFM_SHARED_HTOD_MB_DATA_ADDR 0x28 82 #define BWFM_SHARED_DTOH_MB_DATA_ADDR 0x2c 83 #define BWFM_SHARED_RING_INFO_ADDR 0x30 84 #define BWFM_SHARED_DMA_SCRATCH_LEN 0x34 85 #define BWFM_SHARED_DMA_SCRATCH_ADDR_LOW 0x38 86 #define BWFM_SHARED_DMA_SCRATCH_ADDR_HIGH 0x3c 87 #define BWFM_SHARED_DMA_RINGUPD_LEN 0x40 88 #define BWFM_SHARED_DMA_RINGUPD_ADDR_LOW 0x44 89 #define BWFM_SHARED_DMA_RINGUPD_ADDR_HIGH 0x48 90 91 #define BWFM_RING_MAX_ITEM 0x04 92 #define BWFM_RING_LEN_ITEMS 0x06 93 #define BWFM_RING_MEM_BASE_ADDR_LOW 0x08 94 #define BWFM_RING_MEM_BASE_ADDR_HIGH 0x0c 95 #define BWFM_RING_MEM_SZ 16 96 97 #define BWFM_CONSOLE_BUFADDR 0x08 98 #define BWFM_CONSOLE_BUFSIZE 0x0c 99 #define BWFM_CONSOLE_WRITEIDX 0x10 100 101 struct bwfm_pci_ringinfo { 102 uint32_t ringmem; 103 uint32_t h2d_w_idx_ptr; 104 uint32_t h2d_r_idx_ptr; 105 uint32_t d2h_w_idx_ptr; 106 uint32_t d2h_r_idx_ptr; 107 uint32_t h2d_w_idx_hostaddr_low; 108 uint32_t h2d_w_idx_hostaddr_high; 109 uint32_t h2d_r_idx_hostaddr_low; 110 uint32_t h2d_r_idx_hostaddr_high; 111 uint32_t d2h_w_idx_hostaddr_low; 112 uint32_t d2h_w_idx_hostaddr_high; 113 uint32_t d2h_r_idx_hostaddr_low; 114 uint32_t d2h_r_idx_hostaddr_high; 115 uint16_t max_flowrings; 116 uint16_t max_submissionrings; 117 uint16_t max_completionrings; 118 }; 119 120 /* Msgbuf defines */ 121 #define MSGBUF_IOCTL_RESP_TIMEOUT 2000 /* msecs */ 122 #define MSGBUF_IOCTL_REQ_PKTID 0xFFFE 123 #define MSGBUF_MAX_PKT_SIZE 2048 124 125 #define MSGBUF_TYPE_GEN_STATUS 0x1 126 #define MSGBUF_TYPE_RING_STATUS 0x2 127 #define MSGBUF_TYPE_FLOW_RING_CREATE 0x3 128 #define MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT 0x4 129 #define MSGBUF_TYPE_FLOW_RING_DELETE 0x5 130 #define MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT 0x6 131 #define MSGBUF_TYPE_FLOW_RING_FLUSH 0x7 132 #define MSGBUF_TYPE_FLOW_RING_FLUSH_CMPLT 0x8 133 #define MSGBUF_TYPE_IOCTLPTR_REQ 0x9 134 #define MSGBUF_TYPE_IOCTLPTR_REQ_ACK 0xA 135 #define MSGBUF_TYPE_IOCTLRESP_BUF_POST 0xB 136 #define MSGBUF_TYPE_IOCTL_CMPLT 0xC 137 #define MSGBUF_TYPE_EVENT_BUF_POST 0xD 138 #define MSGBUF_TYPE_WL_EVENT 0xE 139 #define MSGBUF_TYPE_TX_POST 0xF 140 #define MSGBUF_TYPE_TX_STATUS 0x10 141 #define MSGBUF_TYPE_RXBUF_POST 0x11 142 #define MSGBUF_TYPE_RX_CMPLT 0x12 143 #define MSGBUF_TYPE_LPBK_DMAXFER 0x13 144 #define MSGBUF_TYPE_LPBK_DMAXFER_CMPLT 0x14 145 146 struct msgbuf_common_hdr { 147 uint8_t msgtype; 148 uint8_t ifidx; 149 uint8_t flags; 150 uint8_t rsvd0; 151 uint32_t request_id; 152 }; 153 154 struct msgbuf_buf_addr { 155 uint32_t low_addr; 156 uint32_t high_addr; 157 }; 158 159 struct msgbuf_ioctl_req_hdr { 160 struct msgbuf_common_hdr msg; 161 uint32_t cmd; 162 uint16_t trans_id; 163 uint16_t input_buf_len; 164 uint16_t output_buf_len; 165 uint16_t rsvd0[3]; 166 struct msgbuf_buf_addr req_buf_addr; 167 uint32_t rsvd1[2]; 168 }; 169 170 struct msgbuf_tx_msghdr { 171 struct msgbuf_common_hdr msg; 172 uint8_t txhdr[ETHER_HDR_LEN]; 173 uint8_t flags; 174 #define BWFM_MSGBUF_PKT_FLAGS_FRAME_802_3 (1 << 0) 175 #define BWFM_MSGBUF_PKT_FLAGS_PRIO_SHIFT 5 176 uint8_t seg_cnt; 177 struct msgbuf_buf_addr metadata_buf_addr; 178 struct msgbuf_buf_addr data_buf_addr; 179 uint16_t metadata_buf_len; 180 uint16_t data_len; 181 uint32_t rsvd0; 182 }; 183 184 struct msgbuf_rx_bufpost { 185 struct msgbuf_common_hdr msg; 186 uint16_t metadata_buf_len; 187 uint16_t data_buf_len; 188 uint32_t rsvd0; 189 struct msgbuf_buf_addr metadata_buf_addr; 190 struct msgbuf_buf_addr data_buf_addr; 191 }; 192 193 struct msgbuf_rx_ioctl_resp_or_event { 194 struct msgbuf_common_hdr msg; 195 uint16_t host_buf_len; 196 uint16_t rsvd0[3]; 197 struct msgbuf_buf_addr host_buf_addr; 198 uint32_t rsvd1[4]; 199 }; 200 201 struct msgbuf_completion_hdr { 202 uint16_t status; 203 uint16_t flow_ring_id; 204 }; 205 206 struct msgbuf_rx_event { 207 struct msgbuf_common_hdr msg; 208 struct msgbuf_completion_hdr compl_hdr; 209 uint16_t event_data_len; 210 uint16_t seqnum; 211 uint16_t rsvd0[4]; 212 }; 213 214 struct msgbuf_ioctl_resp_hdr { 215 struct msgbuf_common_hdr msg; 216 struct msgbuf_completion_hdr compl_hdr; 217 uint16_t resp_len; 218 uint16_t trans_id; 219 uint32_t cmd; 220 uint32_t rsvd0; 221 }; 222 223 struct msgbuf_tx_status { 224 struct msgbuf_common_hdr msg; 225 struct msgbuf_completion_hdr compl_hdr; 226 uint16_t metadata_len; 227 uint16_t tx_status; 228 }; 229 230 struct msgbuf_rx_complete { 231 struct msgbuf_common_hdr msg; 232 struct msgbuf_completion_hdr compl_hdr; 233 uint16_t metadata_len; 234 uint16_t data_len; 235 uint16_t data_offset; 236 uint16_t flags; 237 uint32_t rx_status_0; 238 uint32_t rx_status_1; 239 uint32_t rsvd0; 240 }; 241 242 struct msgbuf_tx_flowring_create_req { 243 struct msgbuf_common_hdr msg; 244 uint8_t da[ETHER_ADDR_LEN]; 245 uint8_t sa[ETHER_ADDR_LEN]; 246 uint8_t tid; 247 uint8_t if_flags; 248 uint16_t flow_ring_id; 249 uint8_t tc; 250 uint8_t priority; 251 uint16_t int_vector; 252 uint16_t max_items; 253 uint16_t len_item; 254 struct msgbuf_buf_addr flow_ring_addr; 255 }; 256 257 struct msgbuf_tx_flowring_delete_req { 258 struct msgbuf_common_hdr msg; 259 uint16_t flow_ring_id; 260 uint16_t reason; 261 uint32_t rsvd0[7]; 262 }; 263 264 struct msgbuf_flowring_create_resp { 265 struct msgbuf_common_hdr msg; 266 struct msgbuf_completion_hdr compl_hdr; 267 uint32_t rsvd0[3]; 268 }; 269 270 struct msgbuf_flowring_delete_resp { 271 struct msgbuf_common_hdr msg; 272 struct msgbuf_completion_hdr compl_hdr; 273 uint32_t rsvd0[3]; 274 }; 275 276 struct msgbuf_flowring_flush_resp { 277 struct msgbuf_common_hdr msg; 278 struct msgbuf_completion_hdr compl_hdr; 279 uint32_t rsvd0[3]; 280 }; 281
Indexes created Sat Sep 20 22:09:52 GMT 2025