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      1 /*	$NetBSD: msiiepreg.h,v 1.9 2007/03/04 03:01:07 uwe Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2001 Valeriy E. Ushakov
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the author may not be used to endorse or promote products
     16  *    derived from this software without specific prior written permission
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 
     30 #ifndef _SPARC_MSIIEP_REG_H_
     31 #define _SPARC_MSIIEP_REG_H_
     32 
     33 /*
     34  * microSPARC-IIep PCI controller registers
     35  *
     36  * Accessible via PA=0011.0000 0000.110x xxxx.xxxx AAAA.AAAA
     37  * where 'x' bits are ignored.  We use PA=0x300c.0000 as "canonical".
     38  * We map it at a fixed MSIIEP_PCIC_VA (see vaddrs.h).
     39  *
     40  * Field names are chosen to match relevant OFW forth words.
     41  *
     42  * NB: Upon reset the PCIC registers and PCI bus accesses are in
     43  * little-endian mode.  We configure PCIC to do endian-swapping
     44  * automagically by setting MSIIEP_PIO_CTRL_BIG_ENDIAN bit in
     45  * pcic_pio_ctrl early in the bootstrap process.
     46  *
     47  * Section numbers in comments refer to:
     48  * "microSPARC(TM)-IIep User's Manual" (Sun Part Number: 802-7100-01)
     49  */
     50 
     51 #define MSIIEP_PCIC_PA	((paddr_t)0x300c0000)
     52 #define MSIIEP_MID_PA	((paddr_t)0x10002000)
     53 #define MID_IOA_ENABLE	0x10000		/* IO arbitration */
     54 #define MID_STANDBY	0x0800		/* put CPU into power saving mode */
     55 #define MID_MASK	0x000108fc	/* bits masked out are reserved */
     56 
     57 
     58 struct msiiep_pcic_reg {
     59 	/* PCI_ID_REG */
     60 	uint32_t	pcic_id;		/* @00/4  9.5.2.1 */
     61 
     62 	/* PCI_COMMAND_STATUS_REG */
     63 	uint16_t	pcic_cmd;		/* @04/2  9.5.2.2 */
     64 	uint16_t	pcic_stat;		/* @06/2  9.5.2.3 */
     65 
     66 	/* PCI_CLASS_REG */
     67 	uint32_t	pcic_class;		/* @08/4  9.5.2.1 */
     68 
     69 	/* PCI_BHLC_REG: but with lattimer and cacheline swapped !!! */
     70 	uint32_t	pcic_bhlc;		/* @0c/4  9.5.2.1, 9.5.3*/
     71 
     72 	/* 9.5.5.1  PCI Base Address Registers */
     73 	uint32_t	pcic_ba[6];		/* @10/4 .. @24/4 */
     74 
     75 	uint32_t	pcic_unused_28;
     76 	uint32_t	pcic_unused_2c;
     77 	uint32_t	pcic_unused_30;
     78 	uint32_t	pcic_unused_34;
     79 	uint32_t	pcic_unused_38;
     80 	uint32_t	pcic_unused_3c;
     81 
     82 	/* 9.5.3  #RETRY and #TRDY counters */
     83 	uint32_t	pcic_cntrs;		/* @40/4 */
     84 
     85 	/* 9.5.5.2  PCI Base Size Registers */
     86 	uint32_t	pcic_sz[6];		/* @44/4 .. @58/4 */
     87 
     88 	uint32_t	pcic_unused_5c;
     89 
     90 
     91 	/* 9.6.3  PIO control */
     92 	uint8_t		pcic_pio_ctrl;		/* @60/1 (no word?) */
     93 #define MSIIEP_PIO_CTRL_PREFETCH_ENABLE		0x80
     94 #define MSIIEP_PIO_CTRL_BURST_ENABLE		0x40
     95 #define MSIIEP_PIO_CTRL_BIG_ENDIAN		0x04
     96 
     97 	uint8_t		pcic_unused_61;
     98 
     99 	/* 9.6.4  DVMA control */
    100 	uint8_t		pcic_dvmac;		/* @62/1  (no word?) */
    101 
    102 	/* 9.6.5  Arbitration/Interrupt Control */
    103 	uint8_t		pcic_arb_intr_ctrl;	/* @63/1 */
    104 
    105 	/*  9.7.5  Processor Interrupt Pending */
    106 	uint32_t	pcic_proc_ipr;		/* @64/4 */
    107 
    108 	/* 9.5.3  Discard Timer */
    109 	uint16_t	pcic_discard_tmr;	/* @68/2 */
    110 
    111 	/* 9.7.6  Software Interrupt Clear/Set */
    112 	uint16_t	pcic_soft_intr_clear;	/* @6a/2 */
    113 	uint16_t	pcic_unused_6c;
    114 	uint16_t	pcic_soft_intr_set;	/* @6e/2 */
    115 
    116 	/*  9.7.2  System Interrupt Pending */
    117 	uint32_t	pcic_sys_ipr;		/* @70/4 */
    118 #define MSIIEP_SYS_IPR_PIO_ERR			0x40000000
    119 #define MSIIEP_SYS_IPR_DMA_ERR			0x20000000
    120 #define MSIIEP_SYS_IPR_SERR			0x10000000
    121 #define MSIIEP_SYS_IPR_MEM_FAULT		0x08000000
    122 
    123 #define MSIIEP_SYS_IPR_BITS "\177\20"					\
    124 		"b\36PIO\0" "b\35DMA\0" "b\34SERR#\0" "b\33MEM\0"	\
    125 		"f\0\20INTR\0"
    126 
    127 	/* 9.7.4  System Interrupt Target Mask (read/clear/set) */
    128 	uint32_t	pcic_sys_itmr;		/* @74/4 */
    129 	uint32_t	pcic_sys_itmr_clr;	/* @78/4 */
    130 	uint32_t	pcic_sys_itmr_set;	/* @7c/4 */
    131 #define MSIIEP_SYS_ITMR_ALL			0x80000000
    132 #define MSIIEP_SYS_ITMR_PIO_ERR			0x40000000
    133 #define MSIIEP_SYS_ITMR_DMA_ERR			0x20000000
    134 #define MSIIEP_SYS_ITMR_SERR			0x10000000
    135 #define MSIIEP_SYS_ITMR_MEM_FAULT		0x08000000
    136 #define MSIIEP_SYS_ITMR_RESET			0x04000000
    137 
    138 	uint8_t		pcic_unused_80;
    139 	uint8_t		pcic_unused_81;
    140 	uint8_t		pcic_unused_82;
    141 
    142 	/* 9.7.3  Clear System Interrupt Pending */
    143 	uint8_t		pcic_sys_ipr_clr;	/* @83/1 */
    144 #define MSIIEP_SYS_IPR_CLR_ALL			0x80
    145 #define MSIIEP_SYS_IPR_CLR_PIO_ERR		0x40
    146 #define MSIIEP_SYS_IPR_CLR_DMA_ERR		0x20
    147 #define MSIIEP_SYS_IPR_CLR_SERR			0x10
    148 #define MSIIEP_SYS_IPR_CLR_RESET		0x08
    149 
    150 
    151 	/* 9.5.7.1  IOTLB control (the rest of IOTLB regs is below at 90) */
    152 	uint32_t	pcic_iotlb_ctrl;	/* @84/4 (no word?) */
    153 
    154 	/* 9.7.1  Interrupt select PCI_INT_L[0..3] (aka pins A to D) */
    155 	uint16_t	pcic_intr_asgn_sel; 	/* @88/2 */
    156 
    157 	/* 9.6.1  Arbitration Assignment Select */
    158 	uint16_t	pcic_arbt_asgn_sel;	/* @8a/2 */
    159 
    160 	/* 9.7.1  Interrupt Select PCI_INT_L[4..7] */
    161 	uint16_t	pcic_intr_asgn_sel_hi; 	/* @8c/2 */
    162 
    163 	/* 9.7.7  Hardware Interrupt Output */
    164 	uint16_t	pcic_intr_out;		/* @8e/2 (no word) */
    165 
    166 	/* IOTLB RAM/CAM input/output */
    167 	uint32_t	pcic_iotlb_ram_in;	/* @90/4  9.5.7.2 */
    168 	uint32_t	pcic_iotlb_cam_in;	/* @94/4  9.5.7.3 */
    169 	uint32_t	pcic_iotlb_ram_out;	/* @98/4  9.5.8.1 */
    170 	uint32_t	pcic_iotlb_cam_out;	/* @9c/4  9.5.8.2 */
    171 
    172 	/* 9.5.4.1  Memory Cycle Translation Register Set 0 */
    173 	uint8_t		pcic_smbar0;		/* @a0/1 */
    174 	uint8_t		pcic_msize0;		/* @a1/1 */
    175 	uint8_t		pcic_pmbar0;		/* @a2/1 */
    176 	uint8_t		pcic_unused_a3;
    177 
    178 	/* 9.5.4.2  Memory Cycle Translation Register Set 1 */
    179 	uint8_t		pcic_smbar1;		/* @a4/1 */
    180 	uint8_t		pcic_msize1;		/* @a5/1 */
    181 	uint8_t		pcic_pmbar1;		/* @a6/1 */
    182 	uint8_t		pcic_unused_a7;
    183 
    184 	/* 9.5.4.3  I/O Cycle Translation Register Set */
    185 	uint8_t		pcic_sibar;		/* @a8/1 */
    186 	uint8_t		pcic_iosize;		/* @a9/1 */
    187 	uint8_t		pcic_pibar;		/* @aa/1 */
    188 	uint8_t		pcic_unused_ab;
    189 
    190 	/*
    191 	 * 9.8  Processor and system counters:
    192 	 *      (limit, counter, non-resetting limit)
    193 	 */
    194 #define MSIIEP_COUNTER_LIMIT	0x80000000
    195 
    196 	/* processor counter (xor user timer that we don't use) */
    197 	uint32_t	pcic_pclr;		/* @ac/4  9.8.1 */
    198 	uint32_t	pcic_pccr;		/* @b0/4  9.8.2 */
    199 	uint32_t	pcic_pclr_nr;		/* @b4/4  9.8.3 */
    200 
    201 	/* system counter */
    202 	uint32_t	pcic_sclr;		/* @b8/4  9.8.4 */
    203 	uint32_t	pcic_sccr;		/* @bc/4  9.8.5 */
    204 	uint32_t	pcic_sclr_nr;		/* @c0/4  9.8.6 */
    205 
    206 	/* 9.8.7  User Timer Start/Stop */
    207 	uint8_t		pcic_pc_ctl;		/* @c4/1 */
    208 
    209 	/* 9.8.8  Processor Counter or User Timer Configuration */
    210 	uint8_t		pcic_pc_cfg;		/* @c5/1 (no word?) */
    211 
    212 	/* 9.8.9  Counter Interrupt Priority Assignment */
    213 	uint8_t		pcic_cipar;		/* @c6/1 */
    214 
    215 
    216 	/* 9.5.9  PIO Error Command and Address Registers */
    217 	uint8_t		pcic_pio_err_cmd;	/* @c7/1 */
    218 	uint32_t	pcic_pio_err_addr;	/* @c8/4 */
    219 
    220 	/* 9.5.8.3  IOTLB Error Address */
    221 	uint32_t	pcic_iotlb_err_addr;	/* @cc/4 */
    222 
    223 	/* 9.9  System Status and System Control (Reset) */
    224 	uint8_t		pcic_sys_scr;		/* @d0/1 */
    225 
    226 
    227 	/* pad to 256 bytes */
    228 	uint8_t		pcic_unused_d1;
    229 	uint8_t		pcic_unused_d2;
    230 	uint8_t		pcic_unused_d3;
    231 	uint32_t	pcic_unused_pad[11];
    232 };
    233 
    234 
    235 
    236 /* XXX: these are temporary hacks to for the conversion of the sources */
    237 #define mspcic_read_1(reg) \
    238 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)
    239 #define mspcic_read_2(reg) \
    240 	(le16toh(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg))
    241 #define mspcic_read_4(reg) \
    242 	(le32toh(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg))
    243 
    244 #define mspcic_read_stream_1(reg) \
    245 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)
    246 #define mspcic_read_stream_2(reg) \
    247 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)
    248 #define mspcic_read_stream_4(reg) \
    249 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)
    250 
    251 #define mspcic_write_1(reg, val) \
    252 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)
    253 #define mspcic_write_2(reg, val) \
    254 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (htole16(val))
    255 #define mspcic_write_4(reg, val) \
    256 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (htole32(val))
    257 
    258 #define mspcic_write_stream_1(reg, val) \
    259 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)
    260 #define mspcic_write_stream_2(reg, val) \
    261 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)
    262 #define mspcic_write_stream_4(reg, val) \
    263 	(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)
    264 
    265 #endif /* _SPARC_MSIIEP_REG_H_ */
    266