1 /* $NetBSD: dvo_ns2501.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $ */ 2 3 /* 4 * 5 * Copyright (c) 2012 Gilles Dartiguelongue, Thomas Richter 6 * 7 * All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the 11 * "Software"), to deal in the Software without restriction, including 12 * without limitation the rights to use, copy, modify, merge, publish, 13 * distribute, sub license, and/or sell copies of the Software, and to 14 * permit persons to whom the Software is furnished to do so, subject to 15 * the following conditions: 16 * 17 * The above copyright notice and this permission notice (including the 18 * next paragraph) shall be included in all copies or substantial portions 19 * of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 22 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 25 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 26 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 27 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 * 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: dvo_ns2501.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $"); 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "intel_display_types.h" 37 #include "intel_dvo_dev.h" 38 39 #define NS2501_VID 0x1305 40 #define NS2501_DID 0x6726 41 42 #define NS2501_VID_LO 0x00 43 #define NS2501_VID_HI 0x01 44 #define NS2501_DID_LO 0x02 45 #define NS2501_DID_HI 0x03 46 #define NS2501_REV 0x04 47 #define NS2501_RSVD 0x05 48 #define NS2501_FREQ_LO 0x06 49 #define NS2501_FREQ_HI 0x07 50 51 #define NS2501_REG8 0x08 52 #define NS2501_8_VEN (1<<5) 53 #define NS2501_8_HEN (1<<4) 54 #define NS2501_8_DSEL (1<<3) 55 #define NS2501_8_BPAS (1<<2) 56 #define NS2501_8_RSVD (1<<1) 57 #define NS2501_8_PD (1<<0) 58 59 #define NS2501_REG9 0x09 60 #define NS2501_9_VLOW (1<<7) 61 #define NS2501_9_MSEL_MASK (0x7<<4) 62 #define NS2501_9_TSEL (1<<3) 63 #define NS2501_9_RSEN (1<<2) 64 #define NS2501_9_RSVD (1<<1) 65 #define NS2501_9_MDI (1<<0) 66 67 #define NS2501_REGC 0x0c 68 69 /* 70 * The following registers are not part of the official datasheet 71 * and are the result of reverse engineering. 72 */ 73 74 /* 75 * Register c0 controls how the DVO synchronizes with 76 * its input. 77 */ 78 #define NS2501_REGC0 0xc0 79 #define NS2501_C0_ENABLE (1<<0) /* enable the DVO sync in general */ 80 #define NS2501_C0_HSYNC (1<<1) /* synchronize horizontal with input */ 81 #define NS2501_C0_VSYNC (1<<2) /* synchronize vertical with input */ 82 #define NS2501_C0_RESET (1<<7) /* reset the synchronization flip/flops */ 83 84 /* 85 * Register 41 is somehow related to the sync register and sync 86 * configuration. It should be 0x32 whenever regC0 is 0x05 (hsync off) 87 * and 0x00 otherwise. 88 */ 89 #define NS2501_REG41 0x41 90 91 /* 92 * this register controls the dithering of the DVO 93 * One bit enables it, the other define the dithering depth. 94 * The higher the value, the lower the dithering depth. 95 */ 96 #define NS2501_F9_REG 0xf9 97 #define NS2501_F9_ENABLE (1<<0) /* if set, dithering is enabled */ 98 #define NS2501_F9_DITHER_MASK (0x7f<<1) /* controls the dither depth */ 99 #define NS2501_F9_DITHER_SHIFT 1 /* shifts the dither mask */ 100 101 /* 102 * PLL configuration register. This is a pair of registers, 103 * one single byte register at 1B, and a pair at 1C,1D. 104 * These registers are counters/dividers. 105 */ 106 #define NS2501_REG1B 0x1b /* one byte PLL control register */ 107 #define NS2501_REG1C 0x1c /* low-part of the second register */ 108 #define NS2501_REG1D 0x1d /* high-part of the second register */ 109 110 /* 111 * Scaler control registers. Horizontal at b8,b9, 112 * vertical at 10,11. The scale factor is computed as 113 * 2^16/control-value. The low-byte comes first. 114 */ 115 #define NS2501_REG10 0x10 /* low-byte vertical scaler */ 116 #define NS2501_REG11 0x11 /* high-byte vertical scaler */ 117 #define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */ 118 #define NS2501_REGB9 0xb9 /* high-byte horizontal scaler */ 119 120 /* 121 * Display window definition. This consists of four registers 122 * per dimension. One register pair defines the start of the 123 * display, one the end. 124 * As far as I understand, this defines the window within which 125 * the scaler samples the input. 126 */ 127 #define NS2501_REGC1 0xc1 /* low-byte horizontal display start */ 128 #define NS2501_REGC2 0xc2 /* high-byte horizontal display start */ 129 #define NS2501_REGC3 0xc3 /* low-byte horizontal display stop */ 130 #define NS2501_REGC4 0xc4 /* high-byte horizontal display stop */ 131 #define NS2501_REGC5 0xc5 /* low-byte vertical display start */ 132 #define NS2501_REGC6 0xc6 /* high-byte vertical display start */ 133 #define NS2501_REGC7 0xc7 /* low-byte vertical display stop */ 134 #define NS2501_REGC8 0xc8 /* high-byte vertical display stop */ 135 136 /* 137 * The following register pair seems to define the start of 138 * the vertical sync. If automatic syncing is enabled, and the 139 * register value defines a sync pulse that is later than the 140 * incoming sync, then the register value is ignored and the 141 * external hsync triggers the synchronization. 142 */ 143 #define NS2501_REG80 0x80 /* low-byte vsync-start */ 144 #define NS2501_REG81 0x81 /* high-byte vsync-start */ 145 146 /* 147 * The following register pair seems to define the total number 148 * of lines created at the output side of the scaler. 149 * This is again a low-high register pair. 150 */ 151 #define NS2501_REG82 0x82 /* output display height, low byte */ 152 #define NS2501_REG83 0x83 /* output display height, high byte */ 153 154 /* 155 * The following registers define the end of the front-porch 156 * in horizontal and vertical position and hence allow to shift 157 * the image left/right or up/down. 158 */ 159 #define NS2501_REG98 0x98 /* horizontal start of display + 256, low */ 160 #define NS2501_REG99 0x99 /* horizontal start of display + 256, high */ 161 #define NS2501_REG8E 0x8e /* vertical start of the display, low byte */ 162 #define NS2501_REG8F 0x8f /* vertical start of the display, high byte */ 163 164 /* 165 * The following register pair control the function of the 166 * backlight and the DVO output. To enable the corresponding 167 * function, the corresponding bit must be set in both registers. 168 */ 169 #define NS2501_REG34 0x34 /* DVO enable functions, first register */ 170 #define NS2501_REG35 0x35 /* DVO enable functions, second register */ 171 #define NS2501_34_ENABLE_OUTPUT (1<<0) /* enable DVO output */ 172 #define NS2501_34_ENABLE_BACKLIGHT (1<<1) /* enable backlight */ 173 174 /* 175 * Registers 9C and 9D define the vertical output offset 176 * of the visible region. 177 */ 178 #define NS2501_REG9C 0x9c 179 #define NS2501_REG9D 0x9d 180 181 /* 182 * The register 9F defines the dithering. This requires the 183 * scaler to be ON. Bit 0 enables dithering, the remaining 184 * bits control the depth of the dither. The higher the value, 185 * the LOWER the dithering amplitude. A good value seems to be 186 * 15 (total register value). 187 */ 188 #define NS2501_REGF9 0xf9 189 #define NS2501_F9_ENABLE_DITHER (1<<0) /* enable dithering */ 190 #define NS2501_F9_DITHER_MASK (0x7f<<1) /* dither masking */ 191 #define NS2501_F9_DITHER_SHIFT 1 /* upshift of the dither mask */ 192 193 enum { 194 MODE_640x480, 195 MODE_800x600, 196 MODE_1024x768, 197 }; 198 199 struct ns2501_reg { 200 u8 offset; 201 u8 value; 202 }; 203 204 /* 205 * The following structure keeps the complete configuration of 206 * the DVO, given a specific output configuration. 207 * This is pretty much guess-work from reverse-engineering, so 208 * read all this with a grain of salt. 209 */ 210 struct ns2501_configuration { 211 u8 sync; /* configuration of the C0 register */ 212 u8 conf; /* configuration register 8 */ 213 u8 syncb; /* configuration register 41 */ 214 u8 dither; /* configuration of the dithering */ 215 u8 pll_a; /* PLL configuration, register A, 1B */ 216 u16 pll_b; /* PLL configuration, register B, 1C/1D */ 217 u16 hstart; /* horizontal start, registers C1/C2 */ 218 u16 hstop; /* horizontal total, registers C3/C4 */ 219 u16 vstart; /* vertical start, registers C5/C6 */ 220 u16 vstop; /* vertical total, registers C7/C8 */ 221 u16 vsync; /* manual vertical sync start, 80/81 */ 222 u16 vtotal; /* number of lines generated, 82/83 */ 223 u16 hpos; /* horizontal position + 256, 98/99 */ 224 u16 vpos; /* vertical position, 8e/8f */ 225 u16 voffs; /* vertical output offset, 9c/9d */ 226 u16 hscale; /* horizontal scaling factor, b8/b9 */ 227 u16 vscale; /* vertical scaling factor, 10/11 */ 228 }; 229 230 /* 231 * DVO configuration values, partially based on what the BIOS 232 * of the Fujitsu Lifebook S6010 writes into registers, 233 * partially found by manual tweaking. These configurations assume 234 * a 1024x768 panel. 235 */ 236 static const struct ns2501_configuration ns2501_modes[] = { 237 [MODE_640x480] = { 238 .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC, 239 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD, 240 .syncb = 0x32, 241 .dither = 0x0f, 242 .pll_a = 17, 243 .pll_b = 852, 244 .hstart = 144, 245 .hstop = 783, 246 .vstart = 22, 247 .vstop = 514, 248 .vsync = 2047, /* actually, ignored with this config */ 249 .vtotal = 1341, 250 .hpos = 0, 251 .vpos = 16, 252 .voffs = 36, 253 .hscale = 40960, 254 .vscale = 40960 255 }, 256 [MODE_800x600] = { 257 .sync = NS2501_C0_ENABLE | 258 NS2501_C0_HSYNC | NS2501_C0_VSYNC, 259 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD, 260 .syncb = 0x00, 261 .dither = 0x0f, 262 .pll_a = 25, 263 .pll_b = 612, 264 .hstart = 215, 265 .hstop = 1016, 266 .vstart = 26, 267 .vstop = 627, 268 .vsync = 807, 269 .vtotal = 1341, 270 .hpos = 0, 271 .vpos = 4, 272 .voffs = 35, 273 .hscale = 51248, 274 .vscale = 51232 275 }, 276 [MODE_1024x768] = { 277 .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC, 278 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD, 279 .syncb = 0x32, 280 .dither = 0x0f, 281 .pll_a = 11, 282 .pll_b = 1350, 283 .hstart = 276, 284 .hstop = 1299, 285 .vstart = 15, 286 .vstop = 1056, 287 .vsync = 2047, 288 .vtotal = 1341, 289 .hpos = 0, 290 .vpos = 7, 291 .voffs = 27, 292 .hscale = 65535, 293 .vscale = 65535 294 } 295 }; 296 297 /* 298 * Other configuration values left by the BIOS of the 299 * Fujitsu S6010 in the DVO control registers. Their 300 * value does not depend on the BIOS and their meaning 301 * is unknown. 302 */ 303 304 static const struct ns2501_reg mode_agnostic_values[] = { 305 /* 08 is mode specific */ 306 [0] = { .offset = 0x0a, .value = 0x81, }, 307 /* 10,11 are part of the mode specific configuration */ 308 [1] = { .offset = 0x12, .value = 0x02, }, 309 [2] = { .offset = 0x18, .value = 0x07, }, 310 [3] = { .offset = 0x19, .value = 0x00, }, 311 [4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */ 312 /* 1b,1c,1d are part of the mode specific configuration */ 313 [5] = { .offset = 0x1e, .value = 0x02, }, 314 [6] = { .offset = 0x1f, .value = 0x40, }, 315 [7] = { .offset = 0x20, .value = 0x00, }, 316 [8] = { .offset = 0x21, .value = 0x00, }, 317 [9] = { .offset = 0x22, .value = 0x00, }, 318 [10] = { .offset = 0x23, .value = 0x00, }, 319 [11] = { .offset = 0x24, .value = 0x00, }, 320 [12] = { .offset = 0x25, .value = 0x00, }, 321 [13] = { .offset = 0x26, .value = 0x00, }, 322 [14] = { .offset = 0x27, .value = 0x00, }, 323 [15] = { .offset = 0x7e, .value = 0x18, }, 324 /* 80-84 are part of the mode-specific configuration */ 325 [16] = { .offset = 0x84, .value = 0x00, }, 326 [17] = { .offset = 0x85, .value = 0x00, }, 327 [18] = { .offset = 0x86, .value = 0x00, }, 328 [19] = { .offset = 0x87, .value = 0x00, }, 329 [20] = { .offset = 0x88, .value = 0x00, }, 330 [21] = { .offset = 0x89, .value = 0x00, }, 331 [22] = { .offset = 0x8a, .value = 0x00, }, 332 [23] = { .offset = 0x8b, .value = 0x00, }, 333 [24] = { .offset = 0x8c, .value = 0x10, }, 334 [25] = { .offset = 0x8d, .value = 0x02, }, 335 /* 8e,8f are part of the mode-specific configuration */ 336 [26] = { .offset = 0x90, .value = 0xff, }, 337 [27] = { .offset = 0x91, .value = 0x07, }, 338 [28] = { .offset = 0x92, .value = 0xa0, }, 339 [29] = { .offset = 0x93, .value = 0x02, }, 340 [30] = { .offset = 0x94, .value = 0x00, }, 341 [31] = { .offset = 0x95, .value = 0x00, }, 342 [32] = { .offset = 0x96, .value = 0x05, }, 343 [33] = { .offset = 0x97, .value = 0x00, }, 344 /* 98,99 are part of the mode-specific configuration */ 345 [34] = { .offset = 0x9a, .value = 0x88, }, 346 [35] = { .offset = 0x9b, .value = 0x00, }, 347 /* 9c,9d are part of the mode-specific configuration */ 348 [36] = { .offset = 0x9e, .value = 0x25, }, 349 [37] = { .offset = 0x9f, .value = 0x03, }, 350 [38] = { .offset = 0xa0, .value = 0x28, }, 351 [39] = { .offset = 0xa1, .value = 0x01, }, 352 [40] = { .offset = 0xa2, .value = 0x28, }, 353 [41] = { .offset = 0xa3, .value = 0x05, }, 354 /* register 0xa4 is mode specific, but 0x80..0x84 works always */ 355 [42] = { .offset = 0xa4, .value = 0x84, }, 356 [43] = { .offset = 0xa5, .value = 0x00, }, 357 [44] = { .offset = 0xa6, .value = 0x00, }, 358 [45] = { .offset = 0xa7, .value = 0x00, }, 359 [46] = { .offset = 0xa8, .value = 0x00, }, 360 /* 0xa9 to 0xab are mode specific, but have no visible effect */ 361 [47] = { .offset = 0xa9, .value = 0x04, }, 362 [48] = { .offset = 0xaa, .value = 0x70, }, 363 [49] = { .offset = 0xab, .value = 0x4f, }, 364 [50] = { .offset = 0xac, .value = 0x00, }, 365 [51] = { .offset = 0xad, .value = 0x00, }, 366 [52] = { .offset = 0xb6, .value = 0x09, }, 367 [53] = { .offset = 0xb7, .value = 0x03, }, 368 /* b8,b9 are part of the mode-specific configuration */ 369 [54] = { .offset = 0xba, .value = 0x00, }, 370 [55] = { .offset = 0xbb, .value = 0x20, }, 371 [56] = { .offset = 0xf3, .value = 0x90, }, 372 [57] = { .offset = 0xf4, .value = 0x00, }, 373 [58] = { .offset = 0xf7, .value = 0x88, }, 374 /* f8 is mode specific, but the value does not matter */ 375 [59] = { .offset = 0xf8, .value = 0x0a, }, 376 [60] = { .offset = 0xf9, .value = 0x00, } 377 }; 378 379 static const struct ns2501_reg regs_init[] = { 380 [0] = { .offset = 0x35, .value = 0xff, }, 381 [1] = { .offset = 0x34, .value = 0x00, }, 382 [2] = { .offset = 0x08, .value = 0x30, }, 383 }; 384 385 struct ns2501_priv { 386 bool quiet; 387 const struct ns2501_configuration *conf; 388 }; 389 390 #define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr)) 391 392 /* 393 ** Read a register from the ns2501. 394 ** Returns true if successful, false otherwise. 395 ** If it returns false, it might be wise to enable the 396 ** DVO with the above function. 397 */ 398 static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch) 399 { 400 struct ns2501_priv *ns = dvo->dev_priv; 401 struct i2c_adapter *adapter = dvo->i2c_bus; 402 u8 out_buf[2]; 403 u8 in_buf[2]; 404 405 struct i2c_msg msgs[] = { 406 { 407 .addr = dvo->slave_addr, 408 .flags = 0, 409 .len = 1, 410 .buf = out_buf, 411 }, 412 { 413 .addr = dvo->slave_addr, 414 .flags = I2C_M_RD, 415 .len = 1, 416 .buf = in_buf, 417 } 418 }; 419 420 out_buf[0] = addr; 421 out_buf[1] = 0; 422 423 if (i2c_transfer(adapter, msgs, 2) == 2) { 424 *ch = in_buf[0]; 425 return true; 426 } 427 428 if (!ns->quiet) { 429 DRM_DEBUG_KMS 430 ("Unable to read register 0x%02x from %s:0x%02x.\n", addr, 431 adapter->name, dvo->slave_addr); 432 } 433 434 return false; 435 } 436 437 /* 438 ** Write a register to the ns2501. 439 ** Returns true if successful, false otherwise. 440 ** If it returns false, it might be wise to enable the 441 ** DVO with the above function. 442 */ 443 static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch) 444 { 445 struct ns2501_priv *ns = dvo->dev_priv; 446 struct i2c_adapter *adapter = dvo->i2c_bus; 447 u8 out_buf[2]; 448 449 struct i2c_msg msg = { 450 .addr = dvo->slave_addr, 451 .flags = 0, 452 .len = 2, 453 .buf = out_buf, 454 }; 455 456 out_buf[0] = addr; 457 out_buf[1] = ch; 458 459 if (i2c_transfer(adapter, &msg, 1) == 1) { 460 return true; 461 } 462 463 if (!ns->quiet) { 464 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d\n", 465 addr, adapter->name, dvo->slave_addr); 466 } 467 468 return false; 469 } 470 471 /* National Semiconductor 2501 driver for chip on i2c bus 472 * scan for the chip on the bus. 473 * Hope the VBIOS initialized the PLL correctly so we can 474 * talk to it. If not, it will not be seen and not detected. 475 * Bummer! 476 */ 477 static bool ns2501_init(struct intel_dvo_device *dvo, 478 struct i2c_adapter *adapter) 479 { 480 /* this will detect the NS2501 chip on the specified i2c bus */ 481 struct ns2501_priv *ns; 482 unsigned char ch; 483 484 ns = kzalloc(sizeof(struct ns2501_priv), GFP_KERNEL); 485 if (ns == NULL) 486 return false; 487 488 dvo->i2c_bus = adapter; 489 dvo->dev_priv = ns; 490 ns->quiet = true; 491 492 if (!ns2501_readb(dvo, NS2501_VID_LO, &ch)) 493 goto out; 494 495 if (ch != (NS2501_VID & 0xff)) { 496 DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n", 497 ch, adapter->name, dvo->slave_addr); 498 goto out; 499 } 500 501 if (!ns2501_readb(dvo, NS2501_DID_LO, &ch)) 502 goto out; 503 504 if (ch != (NS2501_DID & 0xff)) { 505 DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n", 506 ch, adapter->name, dvo->slave_addr); 507 goto out; 508 } 509 ns->quiet = false; 510 511 DRM_DEBUG_KMS("init ns2501 dvo controller successfully!\n"); 512 513 return true; 514 515 out: 516 kfree(ns); 517 return false; 518 } 519 520 static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo) 521 { 522 /* 523 * This is a Laptop display, it doesn't have hotplugging. 524 * Even if not, the detection bit of the 2501 is unreliable as 525 * it only works for some display types. 526 * It is even more unreliable as the PLL must be active for 527 * allowing reading from the chiop. 528 */ 529 return connector_status_connected; 530 } 531 532 static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo, 533 struct drm_display_mode *mode) 534 { 535 DRM_DEBUG_KMS 536 ("is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d)\n", 537 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); 538 539 /* 540 * Currently, these are all the modes I have data from. 541 * More might exist. Unclear how to find the native resolution 542 * of the panel in here so we could always accept it 543 * by disabling the scaler. 544 */ 545 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) || 546 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) || 547 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) { 548 return MODE_OK; 549 } else { 550 return MODE_ONE_SIZE; /* Is this a reasonable error? */ 551 } 552 } 553 554 static void ns2501_mode_set(struct intel_dvo_device *dvo, 555 const struct drm_display_mode *mode, 556 const struct drm_display_mode *adjusted_mode) 557 { 558 const struct ns2501_configuration *conf; 559 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); 560 int mode_idx, i; 561 562 DRM_DEBUG_KMS 563 ("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n", 564 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); 565 566 DRM_DEBUG_KMS("Detailed requested mode settings are:\n" 567 "clock : %d kHz\n" 568 "hdisplay : %d\n" 569 "hblank start : %d\n" 570 "hblank end : %d\n" 571 "hsync start : %d\n" 572 "hsync end : %d\n" 573 "htotal : %d\n" 574 "hskew : %d\n" 575 "vdisplay : %d\n" 576 "vblank start : %d\n" 577 "hblank end : %d\n" 578 "vsync start : %d\n" 579 "vsync end : %d\n" 580 "vtotal : %d\n", 581 adjusted_mode->crtc_clock, 582 adjusted_mode->crtc_hdisplay, 583 adjusted_mode->crtc_hblank_start, 584 adjusted_mode->crtc_hblank_end, 585 adjusted_mode->crtc_hsync_start, 586 adjusted_mode->crtc_hsync_end, 587 adjusted_mode->crtc_htotal, 588 adjusted_mode->crtc_hskew, 589 adjusted_mode->crtc_vdisplay, 590 adjusted_mode->crtc_vblank_start, 591 adjusted_mode->crtc_vblank_end, 592 adjusted_mode->crtc_vsync_start, 593 adjusted_mode->crtc_vsync_end, 594 adjusted_mode->crtc_vtotal); 595 596 if (mode->hdisplay == 640 && mode->vdisplay == 480) 597 mode_idx = MODE_640x480; 598 else if (mode->hdisplay == 800 && mode->vdisplay == 600) 599 mode_idx = MODE_800x600; 600 else if (mode->hdisplay == 1024 && mode->vdisplay == 768) 601 mode_idx = MODE_1024x768; 602 else 603 return; 604 605 /* Hopefully doing it every time won't hurt... */ 606 for (i = 0; i < ARRAY_SIZE(regs_init); i++) 607 ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value); 608 609 /* Write the mode-agnostic values */ 610 for (i = 0; i < ARRAY_SIZE(mode_agnostic_values); i++) 611 ns2501_writeb(dvo, mode_agnostic_values[i].offset, 612 mode_agnostic_values[i].value); 613 614 /* Write now the mode-specific configuration */ 615 conf = ns2501_modes + mode_idx; 616 ns->conf = conf; 617 618 ns2501_writeb(dvo, NS2501_REG8, conf->conf); 619 ns2501_writeb(dvo, NS2501_REG1B, conf->pll_a); 620 ns2501_writeb(dvo, NS2501_REG1C, conf->pll_b & 0xff); 621 ns2501_writeb(dvo, NS2501_REG1D, conf->pll_b >> 8); 622 ns2501_writeb(dvo, NS2501_REGC1, conf->hstart & 0xff); 623 ns2501_writeb(dvo, NS2501_REGC2, conf->hstart >> 8); 624 ns2501_writeb(dvo, NS2501_REGC3, conf->hstop & 0xff); 625 ns2501_writeb(dvo, NS2501_REGC4, conf->hstop >> 8); 626 ns2501_writeb(dvo, NS2501_REGC5, conf->vstart & 0xff); 627 ns2501_writeb(dvo, NS2501_REGC6, conf->vstart >> 8); 628 ns2501_writeb(dvo, NS2501_REGC7, conf->vstop & 0xff); 629 ns2501_writeb(dvo, NS2501_REGC8, conf->vstop >> 8); 630 ns2501_writeb(dvo, NS2501_REG80, conf->vsync & 0xff); 631 ns2501_writeb(dvo, NS2501_REG81, conf->vsync >> 8); 632 ns2501_writeb(dvo, NS2501_REG82, conf->vtotal & 0xff); 633 ns2501_writeb(dvo, NS2501_REG83, conf->vtotal >> 8); 634 ns2501_writeb(dvo, NS2501_REG98, conf->hpos & 0xff); 635 ns2501_writeb(dvo, NS2501_REG99, conf->hpos >> 8); 636 ns2501_writeb(dvo, NS2501_REG8E, conf->vpos & 0xff); 637 ns2501_writeb(dvo, NS2501_REG8F, conf->vpos >> 8); 638 ns2501_writeb(dvo, NS2501_REG9C, conf->voffs & 0xff); 639 ns2501_writeb(dvo, NS2501_REG9D, conf->voffs >> 8); 640 ns2501_writeb(dvo, NS2501_REGB8, conf->hscale & 0xff); 641 ns2501_writeb(dvo, NS2501_REGB9, conf->hscale >> 8); 642 ns2501_writeb(dvo, NS2501_REG10, conf->vscale & 0xff); 643 ns2501_writeb(dvo, NS2501_REG11, conf->vscale >> 8); 644 ns2501_writeb(dvo, NS2501_REGF9, conf->dither); 645 ns2501_writeb(dvo, NS2501_REG41, conf->syncb); 646 ns2501_writeb(dvo, NS2501_REGC0, conf->sync); 647 } 648 649 /* set the NS2501 power state */ 650 static bool ns2501_get_hw_state(struct intel_dvo_device *dvo) 651 { 652 unsigned char ch; 653 654 if (!ns2501_readb(dvo, NS2501_REG8, &ch)) 655 return false; 656 657 return ch & NS2501_8_PD; 658 } 659 660 /* set the NS2501 power state */ 661 static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) 662 { 663 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); 664 665 DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable); 666 667 if (enable) { 668 ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync | 0x08); 669 670 ns2501_writeb(dvo, NS2501_REG41, ns->conf->syncb); 671 672 ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT); 673 msleep(15); 674 675 ns2501_writeb(dvo, NS2501_REG8, 676 ns->conf->conf | NS2501_8_BPAS); 677 if (!(ns->conf->conf & NS2501_8_BPAS)) 678 ns2501_writeb(dvo, NS2501_REG8, ns->conf->conf); 679 msleep(200); 680 681 ns2501_writeb(dvo, NS2501_REG34, 682 NS2501_34_ENABLE_OUTPUT | NS2501_34_ENABLE_BACKLIGHT); 683 684 ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync); 685 } else { 686 ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT); 687 msleep(200); 688 689 ns2501_writeb(dvo, NS2501_REG8, NS2501_8_VEN | NS2501_8_HEN | 690 NS2501_8_BPAS); 691 msleep(15); 692 693 ns2501_writeb(dvo, NS2501_REG34, 0x00); 694 } 695 } 696 697 static void ns2501_destroy(struct intel_dvo_device *dvo) 698 { 699 struct ns2501_priv *ns = dvo->dev_priv; 700 701 if (ns) { 702 kfree(ns); 703 dvo->dev_priv = NULL; 704 } 705 } 706 707 const struct intel_dvo_dev_ops ns2501_ops = { 708 .init = ns2501_init, 709 .detect = ns2501_detect, 710 .mode_valid = ns2501_mode_valid, 711 .mode_set = ns2501_mode_set, 712 .dpms = ns2501_dpms, 713 .get_hw_state = ns2501_get_hw_state, 714 .destroy = ns2501_destroy, 715 }; 716
Indexes created Mon Sep 29 21:09:56 GMT 2025