1 /* $NetBSD: via_dmablit.h,v 1.5 2021/12/19 12:30:23 riastradh Exp $ */ 2 3 /* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro 4 * 5 * Copyright 2005 Thomas Hellstrom. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sub license, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 23 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 24 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 25 * USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Thomas Hellstrom. 29 * Register info from Digeo Inc. 30 */ 31 32 #ifndef _VIA_DMABLIT_H 33 #define _VIA_DMABLIT_H 34 35 #include <linux/dma-mapping.h> 36 #include <linux/workqueue.h> 37 38 #include <drm/drm_wait_netbsd.h> 39 40 #define VIA_NUM_BLIT_ENGINES 2 41 #define VIA_NUM_BLIT_SLOTS 8 42 43 struct _drm_via_descriptor; 44 45 typedef struct _drm_via_sg_info { 46 #ifdef __NetBSD__ 47 bus_dmamap_t dmamap; 48 #else 49 struct page **pages; 50 #endif 51 unsigned long num_pages; 52 #ifdef __NetBSD__ 53 bus_dma_segment_t *desc_segs; 54 int num_desc_segs; 55 void *desc_kva; 56 bus_dmamap_t desc_dmamap; 57 #endif 58 struct _drm_via_descriptor **desc_pages; 59 int num_desc_pages; 60 int num_desc; 61 enum dma_data_direction direction; 62 dma_addr_t chain_start; 63 uint32_t free_on_sequence; 64 unsigned int descriptors_per_page; 65 int aborted; 66 enum { 67 dr_via_device_mapped, 68 dr_via_desc_pages_alloc, 69 dr_via_pages_locked, 70 dr_via_pages_alloc, 71 dr_via_sg_init 72 } state; 73 } drm_via_sg_info_t; 74 75 typedef struct _drm_via_blitq { 76 struct drm_device *dev; 77 uint32_t cur_blit_handle; 78 uint32_t done_blit_handle; 79 unsigned serviced; 80 unsigned head; 81 unsigned cur; 82 unsigned num_free; 83 unsigned num_outstanding; 84 unsigned long end; 85 int aborting; 86 int is_active; 87 drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS]; 88 spinlock_t blit_lock; 89 #ifdef __NetBSD__ 90 drm_waitqueue_t blit_queue[VIA_NUM_BLIT_SLOTS]; 91 drm_waitqueue_t busy_queue; 92 #else 93 wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS]; 94 wait_queue_head_t busy_queue; 95 #endif 96 struct work_struct wq; 97 struct timer_list poll_timer; 98 } drm_via_blitq_t; 99 100 101 /* 102 * PCI DMA Registers 103 * Channels 2 & 3 don't seem to be implemented in hardware. 104 */ 105 106 #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ 107 #define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ 108 #define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ 109 #define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ 110 111 #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ 112 #define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ 113 #define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ 114 #define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ 115 116 #define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ 117 #define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ 118 #define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ 119 #define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ 120 121 #define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ 122 #define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ 123 #define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ 124 #define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ 125 126 #define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ 127 #define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ 128 #define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ 129 #define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ 130 131 #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ 132 #define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ 133 #define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ 134 #define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ 135 136 #define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ 137 138 /* Define for DMA engine */ 139 /* DPR */ 140 #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 141 #define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ 142 #define VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ 143 144 /* MR */ 145 #define VIA_DMA_MR_CM (1<<0) /* chaining mode */ 146 #define VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ 147 #define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ 148 149 /* CSR */ 150 #define VIA_DMA_CSR_DE (1<<0) /* DMA enable */ 151 #define VIA_DMA_CSR_TS (1<<1) /* transfer start */ 152 #define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ 153 #define VIA_DMA_CSR_TD (1<<3) /* transfer done */ 154 #define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ 155 #define VIA_DMA_DPR_EC (1<<1) /* end of chain */ 156 157 158 159 #endif 160
Indexes created Sat Sep 20 22:09:52 GMT 2025