1 /* $NetBSD: amdgpu_gfx.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __AMDGPU_GFX_H__ 27 #define __AMDGPU_GFX_H__ 28 29 /* 30 * GFX stuff 31 */ 32 #include "clearstate_defs.h" 33 #include "amdgpu_ring.h" 34 #include "amdgpu_rlc.h" 35 36 /* GFX current status */ 37 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 38 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 39 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 40 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 41 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 42 43 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 44 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 45 46 struct amdgpu_mec { 47 struct amdgpu_bo *hpd_eop_obj; 48 u64 hpd_eop_gpu_addr; 49 struct amdgpu_bo *mec_fw_obj; 50 u64 mec_fw_gpu_addr; 51 u32 num_mec; 52 u32 num_pipe_per_mec; 53 u32 num_queue_per_pipe; 54 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 55 56 /* These are the resources for which amdgpu takes ownership */ 57 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 58 }; 59 60 enum amdgpu_unmap_queues_action { 61 PREEMPT_QUEUES = 0, 62 RESET_QUEUES, 63 DISABLE_PROCESS_QUEUES, 64 PREEMPT_QUEUES_NO_UNMAP, 65 }; 66 67 struct kiq_pm4_funcs { 68 /* Support ASIC-specific kiq pm4 packets*/ 69 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 70 uint64_t queue_mask); 71 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 72 struct amdgpu_ring *ring); 73 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 74 struct amdgpu_ring *ring, 75 enum amdgpu_unmap_queues_action action, 76 u64 gpu_addr, u64 seq); 77 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 78 struct amdgpu_ring *ring, 79 u64 addr, 80 u64 seq); 81 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 82 uint16_t pasid, uint32_t flush_type, 83 bool all_hub); 84 /* Packet sizes */ 85 int set_resources_size; 86 int map_queues_size; 87 int unmap_queues_size; 88 int query_status_size; 89 int invalidate_tlbs_size; 90 }; 91 92 struct amdgpu_kiq { 93 u64 eop_gpu_addr; 94 struct amdgpu_bo *eop_obj; 95 spinlock_t ring_lock; 96 struct amdgpu_ring ring; 97 struct amdgpu_irq_src irq; 98 const struct kiq_pm4_funcs *pmf; 99 uint32_t reg_val_offs; 100 }; 101 102 /* 103 * GPU scratch registers structures, functions & helpers 104 */ 105 struct amdgpu_scratch { 106 unsigned num_reg; 107 uint32_t reg_base; 108 uint32_t free_mask; 109 }; 110 111 /* 112 * GFX configurations 113 */ 114 #define AMDGPU_GFX_MAX_SE 4 115 #define AMDGPU_GFX_MAX_SH_PER_SE 2 116 117 struct amdgpu_rb_config { 118 uint32_t rb_backend_disable; 119 uint32_t user_rb_backend_disable; 120 uint32_t raster_config; 121 uint32_t raster_config_1; 122 }; 123 124 struct gb_addr_config { 125 uint16_t pipe_interleave_size; 126 uint8_t num_pipes; 127 uint8_t max_compress_frags; 128 uint8_t num_banks; 129 uint8_t num_se; 130 uint8_t num_rb_per_se; 131 }; 132 133 struct amdgpu_gfx_config { 134 unsigned max_shader_engines; 135 unsigned max_tile_pipes; 136 unsigned max_cu_per_sh; 137 unsigned max_sh_per_se; 138 unsigned max_backends_per_se; 139 unsigned max_texture_channel_caches; 140 unsigned max_gprs; 141 unsigned max_gs_threads; 142 unsigned max_hw_contexts; 143 unsigned sc_prim_fifo_size_frontend; 144 unsigned sc_prim_fifo_size_backend; 145 unsigned sc_hiz_tile_fifo_size; 146 unsigned sc_earlyz_tile_fifo_size; 147 148 unsigned num_tile_pipes; 149 unsigned backend_enable_mask; 150 unsigned mem_max_burst_length_bytes; 151 unsigned mem_row_size_in_kb; 152 unsigned shader_engine_tile_size; 153 unsigned num_gpus; 154 unsigned multi_gpu_tile_size; 155 unsigned mc_arb_ramcfg; 156 unsigned gb_addr_config; 157 unsigned num_rbs; 158 unsigned gs_vgt_table_depth; 159 unsigned gs_prim_buffer_depth; 160 161 uint32_t tile_mode_array[32]; 162 uint32_t macrotile_mode_array[16]; 163 164 struct gb_addr_config gb_addr_config_fields; 165 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 166 167 /* gfx configure feature */ 168 uint32_t double_offchip_lds_buf; 169 /* cached value of DB_DEBUG2 */ 170 uint32_t db_debug2; 171 /* gfx10 specific config */ 172 uint32_t num_sc_per_sh; 173 uint32_t num_packer_per_sc; 174 uint32_t pa_sc_tile_steering_override; 175 uint64_t tcc_disabled_mask; 176 }; 177 178 struct amdgpu_cu_info { 179 uint32_t simd_per_cu; 180 uint32_t max_waves_per_simd; 181 uint32_t wave_front_size; 182 uint32_t max_scratch_slots_per_cu; 183 uint32_t lds_size; 184 185 /* total active CU number */ 186 uint32_t number; 187 uint32_t ao_cu_mask; 188 uint32_t ao_cu_bitmap[4][4]; 189 uint32_t bitmap[4][4]; 190 }; 191 192 struct amdgpu_gfx_funcs { 193 /* get the gpu clock counter */ 194 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 195 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 196 u32 sh_num, u32 instance); 197 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 198 uint32_t wave, uint32_t *dst, int *no_fields); 199 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 200 uint32_t wave, uint32_t thread, uint32_t start, 201 uint32_t size, uint32_t *dst); 202 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 203 uint32_t wave, uint32_t start, uint32_t size, 204 uint32_t *dst); 205 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 206 u32 queue, u32 vmid); 207 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); 208 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status); 209 }; 210 211 struct sq_work { 212 struct work_struct work; 213 unsigned ih_data; 214 }; 215 216 struct amdgpu_pfp { 217 struct amdgpu_bo *pfp_fw_obj; 218 uint64_t pfp_fw_gpu_addr; 219 uint32_t *pfp_fw_ptr; 220 }; 221 222 struct amdgpu_ce { 223 struct amdgpu_bo *ce_fw_obj; 224 uint64_t ce_fw_gpu_addr; 225 uint32_t *ce_fw_ptr; 226 }; 227 228 struct amdgpu_me { 229 struct amdgpu_bo *me_fw_obj; 230 uint64_t me_fw_gpu_addr; 231 uint32_t *me_fw_ptr; 232 uint32_t num_me; 233 uint32_t num_pipe_per_me; 234 uint32_t num_queue_per_pipe; 235 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 236 237 /* These are the resources for which amdgpu takes ownership */ 238 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 239 }; 240 241 struct amdgpu_gfx { 242 struct mutex gpu_clock_mutex; 243 struct amdgpu_gfx_config config; 244 struct amdgpu_rlc rlc; 245 struct amdgpu_pfp pfp; 246 struct amdgpu_ce ce; 247 struct amdgpu_me me; 248 struct amdgpu_mec mec; 249 struct amdgpu_kiq kiq; 250 struct amdgpu_scratch scratch; 251 const struct firmware *me_fw; /* ME firmware */ 252 uint32_t me_fw_version; 253 const struct firmware *pfp_fw; /* PFP firmware */ 254 uint32_t pfp_fw_version; 255 const struct firmware *ce_fw; /* CE firmware */ 256 uint32_t ce_fw_version; 257 const struct firmware *rlc_fw; /* RLC firmware */ 258 uint32_t rlc_fw_version; 259 const struct firmware *mec_fw; /* MEC firmware */ 260 uint32_t mec_fw_version; 261 const struct firmware *mec2_fw; /* MEC2 firmware */ 262 uint32_t mec2_fw_version; 263 uint32_t me_feature_version; 264 uint32_t ce_feature_version; 265 uint32_t pfp_feature_version; 266 uint32_t rlc_feature_version; 267 uint32_t rlc_srlc_fw_version; 268 uint32_t rlc_srlc_feature_version; 269 uint32_t rlc_srlg_fw_version; 270 uint32_t rlc_srlg_feature_version; 271 uint32_t rlc_srls_fw_version; 272 uint32_t rlc_srls_feature_version; 273 uint32_t mec_feature_version; 274 uint32_t mec2_feature_version; 275 bool mec_fw_write_wait; 276 bool me_fw_write_wait; 277 bool cp_fw_write_wait; 278 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 279 struct drm_gpu_scheduler *gfx_sched[AMDGPU_MAX_GFX_RINGS]; 280 uint32_t num_gfx_sched; 281 unsigned num_gfx_rings; 282 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 283 struct drm_gpu_scheduler *compute_sched[AMDGPU_MAX_COMPUTE_RINGS]; 284 uint32_t num_compute_sched; 285 unsigned num_compute_rings; 286 struct amdgpu_irq_src eop_irq; 287 struct amdgpu_irq_src priv_reg_irq; 288 struct amdgpu_irq_src priv_inst_irq; 289 struct amdgpu_irq_src cp_ecc_error_irq; 290 struct amdgpu_irq_src sq_irq; 291 struct sq_work sq_work; 292 293 /* gfx status */ 294 uint32_t gfx_current_status; 295 /* ce ram size*/ 296 unsigned ce_ram_size; 297 struct amdgpu_cu_info cu_info; 298 const struct amdgpu_gfx_funcs *funcs; 299 300 /* reset mask */ 301 uint32_t grbm_soft_reset; 302 uint32_t srbm_soft_reset; 303 304 /* gfx off */ 305 bool gfx_off_state; /* true: enabled, false: disabled */ 306 struct mutex gfx_off_mutex; 307 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 308 struct delayed_work gfx_off_delay_work; 309 310 /* pipe reservation */ 311 struct mutex pipe_reserve_mutex; 312 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 313 314 /*ras */ 315 struct ras_common_if *ras_if; 316 }; 317 318 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 319 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 320 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 321 322 /** 323 * amdgpu_gfx_create_bitmask - create a bitmask 324 * 325 * @bit_width: length of the mask 326 * 327 * create a variable length bit mask. 328 * Returns the bitmask. 329 */ 330 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 331 { 332 return (u32)((1ULL << bit_width) - 1); 333 } 334 335 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 336 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 337 338 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 339 unsigned max_sh); 340 341 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 342 struct amdgpu_ring *ring, 343 struct amdgpu_irq_src *irq); 344 345 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 346 347 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 348 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 349 unsigned hpd_size); 350 351 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 352 unsigned mqd_size); 353 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 354 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 355 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 356 357 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 358 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 359 360 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 361 int pipe, int queue); 362 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 363 int *mec, int *pipe, int *queue); 364 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 365 int pipe, int queue); 366 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 367 int pipe, int queue); 368 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 369 int *me, int *pipe, int *queue); 370 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 371 int pipe, int queue); 372 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 373 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev); 374 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 375 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 376 void *err_data, 377 struct amdgpu_iv_entry *entry); 378 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 379 struct amdgpu_irq_src *source, 380 struct amdgpu_iv_entry *entry); 381 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 382 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 383 #endif 384
Indexes created Sat Sep 20 22:09:52 GMT 2025