1 /* $NetBSD: nouveau_dispnv04_crtc.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $ */ 2 3 /* 4 * Copyright 1993-2003 NVIDIA, Corporation 5 * Copyright 2006 Dave Airlie 6 * Copyright 2007 Maarten Maathuis 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_crtc.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $"); 29 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/drm_fourcc.h> 32 #include <drm/drm_plane_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include "nouveau_drv.h" 36 #include "nouveau_reg.h" 37 #include "nouveau_ttm.h" 38 #include "nouveau_bo.h" 39 #include "nouveau_gem.h" 40 #include "nouveau_encoder.h" 41 #include "nouveau_connector.h" 42 #include "nouveau_crtc.h" 43 #include "hw.h" 44 #include "nvreg.h" 45 #include "nouveau_fbcon.h" 46 #include "disp.h" 47 #include "nouveau_dma.h" 48 49 #include <subdev/bios/pll.h> 50 #include <subdev/clk.h> 51 52 static int 53 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 54 struct drm_framebuffer *old_fb); 55 56 static void 57 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 58 { 59 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 60 crtcstate->CRTC[index]); 61 } 62 63 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 64 { 65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 66 struct drm_device *dev = crtc->dev; 67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 68 69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 70 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 73 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 74 } 75 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 76 } 77 78 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 79 { 80 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 81 struct drm_device *dev = crtc->dev; 82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 83 84 nv_crtc->sharpness = level; 85 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 86 level += 0x40; 87 regp->ramdac_634 = level; 88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 89 } 90 91 #define PLLSEL_VPLL1_MASK \ 92 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 93 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 94 #define PLLSEL_VPLL2_MASK \ 95 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 96 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 97 #define PLLSEL_TV_MASK \ 98 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 99 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 100 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 101 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 102 103 /* NV4x 0x40.. pll notes: 104 * gpu pll: 0x4000 + 0x4004 105 * ?gpu? pll: 0x4008 + 0x400c 106 * vpll1: 0x4010 + 0x4014 107 * vpll2: 0x4018 + 0x401c 108 * mpll: 0x4020 + 0x4024 109 * mpll: 0x4038 + 0x403c 110 * 111 * the first register of each pair has some unknown details: 112 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 113 * bits 20-23: (mpll) something to do with post divider? 114 * bits 28-31: related to single stage mode? (bit 8/12) 115 */ 116 117 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 118 { 119 struct drm_device *dev = crtc->dev; 120 struct nouveau_drm *drm = nouveau_drm(dev); 121 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 122 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 123 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 125 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 126 struct nvkm_pll_vals *pv = ®p->pllvals; 127 struct nvbios_pll pll_lim; 128 129 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 130 &pll_lim)) 131 return; 132 133 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 134 pv->NM2 = 0; 135 136 /* for newer nv4x the blob uses only the first stage of the vpll below a 137 * certain clock. for a certain nv4b this is 150MHz. since the max 138 * output frequency of the first stage for this card is 300MHz, it is 139 * assumed the threshold is given by vco1 maxfreq/2 140 */ 141 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 142 * not 8, others unknown), the blob always uses both plls. no problem 143 * has yet been observed in allowing the use a single stage pll on all 144 * nv43 however. the behaviour of single stage use is untested on nv40 145 */ 146 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 147 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 148 149 150 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 151 return; 152 153 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 154 155 /* The blob uses this always, so let's do the same */ 156 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 157 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 158 /* again nv40 and some nv43 act more like nv3x as described above */ 159 if (drm->client.device.info.chipset < 0x41) 160 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 161 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 162 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 163 164 if (pv->NM2) 165 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 167 else 168 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 169 pv->N1, pv->M1, pv->log2P); 170 171 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 172 } 173 174 static void 175 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 176 { 177 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 178 struct drm_device *dev = crtc->dev; 179 struct nouveau_drm *drm = nouveau_drm(dev); 180 unsigned char seq1 = 0, crtc17 = 0; 181 unsigned char crtc1A; 182 183 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 184 nv_crtc->index); 185 186 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 187 return; 188 189 nv_crtc->last_dpms = mode; 190 191 if (nv_two_heads(dev)) 192 NVSetOwner(dev, nv_crtc->index); 193 194 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 195 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 196 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 197 switch (mode) { 198 case DRM_MODE_DPMS_STANDBY: 199 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 200 seq1 = 0x20; 201 crtc17 = 0x80; 202 crtc1A |= 0x80; 203 break; 204 case DRM_MODE_DPMS_SUSPEND: 205 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 206 seq1 = 0x20; 207 crtc17 = 0x80; 208 crtc1A |= 0x40; 209 break; 210 case DRM_MODE_DPMS_OFF: 211 /* Screen: Off; HSync: Off, VSync: Off */ 212 seq1 = 0x20; 213 crtc17 = 0x00; 214 crtc1A |= 0xC0; 215 break; 216 case DRM_MODE_DPMS_ON: 217 default: 218 /* Screen: On; HSync: On, VSync: On */ 219 seq1 = 0x00; 220 crtc17 = 0x80; 221 break; 222 } 223 224 NVVgaSeqReset(dev, nv_crtc->index, true); 225 /* Each head has it's own sequencer, so we can turn it off when we want */ 226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 228 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 229 mdelay(10); 230 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 231 NVVgaSeqReset(dev, nv_crtc->index, false); 232 233 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 234 } 235 236 static void 237 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 238 { 239 struct drm_device *dev = crtc->dev; 240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 242 struct drm_framebuffer *fb = crtc->primary->fb; 243 244 /* Calculate our timings */ 245 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 246 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 247 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 248 int horizTotal = (mode->crtc_htotal >> 3) - 5; 249 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 250 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 251 int vertDisplay = mode->crtc_vdisplay - 1; 252 int vertStart = mode->crtc_vsync_start - 1; 253 int vertEnd = mode->crtc_vsync_end - 1; 254 int vertTotal = mode->crtc_vtotal - 2; 255 int vertBlankStart = mode->crtc_vdisplay - 1; 256 int vertBlankEnd = mode->crtc_vtotal - 1; 257 258 struct drm_encoder *encoder; 259 bool fp_output = false; 260 261 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 262 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 263 264 if (encoder->crtc == crtc && 265 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 266 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 267 fp_output = true; 268 } 269 270 if (fp_output) { 271 vertStart = vertTotal - 3; 272 vertEnd = vertTotal - 2; 273 vertBlankStart = vertStart; 274 horizStart = horizTotal - 5; 275 horizEnd = horizTotal - 2; 276 horizBlankEnd = horizTotal + 4; 277 #if 0 278 if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 279 /* This reportedly works around some video overlay bandwidth problems */ 280 horizTotal += 2; 281 #endif 282 } 283 284 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 285 vertTotal |= 1; 286 287 #if 0 288 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 289 ErrorF("horizStart: 0x%X \n", horizStart); 290 ErrorF("horizEnd: 0x%X \n", horizEnd); 291 ErrorF("horizTotal: 0x%X \n", horizTotal); 292 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 293 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 294 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 295 ErrorF("vertStart: 0x%X \n", vertStart); 296 ErrorF("vertEnd: 0x%X \n", vertEnd); 297 ErrorF("vertTotal: 0x%X \n", vertTotal); 298 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 299 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 300 #endif 301 302 /* 303 * compute correct Hsync & Vsync polarity 304 */ 305 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 306 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 307 308 regp->MiscOutReg = 0x23; 309 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 310 regp->MiscOutReg |= 0x40; 311 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 312 regp->MiscOutReg |= 0x80; 313 } else { 314 int vdisplay = mode->vdisplay; 315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 316 vdisplay *= 2; 317 if (mode->vscan > 1) 318 vdisplay *= mode->vscan; 319 if (vdisplay < 400) 320 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 321 else if (vdisplay < 480) 322 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 323 else if (vdisplay < 768) 324 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 325 else 326 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 327 } 328 329 /* 330 * Time Sequencer 331 */ 332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 333 /* 0x20 disables the sequencer */ 334 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 336 else 337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 341 342 /* 343 * CRTC 344 */ 345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 349 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 352 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 353 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 354 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 355 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 356 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 357 (1 << 4) | 358 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 359 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 360 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 361 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 363 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 364 1 << 6 | 365 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 372 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 374 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 375 /* framebuffer can be larger than crtc scanout area. */ 376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 378 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 379 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 382 383 /* 384 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 385 */ 386 387 /* framebuffer can be larger than crtc scanout area. */ 388 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 389 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 390 regp->CRTC[NV_CIO_CRE_42] = 391 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 393 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 394 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 395 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 396 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 397 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 398 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 399 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 400 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 401 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 402 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 403 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 404 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 405 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 406 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 407 408 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 409 horizTotal = (horizTotal >> 1) & ~1; 410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 411 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 412 } else 413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 414 415 /* 416 * Graphics Display Controller 417 */ 418 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 419 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 420 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 421 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 422 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 425 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 426 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 427 428 regp->Attribute[0] = 0x00; /* standard colormap translation */ 429 regp->Attribute[1] = 0x01; 430 regp->Attribute[2] = 0x02; 431 regp->Attribute[3] = 0x03; 432 regp->Attribute[4] = 0x04; 433 regp->Attribute[5] = 0x05; 434 regp->Attribute[6] = 0x06; 435 regp->Attribute[7] = 0x07; 436 regp->Attribute[8] = 0x08; 437 regp->Attribute[9] = 0x09; 438 regp->Attribute[10] = 0x0A; 439 regp->Attribute[11] = 0x0B; 440 regp->Attribute[12] = 0x0C; 441 regp->Attribute[13] = 0x0D; 442 regp->Attribute[14] = 0x0E; 443 regp->Attribute[15] = 0x0F; 444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 445 /* Non-vga */ 446 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 447 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 448 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 449 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 450 } 451 452 /** 453 * Sets up registers for the given mode/adjusted_mode pair. 454 * 455 * The clocks, CRTCs and outputs attached to this CRTC must be off. 456 * 457 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 458 * be easily turned on/off after this. 459 */ 460 static void 461 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 462 { 463 struct drm_device *dev = crtc->dev; 464 struct nouveau_drm *drm = nouveau_drm(dev); 465 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 468 const struct drm_framebuffer *fb = crtc->primary->fb; 469 struct drm_encoder *encoder; 470 bool lvds_output = false, tmds_output = false, tv_output = false, 471 off_chip_digital = false; 472 473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 474 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 475 bool digital = false; 476 477 if (encoder->crtc != crtc) 478 continue; 479 480 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 481 digital = lvds_output = true; 482 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 483 tv_output = true; 484 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 485 digital = tmds_output = true; 486 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 487 off_chip_digital = true; 488 } 489 490 /* Registers not directly related to the (s)vga mode */ 491 492 /* What is the meaning of this register? */ 493 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 495 496 regp->crtc_eng_ctrl = 0; 497 /* Except for rare conditions I2C is enabled on the primary crtc */ 498 if (nv_crtc->index == 0) 499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 500 #if 0 501 /* Set overlay to desired crtc. */ 502 if (dev->overlayAdaptor) { 503 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 504 if (pPriv->overlayCRTC == nv_crtc->index) 505 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 506 } 507 #endif 508 509 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 510 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 511 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 512 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 513 if (drm->client.device.info.chipset >= 0x11) 514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 515 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 516 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 517 518 /* Unblock some timings */ 519 regp->CRTC[NV_CIO_CRE_53] = 0; 520 regp->CRTC[NV_CIO_CRE_54] = 0; 521 522 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 523 if (lvds_output) 524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 525 else if (tmds_output) 526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 527 else 528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 529 530 /* These values seem to vary */ 531 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 533 534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 535 536 /* probably a scratch reg, but kept for cargo-cult purposes: 537 * bit0: crtc0?, head A 538 * bit6: lvds, head A 539 * bit7: (only in X), head A 540 */ 541 if (nv_crtc->index == 0) 542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 543 544 /* The blob seems to take the current value from crtc 0, add 4 to that 545 * and reuse the old value for crtc 1 */ 546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 547 if (!nv_crtc->index) 548 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 549 550 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 551 * 1 << 30 on 0x60.830), for no apparent reason */ 552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 553 554 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 556 557 regp->crtc_830 = mode->crtc_vdisplay - 3; 558 regp->crtc_834 = mode->crtc_vdisplay - 1; 559 560 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 561 /* This is what the blob does */ 562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 563 564 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 566 567 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 568 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 569 else 570 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 571 572 /* Some misc regs */ 573 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 574 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 575 regp->CRTC[NV_CIO_CRE_86] = 0x1; 576 } 577 578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; 579 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 580 if (lvds_output || tmds_output || tv_output) 581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 582 583 /* Generic PRAMDAC regs */ 584 585 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 586 /* Only bit that bios and blob set. */ 587 regp->nv10_cursync = (1 << 25); 588 589 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 590 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 591 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 592 if (fb->format->depth == 16) 593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 594 if (drm->client.device.info.chipset >= 0x11) 595 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 596 597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 598 regp->tv_setup = 0; 599 600 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 601 602 /* Some values the blob sets */ 603 regp->ramdac_8c0 = 0x100; 604 regp->ramdac_a20 = 0x0; 605 regp->ramdac_a24 = 0xfffff; 606 regp->ramdac_a34 = 0x1; 607 } 608 609 static int 610 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 611 { 612 struct nv04_display *disp = nv04_display(crtc->dev); 613 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); 614 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 615 int ret; 616 617 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false); 618 if (ret == 0) { 619 if (disp->image[nv_crtc->index]) 620 nouveau_bo_unpin(disp->image[nv_crtc->index]); 621 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); 622 } 623 624 return ret; 625 } 626 627 /** 628 * Sets up registers for the given mode/adjusted_mode pair. 629 * 630 * The clocks, CRTCs and outputs attached to this CRTC must be off. 631 * 632 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 633 * be easily turned on/off after this. 634 */ 635 static int 636 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 637 struct drm_display_mode *adjusted_mode, 638 int x, int y, struct drm_framebuffer *old_fb) 639 { 640 struct drm_device *dev = crtc->dev; 641 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 642 struct nouveau_drm *drm = nouveau_drm(dev); 643 int ret; 644 645 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 646 drm_mode_debug_printmodeline(adjusted_mode); 647 648 ret = nv_crtc_swap_fbs(crtc, old_fb); 649 if (ret) 650 return ret; 651 652 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 653 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 654 655 nv_crtc_mode_set_vga(crtc, adjusted_mode); 656 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 657 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 658 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 659 nv_crtc_mode_set_regs(crtc, adjusted_mode); 660 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 661 return 0; 662 } 663 664 static void nv_crtc_save(struct drm_crtc *crtc) 665 { 666 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 667 struct drm_device *dev = crtc->dev; 668 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 669 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 670 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 671 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 672 673 if (nv_two_heads(crtc->dev)) 674 NVSetOwner(crtc->dev, nv_crtc->index); 675 676 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 677 678 /* init some state to saved value */ 679 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 680 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 681 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 682 crtc_state->gpio_ext = crtc_saved->gpio_ext; 683 } 684 685 static void nv_crtc_restore(struct drm_crtc *crtc) 686 { 687 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 688 struct drm_device *dev = crtc->dev; 689 int head = nv_crtc->index; 690 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 691 692 if (nv_two_heads(crtc->dev)) 693 NVSetOwner(crtc->dev, head); 694 695 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 696 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 697 698 nv_crtc->last_dpms = NV_DPMS_CLEARED; 699 } 700 701 static void nv_crtc_prepare(struct drm_crtc *crtc) 702 { 703 struct drm_device *dev = crtc->dev; 704 struct nouveau_drm *drm = nouveau_drm(dev); 705 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 706 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 707 708 if (nv_two_heads(dev)) 709 NVSetOwner(dev, nv_crtc->index); 710 711 drm_crtc_vblank_off(crtc); 712 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 713 714 NVBlankScreen(dev, nv_crtc->index, true); 715 716 /* Some more preparation. */ 717 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 718 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 719 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 720 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 721 } 722 } 723 724 static void nv_crtc_commit(struct drm_crtc *crtc) 725 { 726 struct drm_device *dev = crtc->dev; 727 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 728 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 729 730 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 731 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 732 733 #ifdef __BIG_ENDIAN 734 /* turn on LFB swapping */ 735 { 736 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 737 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 738 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 739 } 740 #endif 741 742 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 743 drm_crtc_vblank_on(crtc); 744 } 745 746 static void nv_crtc_destroy(struct drm_crtc *crtc) 747 { 748 struct nv04_display *disp = nv04_display(crtc->dev); 749 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 750 751 if (!nv_crtc) 752 return; 753 754 drm_crtc_cleanup(crtc); 755 756 if (disp->image[nv_crtc->index]) 757 nouveau_bo_unpin(disp->image[nv_crtc->index]); 758 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 759 760 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 761 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 762 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 763 kfree(nv_crtc); 764 } 765 766 static void 767 nv_crtc_gamma_load(struct drm_crtc *crtc) 768 { 769 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 770 struct drm_device *dev = nv_crtc->base.dev; 771 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 772 u16 *r, *g, *b; 773 int i; 774 775 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 776 r = crtc->gamma_store; 777 g = r + crtc->gamma_size; 778 b = g + crtc->gamma_size; 779 780 for (i = 0; i < 256; i++) { 781 rgbs[i].r = *r++ >> 8; 782 rgbs[i].g = *g++ >> 8; 783 rgbs[i].b = *b++ >> 8; 784 } 785 786 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 787 } 788 789 static void 790 nv_crtc_disable(struct drm_crtc *crtc) 791 { 792 struct nv04_display *disp = nv04_display(crtc->dev); 793 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 794 if (disp->image[nv_crtc->index]) 795 nouveau_bo_unpin(disp->image[nv_crtc->index]); 796 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 797 } 798 799 static int 800 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, 801 uint32_t size, 802 struct drm_modeset_acquire_ctx *ctx) 803 { 804 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 805 806 /* We need to know the depth before we upload, but it's possible to 807 * get called before a framebuffer is bound. If this is the case, 808 * mark the lut values as dirty by setting depth==0, and it'll be 809 * uploaded on the first mode_set_base() 810 */ 811 if (!nv_crtc->base.primary->fb) { 812 nv_crtc->lut.depth = 0; 813 return 0; 814 } 815 816 nv_crtc_gamma_load(crtc); 817 818 return 0; 819 } 820 821 static int 822 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 823 struct drm_framebuffer *passed_fb, 824 int x, int y, bool atomic) 825 { 826 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 827 struct drm_device *dev = crtc->dev; 828 struct nouveau_drm *drm = nouveau_drm(dev); 829 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 830 struct drm_framebuffer *drm_fb; 831 struct nouveau_framebuffer *fb; 832 int arb_burst, arb_lwm; 833 834 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 835 836 /* no fb bound */ 837 if (!atomic && !crtc->primary->fb) { 838 NV_DEBUG(drm, "No FB bound\n"); 839 return 0; 840 } 841 842 /* If atomic, we want to switch to the fb we were passed, so 843 * now we update pointers to do that. 844 */ 845 if (atomic) { 846 drm_fb = passed_fb; 847 fb = nouveau_framebuffer(passed_fb); 848 } else { 849 drm_fb = crtc->primary->fb; 850 fb = nouveau_framebuffer(crtc->primary->fb); 851 } 852 853 nv_crtc->fb.offset = fb->nvbo->bo.offset; 854 855 if (nv_crtc->lut.depth != drm_fb->format->depth) { 856 nv_crtc->lut.depth = drm_fb->format->depth; 857 nv_crtc_gamma_load(crtc); 858 } 859 860 /* Update the framebuffer format. */ 861 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 862 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; 863 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 864 if (drm_fb->format->depth == 16) 865 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 866 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 867 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 868 regp->ramdac_gen_ctrl); 869 870 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 871 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 872 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 873 regp->CRTC[NV_CIO_CRE_42] = 874 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 875 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 876 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 877 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 878 879 /* Update the framebuffer location. */ 880 regp->fb_start = nv_crtc->fb.offset & ~3; 881 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); 882 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 883 884 /* Update the arbitration parameters. */ 885 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, 886 &arb_burst, &arb_lwm); 887 888 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 889 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 890 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 891 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 892 893 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { 894 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 895 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 896 } 897 898 return 0; 899 } 900 901 static int 902 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 903 struct drm_framebuffer *old_fb) 904 { 905 int ret = nv_crtc_swap_fbs(crtc, old_fb); 906 if (ret) 907 return ret; 908 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 909 } 910 911 static int 912 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 913 struct drm_framebuffer *fb, 914 int x, int y, enum mode_set_atomic state) 915 { 916 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 917 struct drm_device *dev = drm->dev; 918 919 if (state == ENTER_ATOMIC_MODE_SET) 920 nouveau_fbcon_accel_save_disable(dev); 921 else 922 nouveau_fbcon_accel_restore(dev); 923 924 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 925 } 926 927 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 928 struct nouveau_bo *dst) 929 { 930 int width = nv_cursor_width(dev); 931 uint32_t pixel; 932 int i, j; 933 934 for (i = 0; i < width; i++) { 935 for (j = 0; j < width; j++) { 936 pixel = nouveau_bo_rd32(src, i*64 + j); 937 938 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 939 | (pixel & 0xf80000) >> 9 940 | (pixel & 0xf800) >> 6 941 | (pixel & 0xf8) >> 3); 942 } 943 } 944 } 945 946 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 947 struct nouveau_bo *dst) 948 { 949 uint32_t pixel; 950 int alpha, i; 951 952 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 953 * cursors (though NPM in combination with fp dithering may not work on 954 * nv11, from "nv" driver history) 955 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 956 * blob uses, however we get given PM cursors so we use PM mode 957 */ 958 for (i = 0; i < 64 * 64; i++) { 959 pixel = nouveau_bo_rd32(src, i); 960 961 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 962 * than" shouldn't happen; fix "equal to" case by adding one to 963 * alpha channel (slightly inaccurate, but so is attempting to 964 * get back to NPM images, due to limits of integer precision) 965 */ 966 alpha = pixel >> 24; 967 if (alpha > 0 && alpha < 255) 968 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 969 970 #ifdef __BIG_ENDIAN 971 { 972 struct nouveau_drm *drm = nouveau_drm(dev); 973 974 if (drm->client.device.info.chipset == 0x11) { 975 pixel = ((pixel & 0x000000ff) << 24) | 976 ((pixel & 0x0000ff00) << 8) | 977 ((pixel & 0x00ff0000) >> 8) | 978 ((pixel & 0xff000000) >> 24); 979 } 980 } 981 #endif 982 983 nouveau_bo_wr32(dst, i, pixel); 984 } 985 } 986 987 static int 988 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 989 uint32_t buffer_handle, uint32_t width, uint32_t height) 990 { 991 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 992 struct drm_device *dev = drm->dev; 993 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 994 struct nouveau_bo *cursor = NULL; 995 struct drm_gem_object *gem; 996 int ret = 0; 997 998 if (!buffer_handle) { 999 nv_crtc->cursor.hide(nv_crtc, true); 1000 return 0; 1001 } 1002 1003 if (width != 64 || height != 64) 1004 return -EINVAL; 1005 1006 gem = drm_gem_object_lookup(file_priv, buffer_handle); 1007 if (!gem) 1008 return -ENOENT; 1009 cursor = nouveau_gem_object(gem); 1010 1011 ret = nouveau_bo_map(cursor); 1012 if (ret) 1013 goto out; 1014 1015 if (drm->client.device.info.chipset >= 0x11) 1016 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1017 else 1018 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1019 1020 nouveau_bo_unmap(cursor); 1021 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 1022 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1023 nv_crtc->cursor.show(nv_crtc, true); 1024 out: 1025 drm_gem_object_put_unlocked(gem); 1026 return ret; 1027 } 1028 1029 static int 1030 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1031 { 1032 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1033 1034 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1035 return 0; 1036 } 1037 1038 struct nv04_page_flip_state { 1039 struct list_head head; 1040 struct drm_pending_vblank_event *event; 1041 struct drm_crtc *crtc; 1042 int bpp, pitch; 1043 u64 offset; 1044 }; 1045 1046 static int 1047 nv04_finish_page_flip(struct nouveau_channel *chan, 1048 struct nv04_page_flip_state *ps) 1049 { 1050 struct nouveau_fence_chan *fctx = chan->fence; 1051 struct nouveau_drm *drm = chan->drm; 1052 struct drm_device *dev = drm->dev; 1053 struct nv04_page_flip_state *s; 1054 unsigned long flags; 1055 1056 spin_lock_irqsave(&dev->event_lock, flags); 1057 1058 if (list_empty(&fctx->flip)) { 1059 NV_ERROR(drm, "unexpected pageflip\n"); 1060 spin_unlock_irqrestore(&dev->event_lock, flags); 1061 return -EINVAL; 1062 } 1063 1064 s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head); 1065 if (s->event) { 1066 drm_crtc_arm_vblank_event(s->crtc, s->event); 1067 } else { 1068 /* Give up ownership of vblank for page-flipped crtc */ 1069 drm_crtc_vblank_put(s->crtc); 1070 } 1071 1072 list_del(&s->head); 1073 if (ps) 1074 *ps = *s; 1075 kfree(s); 1076 1077 spin_unlock_irqrestore(&dev->event_lock, flags); 1078 return 0; 1079 } 1080 1081 int 1082 nv04_flip_complete(struct nvif_notify *notify) 1083 { 1084 struct nouveau_cli *cli = (void *)notify->object->client; 1085 struct nouveau_drm *drm = cli->drm; 1086 struct nouveau_channel *chan = drm->channel; 1087 struct nv04_page_flip_state state; 1088 1089 if (!nv04_finish_page_flip(chan, &state)) { 1090 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), 1091 state.offset + state.crtc->y * 1092 state.pitch + state.crtc->x * 1093 state.bpp / 8); 1094 } 1095 1096 return NVIF_NOTIFY_KEEP; 1097 } 1098 1099 static int 1100 nv04_page_flip_emit(struct nouveau_channel *chan, 1101 struct nouveau_bo *old_bo, 1102 struct nouveau_bo *new_bo, 1103 struct nv04_page_flip_state *s, 1104 struct nouveau_fence **pfence) 1105 { 1106 struct nouveau_fence_chan *fctx = chan->fence; 1107 struct nouveau_drm *drm = chan->drm; 1108 struct drm_device *dev = drm->dev; 1109 unsigned long flags; 1110 int ret; 1111 1112 /* Queue it to the pending list */ 1113 spin_lock_irqsave(&dev->event_lock, flags); 1114 list_add_tail(&s->head, &fctx->flip); 1115 spin_unlock_irqrestore(&dev->event_lock, flags); 1116 1117 /* Synchronize with the old framebuffer */ 1118 ret = nouveau_fence_sync(old_bo, chan, false, false); 1119 if (ret) 1120 goto fail; 1121 1122 /* Emit the pageflip */ 1123 ret = RING_SPACE(chan, 2); 1124 if (ret) 1125 goto fail; 1126 1127 BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); 1128 OUT_RING (chan, 0x00000000); 1129 FIRE_RING (chan); 1130 1131 ret = nouveau_fence_new(chan, false, pfence); 1132 if (ret) 1133 goto fail; 1134 1135 return 0; 1136 fail: 1137 spin_lock_irqsave(&dev->event_lock, flags); 1138 list_del(&s->head); 1139 spin_unlock_irqrestore(&dev->event_lock, flags); 1140 return ret; 1141 } 1142 1143 static int 1144 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1145 struct drm_pending_vblank_event *event, u32 flags, 1146 struct drm_modeset_acquire_ctx *ctx) 1147 { 1148 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; 1149 struct drm_device *dev = crtc->dev; 1150 struct nouveau_drm *drm = nouveau_drm(dev); 1151 struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->primary->fb)->nvbo; 1152 struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; 1153 struct nv04_page_flip_state *s; 1154 struct nouveau_channel *chan; 1155 struct nouveau_cli *cli; 1156 struct nouveau_fence *fence; 1157 struct nv04_display *dispnv04 = nv04_display(dev); 1158 int head = nouveau_crtc(crtc)->index; 1159 int ret; 1160 1161 chan = drm->channel; 1162 if (!chan) 1163 return -ENODEV; 1164 cli = (void *)chan->user.client; 1165 1166 s = kzalloc(sizeof(*s), GFP_KERNEL); 1167 if (!s) 1168 return -ENOMEM; 1169 1170 if (new_bo != old_bo) { 1171 ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM, true); 1172 if (ret) 1173 goto fail_free; 1174 } 1175 1176 mutex_lock(&cli->mutex); 1177 ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL); 1178 if (ret) 1179 goto fail_unpin; 1180 1181 /* synchronise rendering channel with the kernel's channel */ 1182 ret = nouveau_fence_sync(new_bo, chan, false, true); 1183 if (ret) { 1184 ttm_bo_unreserve(&new_bo->bo); 1185 goto fail_unpin; 1186 } 1187 1188 if (new_bo != old_bo) { 1189 ttm_bo_unreserve(&new_bo->bo); 1190 1191 ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL); 1192 if (ret) 1193 goto fail_unpin; 1194 } 1195 1196 /* Initialize a page flip struct */ 1197 *s = (struct nv04_page_flip_state) 1198 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], 1199 new_bo->bo.offset }; 1200 1201 /* Keep vblanks on during flip, for the target crtc of this flip */ 1202 drm_crtc_vblank_get(crtc); 1203 1204 /* Emit a page flip */ 1205 if (swap_interval) { 1206 ret = RING_SPACE(chan, 8); 1207 if (ret) 1208 goto fail_unreserve; 1209 1210 BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1); 1211 OUT_RING (chan, 0); 1212 BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1); 1213 OUT_RING (chan, head); 1214 BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1); 1215 OUT_RING (chan, 0); 1216 BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1); 1217 OUT_RING (chan, 0); 1218 } 1219 1220 nouveau_bo_ref(new_bo, &dispnv04->image[head]); 1221 1222 ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence); 1223 if (ret) 1224 goto fail_unreserve; 1225 mutex_unlock(&cli->mutex); 1226 1227 /* Update the crtc struct and cleanup */ 1228 crtc->primary->fb = fb; 1229 1230 nouveau_bo_fence(old_bo, fence, false); 1231 ttm_bo_unreserve(&old_bo->bo); 1232 if (old_bo != new_bo) 1233 nouveau_bo_unpin(old_bo); 1234 nouveau_fence_unref(&fence); 1235 return 0; 1236 1237 fail_unreserve: 1238 drm_crtc_vblank_put(crtc); 1239 ttm_bo_unreserve(&old_bo->bo); 1240 fail_unpin: 1241 mutex_unlock(&cli->mutex); 1242 if (old_bo != new_bo) 1243 nouveau_bo_unpin(new_bo); 1244 fail_free: 1245 kfree(s); 1246 return ret; 1247 } 1248 1249 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1250 .cursor_set = nv04_crtc_cursor_set, 1251 .cursor_move = nv04_crtc_cursor_move, 1252 .gamma_set = nv_crtc_gamma_set, 1253 .set_config = drm_crtc_helper_set_config, 1254 .page_flip = nv04_crtc_page_flip, 1255 .destroy = nv_crtc_destroy, 1256 }; 1257 1258 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1259 .dpms = nv_crtc_dpms, 1260 .prepare = nv_crtc_prepare, 1261 .commit = nv_crtc_commit, 1262 .mode_set = nv_crtc_mode_set, 1263 .mode_set_base = nv04_crtc_mode_set_base, 1264 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1265 .disable = nv_crtc_disable, 1266 }; 1267 1268 static const uint32_t modeset_formats[] = { 1269 DRM_FORMAT_XRGB8888, 1270 DRM_FORMAT_RGB565, 1271 DRM_FORMAT_XRGB1555, 1272 }; 1273 1274 static struct drm_plane * 1275 create_primary_plane(struct drm_device *dev) 1276 { 1277 struct drm_plane *primary; 1278 int ret; 1279 1280 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 1281 if (primary == NULL) { 1282 DRM_DEBUG_KMS("Failed to allocate primary plane\n"); 1283 return NULL; 1284 } 1285 1286 /* possible_crtc's will be filled in later by crtc_init */ 1287 ret = drm_universal_plane_init(dev, primary, 0, 1288 &drm_primary_helper_funcs, 1289 modeset_formats, 1290 ARRAY_SIZE(modeset_formats), NULL, 1291 DRM_PLANE_TYPE_PRIMARY, NULL); 1292 if (ret) { 1293 kfree(primary); 1294 primary = NULL; 1295 } 1296 1297 return primary; 1298 } 1299 1300 int 1301 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1302 { 1303 struct nouveau_crtc *nv_crtc; 1304 int ret; 1305 1306 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1307 if (!nv_crtc) 1308 return -ENOMEM; 1309 1310 nv_crtc->lut.depth = 0; 1311 1312 nv_crtc->index = crtc_num; 1313 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1314 1315 nv_crtc->save = nv_crtc_save; 1316 nv_crtc->restore = nv_crtc_restore; 1317 1318 drm_crtc_init_with_planes(dev, &nv_crtc->base, 1319 create_primary_plane(dev), NULL, 1320 &nv04_crtc_funcs, NULL); 1321 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1322 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1323 1324 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100, 1325 TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, 1326 &nv_crtc->cursor.nvbo); 1327 if (!ret) { 1328 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); 1329 if (!ret) { 1330 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1331 if (ret) 1332 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1333 } 1334 if (ret) 1335 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1336 } 1337 1338 nv04_cursor_init(nv_crtc); 1339 1340 return 0; 1341 } 1342
Indexes created Thu Sep 25 02:09:54 GMT 2025