1 /* $NetBSD: nouveau_nvkm_engine_fifo_nv04.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_nv04.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $"); 28 29 #include "nv04.h" 30 #include "channv04.h" 31 #include "regsnv04.h" 32 33 #include <core/client.h> 34 #include <core/ramht.h> 35 #include <subdev/instmem.h> 36 #include <subdev/timer.h> 37 #include <engine/sw.h> 38 39 static const struct nv04_fifo_ramfc 40 nv04_fifo_ramfc[] = { 41 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 42 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 43 { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 44 { 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 45 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 46 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 47 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE }, 48 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 }, 49 {} 50 }; 51 52 void 53 nv04_fifo_pause(struct nvkm_fifo *base, unsigned long *pflags) 54 __acquires(fifo->base.lock) 55 { 56 struct nv04_fifo *fifo = nv04_fifo(base); 57 struct nvkm_device *device = fifo->base.engine.subdev.device; 58 unsigned long flags; 59 60 spin_lock_irqsave(&fifo->base.lock, flags); 61 *pflags = flags; 62 63 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); 64 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); 65 66 /* in some cases the puller may be left in an inconsistent state 67 * if you try to stop it while it's busy translating handles. 68 * sometimes you get a CACHE_ERROR, sometimes it just fails 69 * silently; sending incorrect instance offsets to PGRAPH after 70 * it's started up again. 71 * 72 * to avoid this, we invalidate the most recently calculated 73 * instance. 74 */ 75 nvkm_msec(device, 2000, 76 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); 77 if (!(tmp & NV04_PFIFO_CACHE1_PULL0_HASH_BUSY)) 78 break; 79 ); 80 81 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & 82 NV04_PFIFO_CACHE1_PULL0_HASH_FAILED) 83 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 84 85 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); 86 } 87 88 void 89 nv04_fifo_start(struct nvkm_fifo *base, unsigned long *pflags) 90 __releases(fifo->base.lock) 91 { 92 struct nv04_fifo *fifo = nv04_fifo(base); 93 struct nvkm_device *device = fifo->base.engine.subdev.device; 94 unsigned long flags = *pflags; 95 96 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); 97 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); 98 99 spin_unlock_irqrestore(&fifo->base.lock, flags); 100 } 101 102 static const char * 103 nv_dma_state_err(u32 state) 104 { 105 static const char * const desc[] = { 106 "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE", 107 "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK" 108 }; 109 return desc[(state >> 29) & 0x7]; 110 } 111 112 static bool 113 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) 114 { 115 struct nvkm_sw *sw = device->sw; 116 const int subc = (addr & 0x0000e000) >> 13; 117 const int mthd = (addr & 0x00001ffc); 118 const u32 mask = 0x0000000f << (subc * 4); 119 u32 engine = nvkm_rd32(device, 0x003280); 120 bool handled = false; 121 122 switch (mthd) { 123 case 0x0000 ... 0x0000: /* subchannel's engine -> software */ 124 nvkm_wr32(device, 0x003280, (engine &= ~mask)); 125 /* fall through */ 126 case 0x0180 ... 0x01fc: /* handle -> instance */ 127 data = nvkm_rd32(device, 0x003258) & 0x0000ffff; 128 /* fall through */ 129 case 0x0100 ... 0x017c: 130 case 0x0200 ... 0x1ffc: /* pass method down to sw */ 131 if (!(engine & mask) && sw) 132 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); 133 break; 134 default: 135 break; 136 } 137 138 return handled; 139 } 140 141 static void 142 nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get) 143 { 144 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 145 struct nvkm_device *device = subdev->device; 146 struct nvkm_fifo_chan *chan; 147 unsigned long flags; 148 u32 pull0 = nvkm_rd32(device, 0x003250); 149 u32 mthd, data; 150 int ptr; 151 152 /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my 153 * G80 chips, but CACHE1 isn't big enough for this much data.. Tests 154 * show that it wraps around to the start at GET=0x800.. No clue as to 155 * why.. 156 */ 157 ptr = (get & 0x7ff) >> 2; 158 159 if (device->card_type < NV_40) { 160 mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); 161 data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr)); 162 } else { 163 mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); 164 data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr)); 165 } 166 167 if (!(pull0 & 0x00000100) || 168 !nv04_fifo_swmthd(device, chid, mthd, data)) { 169 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 170 nvkm_error(subdev, "CACHE_ERROR - " 171 "ch %d [%s] subc %d mthd %04x data %08x\n", 172 chid, chan ? chan->object.client->name : "unknown", 173 (mthd >> 13) & 7, mthd & 0x1ffc, data); 174 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 175 } 176 177 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); 178 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 179 180 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 181 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1); 182 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 183 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 184 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1); 185 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0); 186 187 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 188 nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); 189 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 190 } 191 192 static void 193 nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) 194 { 195 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 196 struct nvkm_device *device = subdev->device; 197 u32 dma_get = nvkm_rd32(device, 0x003244); 198 u32 dma_put = nvkm_rd32(device, 0x003240); 199 u32 push = nvkm_rd32(device, 0x003220); 200 u32 state = nvkm_rd32(device, 0x003228); 201 struct nvkm_fifo_chan *chan; 202 unsigned long flags; 203 const char *name; 204 205 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 206 name = chan ? chan->object.client->name : "unknown"; 207 if (device->card_type == NV_50) { 208 u32 ho_get = nvkm_rd32(device, 0x003328); 209 u32 ho_put = nvkm_rd32(device, 0x003320); 210 u32 ib_get = nvkm_rd32(device, 0x003334); 211 u32 ib_put = nvkm_rd32(device, 0x003330); 212 213 nvkm_error(subdev, "DMA_PUSHER - " 214 "ch %d [%s] get %02x%08x put %02x%08x ib_get %08x " 215 "ib_put %08x state %08x (err: %s) push %08x\n", 216 chid, name, ho_get, dma_get, ho_put, dma_put, 217 ib_get, ib_put, state, nv_dma_state_err(state), 218 push); 219 220 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ 221 nvkm_wr32(device, 0x003364, 0x00000000); 222 if (dma_get != dma_put || ho_get != ho_put) { 223 nvkm_wr32(device, 0x003244, dma_put); 224 nvkm_wr32(device, 0x003328, ho_put); 225 } else 226 if (ib_get != ib_put) 227 nvkm_wr32(device, 0x003334, ib_put); 228 } else { 229 nvkm_error(subdev, "DMA_PUSHER - ch %d [%s] get %08x put %08x " 230 "state %08x (err: %s) push %08x\n", 231 chid, name, dma_get, dma_put, state, 232 nv_dma_state_err(state), push); 233 234 if (dma_get != dma_put) 235 nvkm_wr32(device, 0x003244, dma_put); 236 } 237 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 238 239 nvkm_wr32(device, 0x003228, 0x00000000); 240 nvkm_wr32(device, 0x003220, 0x00000001); 241 nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); 242 } 243 244 void 245 nv04_fifo_intr(struct nvkm_fifo *base) 246 { 247 struct nv04_fifo *fifo = nv04_fifo(base); 248 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 249 struct nvkm_device *device = subdev->device; 250 u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); 251 u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; 252 u32 reassign, chid, get, sem; 253 254 reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1; 255 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); 256 257 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & (fifo->base.nr - 1); 258 get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET); 259 260 if (stat & NV_PFIFO_INTR_CACHE_ERROR) { 261 nv04_fifo_cache_error(fifo, chid, get); 262 stat &= ~NV_PFIFO_INTR_CACHE_ERROR; 263 } 264 265 if (stat & NV_PFIFO_INTR_DMA_PUSHER) { 266 nv04_fifo_dma_pusher(fifo, chid); 267 stat &= ~NV_PFIFO_INTR_DMA_PUSHER; 268 } 269 270 if (stat & NV_PFIFO_INTR_SEMAPHORE) { 271 stat &= ~NV_PFIFO_INTR_SEMAPHORE; 272 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); 273 274 sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE); 275 nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); 276 277 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 278 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 279 } 280 281 if (device->card_type == NV_50) { 282 if (stat & 0x00000010) { 283 stat &= ~0x00000010; 284 nvkm_wr32(device, 0x002100, 0x00000010); 285 } 286 287 if (stat & 0x40000000) { 288 nvkm_wr32(device, 0x002100, 0x40000000); 289 nvkm_fifo_uevent(&fifo->base); 290 stat &= ~0x40000000; 291 } 292 } 293 294 if (stat) { 295 nvkm_warn(subdev, "intr %08x\n", stat); 296 nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); 297 nvkm_wr32(device, NV03_PFIFO_INTR_0, stat); 298 } 299 300 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); 301 } 302 303 void 304 nv04_fifo_init(struct nvkm_fifo *base) 305 { 306 struct nv04_fifo *fifo = nv04_fifo(base); 307 struct nvkm_device *device = fifo->base.engine.subdev.device; 308 struct nvkm_instmem *imem = device->imem; 309 struct nvkm_ramht *ramht = imem->ramht; 310 struct nvkm_memory *ramro = imem->ramro; 311 struct nvkm_memory *ramfc = imem->ramfc; 312 313 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 314 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 315 316 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 317 ((ramht->bits - 9) << 16) | 318 (ramht->gpuobj->addr >> 8)); 319 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 320 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); 321 322 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); 323 324 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); 325 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); 326 327 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 328 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 329 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 330 } 331 332 int 333 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, 334 int index, int nr, const struct nv04_fifo_ramfc *ramfc, 335 struct nvkm_fifo **pfifo) 336 { 337 struct nv04_fifo *fifo; 338 int ret; 339 340 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) 341 return -ENOMEM; 342 fifo->ramfc = ramfc; 343 *pfifo = &fifo->base; 344 345 ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base); 346 if (ret) 347 return ret; 348 349 set_bit(nr - 1, fifo->base.mask); /* inactive channel */ 350 return 0; 351 } 352 353 static const struct nvkm_fifo_func 354 nv04_fifo = { 355 .init = nv04_fifo_init, 356 .intr = nv04_fifo_intr, 357 .pause = nv04_fifo_pause, 358 .start = nv04_fifo_start, 359 .chan = { 360 &nv04_fifo_dma_oclass, 361 NULL 362 }, 363 }; 364 365 int 366 nv04_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) 367 { 368 return nv04_fifo_new_(&nv04_fifo, device, index, 16, 369 nv04_fifo_ramfc, pfifo); 370 } 371
Indexes created Sun Sep 21 20:09:37 GMT 2025