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      1 /*	$NetBSD: nouveau_nvkm_engine_fifo_nv10.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_nv10.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
     28 
     29 #include "nv04.h"
     30 #include "channv04.h"
     31 #include "regsnv04.h"
     32 
     33 static const struct nv04_fifo_ramfc
     34 nv10_fifo_ramfc[] = {
     35 	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
     36 	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
     37 	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
     38 	{ 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
     39 	{ 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
     40 	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
     41 	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
     42 	{ 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
     43 	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
     44 	{}
     45 };
     46 
     47 static const struct nvkm_fifo_func
     48 nv10_fifo = {
     49 	.init = nv04_fifo_init,
     50 	.intr = nv04_fifo_intr,
     51 	.pause = nv04_fifo_pause,
     52 	.start = nv04_fifo_start,
     53 	.chan = {
     54 		&nv10_fifo_dma_oclass,
     55 		NULL
     56 	},
     57 };
     58 
     59 int
     60 nv10_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
     61 {
     62 	return nv04_fifo_new_(&nv10_fifo, device, index, 32,
     63 			      nv10_fifo_ramfc, pfifo);
     64 }
     65