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      1 /*	$NetBSD: nouveau_nvkm_engine_gr_nv15.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2007 Matthieu CASTET <castet.matthieu (at) free.fr>
      5  * All Rights Reserved.
      6  *
      7  * Permission is hereby granted, free of charge, to any person obtaining a
      8  * copy of this software and associated documentation files (the "Software"),
      9  * to deal in the Software without restriction, including without limitation
     10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     11  * and/or sell copies of the Software, and to permit persons to whom the
     12  * Software is furnished to do so, subject to the following conditions:
     13  *
     14  * The above copyright notice and this permission notice (including the next
     15  * paragr) shall be included in all copies or substantial portions of the
     16  * Software.
     17  *
     18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
     22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     24  * DEALINGS IN THE SOFTWARE.
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_nv15.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
     28 
     29 #include "nv10.h"
     30 
     31 static const struct nvkm_gr_func
     32 nv15_gr = {
     33 	.init = nv10_gr_init,
     34 	.intr = nv10_gr_intr,
     35 	.tile = nv10_gr_tile,
     36 	.chan_new = nv10_gr_chan_new,
     37 	.sclass = {
     38 		{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
     39 		{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
     40 		{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
     41 		{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
     42 		{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
     43 		{ -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
     44 		{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
     45 		{ -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
     46 		{ -1, -1, 0x005f, &nv04_gr_object }, /* blit */
     47 		{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
     48 		{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
     49 		{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
     50 		{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
     51 		{ -1, -1, 0x009f, &nv04_gr_object }, /* blit */
     52 		{ -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */
     53 		{ -1, -1, 0x0094, &nv04_gr_object }, /* ttri */
     54 		{ -1, -1, 0x0095, &nv04_gr_object }, /* mtri */
     55 		{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
     56 		{}
     57 	}
     58 };
     59 
     60 int
     61 nv15_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
     62 {
     63 	return nv10_gr_new_(&nv15_gr, device, index, pgr);
     64 }
     65