1 /* $NetBSD: nouveau_nvkm_engine_gr_nv35.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: MIT 4 #include <sys/cdefs.h> 5 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_nv35.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $"); 6 7 #include "nv20.h" 8 #include "regs.h" 9 10 #include <core/gpuobj.h> 11 #include <engine/fifo.h> 12 #include <engine/fifo/chan.h> 13 14 /******************************************************************************* 15 * PGRAPH context 16 ******************************************************************************/ 17 18 static const struct nvkm_object_func 19 nv35_gr_chan = { 20 .dtor = nv20_gr_chan_dtor, 21 .init = nv20_gr_chan_init, 22 .fini = nv20_gr_chan_fini, 23 }; 24 25 static int 26 nv35_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, 27 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) 28 { 29 struct nv20_gr *gr = nv20_gr(base); 30 struct nv20_gr_chan *chan; 31 int ret, i; 32 33 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 34 return -ENOMEM; 35 nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); 36 chan->gr = gr; 37 chan->chid = fifoch->chid; 38 *pobject = &chan->object; 39 40 ret = nvkm_memory_new(gr->base.engine.subdev.device, 41 NVKM_MEM_TARGET_INST, 0x577c, 16, true, 42 &chan->inst); 43 if (ret) 44 return ret; 45 46 nvkm_kmap(chan->inst); 47 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); 48 nvkm_wo32(chan->inst, 0x040c, 0x00000101); 49 nvkm_wo32(chan->inst, 0x0420, 0x00000111); 50 nvkm_wo32(chan->inst, 0x0424, 0x00000060); 51 nvkm_wo32(chan->inst, 0x0440, 0x00000080); 52 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); 53 nvkm_wo32(chan->inst, 0x0448, 0x00000001); 54 nvkm_wo32(chan->inst, 0x045c, 0x44400000); 55 nvkm_wo32(chan->inst, 0x0488, 0xffff0000); 56 for (i = 0x04dc; i < 0x04e4; i += 4) 57 nvkm_wo32(chan->inst, i, 0x0fff0000); 58 nvkm_wo32(chan->inst, 0x04e8, 0x00011100); 59 for (i = 0x0504; i < 0x0544; i += 4) 60 nvkm_wo32(chan->inst, i, 0x07ff0000); 61 nvkm_wo32(chan->inst, 0x054c, 0x4b7fffff); 62 nvkm_wo32(chan->inst, 0x0588, 0x00000080); 63 nvkm_wo32(chan->inst, 0x058c, 0x30201000); 64 nvkm_wo32(chan->inst, 0x0590, 0x70605040); 65 nvkm_wo32(chan->inst, 0x0594, 0xb8a89888); 66 nvkm_wo32(chan->inst, 0x0598, 0xf8e8d8c8); 67 nvkm_wo32(chan->inst, 0x05ac, 0xb0000000); 68 for (i = 0x0604; i < 0x0644; i += 4) 69 nvkm_wo32(chan->inst, i, 0x00010588); 70 for (i = 0x0644; i < 0x0684; i += 4) 71 nvkm_wo32(chan->inst, i, 0x00030303); 72 for (i = 0x06c4; i < 0x0704; i += 4) 73 nvkm_wo32(chan->inst, i, 0x0008aae4); 74 for (i = 0x0704; i < 0x0744; i += 4) 75 nvkm_wo32(chan->inst, i, 0x01012000); 76 for (i = 0x0744; i < 0x0784; i += 4) 77 nvkm_wo32(chan->inst, i, 0x00080008); 78 nvkm_wo32(chan->inst, 0x0860, 0x00040000); 79 nvkm_wo32(chan->inst, 0x0864, 0x00010000); 80 for (i = 0x0868; i < 0x0878; i += 4) 81 nvkm_wo32(chan->inst, i, 0x00040004); 82 for (i = 0x1f1c; i <= 0x308c ; i += 16) { 83 nvkm_wo32(chan->inst, i + 0, 0x10700ff9); 84 nvkm_wo32(chan->inst, i + 4, 0x0436086c); 85 nvkm_wo32(chan->inst, i + 8, 0x000c001b); 86 } 87 for (i = 0x30bc; i < 0x30cc; i += 4) 88 nvkm_wo32(chan->inst, i, 0x0000ffff); 89 nvkm_wo32(chan->inst, 0x3450, 0x3f800000); 90 nvkm_wo32(chan->inst, 0x380c, 0x3f800000); 91 nvkm_wo32(chan->inst, 0x3820, 0x3f800000); 92 nvkm_wo32(chan->inst, 0x384c, 0x40000000); 93 nvkm_wo32(chan->inst, 0x3850, 0x3f800000); 94 nvkm_wo32(chan->inst, 0x3854, 0x3f000000); 95 nvkm_wo32(chan->inst, 0x385c, 0x40000000); 96 nvkm_wo32(chan->inst, 0x3860, 0x3f800000); 97 nvkm_wo32(chan->inst, 0x3868, 0xbf800000); 98 nvkm_wo32(chan->inst, 0x3870, 0xbf800000); 99 nvkm_done(chan->inst); 100 return 0; 101 } 102 103 /******************************************************************************* 104 * PGRAPH engine/subdev functions 105 ******************************************************************************/ 106 107 static const struct nvkm_gr_func 108 nv35_gr = { 109 .dtor = nv20_gr_dtor, 110 .oneinit = nv20_gr_oneinit, 111 .init = nv30_gr_init, 112 .intr = nv20_gr_intr, 113 .tile = nv20_gr_tile, 114 .chan_new = nv35_gr_chan_new, 115 .sclass = { 116 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ 117 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ 118 { -1, -1, 0x0030, &nv04_gr_object }, /* null */ 119 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ 120 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ 121 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ 122 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ 123 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ 124 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ 125 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ 126 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ 127 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ 128 { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ 129 { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ 130 { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ 131 { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ 132 { -1, -1, 0x0497, &nv04_gr_object }, /* rankine */ 133 { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */ 134 {} 135 } 136 }; 137 138 int 139 nv35_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 140 { 141 return nv20_gr_new_(&nv35_gr, device, index, pgr); 142 } 143
Indexes created Sun Sep 28 07:09:56 GMT 2025