1 /* $NetBSD: nouveau_nvkm_engine_fifo_dmanv40.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_dmanv40.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $"); 28 29 #include "channv04.h" 30 #include "regsnv04.h" 31 32 #include <core/client.h> 33 #include <core/ramht.h> 34 #include <subdev/instmem.h> 35 36 #include <nvif/class.h> 37 #include <nvif/cl006b.h> 38 #include <nvif/unpack.h> 39 40 static bool 41 nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) 42 { 43 switch (engine->subdev.index) { 44 case NVKM_ENGINE_DMAOBJ: 45 case NVKM_ENGINE_SW: 46 return false; 47 case NVKM_ENGINE_GR: 48 *reg = 0x0032e0; 49 *ctx = 0x38; 50 return true; 51 case NVKM_ENGINE_MPEG: 52 if (engine->subdev.device->chipset < 0x44) 53 return false; 54 *reg = 0x00330c; 55 *ctx = 0x54; 56 return true; 57 default: 58 WARN_ON(1); 59 return false; 60 } 61 } 62 63 static int 64 nv40_fifo_dma_engine_fini(struct nvkm_fifo_chan *base, 65 struct nvkm_engine *engine, bool suspend) 66 { 67 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 68 struct nv04_fifo *fifo = chan->fifo; 69 struct nvkm_device *device = fifo->base.engine.subdev.device; 70 struct nvkm_instmem *imem = device->imem; 71 unsigned long flags; 72 u32 reg, ctx; 73 int chid; 74 75 if (!nv40_fifo_dma_engine(engine, ®, &ctx)) 76 return 0; 77 78 spin_lock_irqsave(&fifo->base.lock, flags); 79 nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); 80 81 chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); 82 if (chid == chan->base.chid) 83 nvkm_wr32(device, reg, 0x00000000); 84 nvkm_kmap(imem->ramfc); 85 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); 86 nvkm_done(imem->ramfc); 87 88 nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); 89 spin_unlock_irqrestore(&fifo->base.lock, flags); 90 return 0; 91 } 92 93 static int 94 nv40_fifo_dma_engine_init(struct nvkm_fifo_chan *base, 95 struct nvkm_engine *engine) 96 { 97 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 98 struct nv04_fifo *fifo = chan->fifo; 99 struct nvkm_device *device = fifo->base.engine.subdev.device; 100 struct nvkm_instmem *imem = device->imem; 101 unsigned long flags; 102 u32 inst, reg, ctx; 103 int chid; 104 105 if (!nv40_fifo_dma_engine(engine, ®, &ctx)) 106 return 0; 107 inst = chan->engn[engine->subdev.index]->addr >> 4; 108 109 spin_lock_irqsave(&fifo->base.lock, flags); 110 nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); 111 112 chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); 113 if (chid == chan->base.chid) 114 nvkm_wr32(device, reg, inst); 115 nvkm_kmap(imem->ramfc); 116 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst); 117 nvkm_done(imem->ramfc); 118 119 nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); 120 spin_unlock_irqrestore(&fifo->base.lock, flags); 121 return 0; 122 } 123 124 static void 125 nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base, 126 struct nvkm_engine *engine) 127 { 128 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 129 nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); 130 } 131 132 static int 133 nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base, 134 struct nvkm_engine *engine, 135 struct nvkm_object *object) 136 { 137 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 138 const int engn = engine->subdev.index; 139 u32 reg, ctx; 140 141 if (!nv40_fifo_dma_engine(engine, ®, &ctx)) 142 return 0; 143 144 return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); 145 } 146 147 static int 148 nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, 149 struct nvkm_object *object) 150 { 151 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 152 struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; 153 u32 context = chan->base.chid << 23; 154 u32 handle = object->handle; 155 int hash; 156 157 switch (object->engine->subdev.index) { 158 case NVKM_ENGINE_DMAOBJ: 159 case NVKM_ENGINE_SW : context |= 0x00000000; break; 160 case NVKM_ENGINE_GR : context |= 0x00100000; break; 161 case NVKM_ENGINE_MPEG : context |= 0x00200000; break; 162 default: 163 WARN_ON(1); 164 return -EINVAL; 165 } 166 167 mutex_lock(&chan->fifo->base.engine.subdev.mutex); 168 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, 169 handle, context); 170 mutex_unlock(&chan->fifo->base.engine.subdev.mutex); 171 return hash; 172 } 173 174 static const struct nvkm_fifo_chan_func 175 nv40_fifo_dma_func = { 176 .dtor = nv04_fifo_dma_dtor, 177 .init = nv04_fifo_dma_init, 178 .fini = nv04_fifo_dma_fini, 179 .engine_ctor = nv40_fifo_dma_engine_ctor, 180 .engine_dtor = nv40_fifo_dma_engine_dtor, 181 .engine_init = nv40_fifo_dma_engine_init, 182 .engine_fini = nv40_fifo_dma_engine_fini, 183 .object_ctor = nv40_fifo_dma_object_ctor, 184 .object_dtor = nv04_fifo_dma_object_dtor, 185 }; 186 187 static int 188 nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, 189 void *data, u32 size, struct nvkm_object **pobject) 190 { 191 struct nvkm_object *parent = oclass->parent; 192 union { 193 struct nv03_channel_dma_v0 v0; 194 } *args = data; 195 struct nv04_fifo *fifo = nv04_fifo(base); 196 struct nv04_fifo_chan *chan = NULL; 197 struct nvkm_device *device = fifo->base.engine.subdev.device; 198 struct nvkm_instmem *imem = device->imem; 199 int ret = -ENOSYS; 200 201 nvif_ioctl(parent, "create channel dma size %d\n", size); 202 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 203 nvif_ioctl(parent, "create channel dma vers %d pushbuf %"PRIx64" " 204 "offset %08x\n", args->v0.version, 205 args->v0.pushbuf, args->v0.offset); 206 if (!args->v0.pushbuf) 207 return -EINVAL; 208 } else 209 return ret; 210 211 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 212 return -ENOMEM; 213 *pobject = &chan->base.object; 214 215 ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base, 216 0x1000, 0x1000, false, 0, args->v0.pushbuf, 217 (1ULL << NVKM_ENGINE_DMAOBJ) | 218 (1ULL << NVKM_ENGINE_GR) | 219 (1ULL << NVKM_ENGINE_MPEG) | 220 (1ULL << NVKM_ENGINE_SW), 221 0, 0xc00000, 0x1000, oclass, &chan->base); 222 chan->fifo = fifo; 223 if (ret) 224 return ret; 225 226 args->v0.chid = chan->base.chid; 227 chan->ramfc = chan->base.chid * 128; 228 229 nvkm_kmap(imem->ramfc); 230 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); 231 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); 232 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); 233 nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | 234 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 235 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 236 #ifdef __BIG_ENDIAN 237 NV_PFIFO_CACHE1_BIG_ENDIAN | 238 #endif 239 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); 240 nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff); 241 nvkm_done(imem->ramfc); 242 return 0; 243 } 244 245 const struct nvkm_fifo_chan_oclass 246 nv40_fifo_dma_oclass = { 247 .base.oclass = NV40_CHANNEL_DMA, 248 .base.minver = 0, 249 .base.maxver = 0, 250 .ctor = nv40_fifo_dma_new, 251 }; 252
Indexes created Mon Sep 29 03:10:08 GMT 2025