1 /* $NetBSD: nouveau_nvkm_engine_gr_ctxnv40.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2009 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26 27 /* NVIDIA context programs handle a number of other conditions which are 28 * not implemented in our versions. It's not clear why NVIDIA context 29 * programs have this code, nor whether it's strictly necessary for 30 * correct operation. We'll implement additional handling if/when we 31 * discover it's necessary. 32 * 33 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" 34 * flag is set, this gets saved into the context. 35 * - On context save, the context program for all cards load nsource 36 * into a flag register and check for ILLEGAL_MTHD. If it's set, 37 * opcode 0x60000d is called before resuming normal operation. 38 * - Some context programs check more conditions than the above. NV44 39 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) 40 * and calls 0x60000d before resuming normal operation. 41 * - At the very beginning of NVIDIA's context programs, flag 9 is checked 42 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared 43 * and then the ctxprog is aborted. It looks like a complicated NOP, 44 * its purpose is unknown. 45 * - In the section of code that loads the per-vs state, NVIDIA check 46 * flag 10. If it's set, they only transfer the small 0x300 byte block 47 * of state + the state for a single vs as opposed to the state for 48 * all vs units. It doesn't seem likely that it'll occur in normal 49 * operation, especially seeing as it appears NVIDIA may have screwed 50 * up the ctxprogs for some cards and have an invalid instruction 51 * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. 52 * - There's a number of places where context offset 0 (where we place 53 * the PRAMIN offset of the context) is loaded into either 0x408000, 54 * 0x408004 or 0x408008. Not sure what's up there either. 55 * - The ctxprogs for some cards save 0x400a00 again during the cleanup 56 * path for auto-loadctx. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxnv40.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $"); 61 62 #define CP_FLAG_CLEAR 0 63 #define CP_FLAG_SET 1 64 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) 65 #define CP_FLAG_SWAP_DIRECTION_LOAD 0 66 #define CP_FLAG_SWAP_DIRECTION_SAVE 1 67 #define CP_FLAG_USER_SAVE ((0 * 32) + 5) 68 #define CP_FLAG_USER_SAVE_NOT_PENDING 0 69 #define CP_FLAG_USER_SAVE_PENDING 1 70 #define CP_FLAG_USER_LOAD ((0 * 32) + 6) 71 #define CP_FLAG_USER_LOAD_NOT_PENDING 0 72 #define CP_FLAG_USER_LOAD_PENDING 1 73 #define CP_FLAG_STATUS ((3 * 32) + 0) 74 #define CP_FLAG_STATUS_IDLE 0 75 #define CP_FLAG_STATUS_BUSY 1 76 #define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) 77 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 78 #define CP_FLAG_AUTO_SAVE_PENDING 1 79 #define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) 80 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 81 #define CP_FLAG_AUTO_LOAD_PENDING 1 82 #define CP_FLAG_UNK54 ((3 * 32) + 6) 83 #define CP_FLAG_UNK54_CLEAR 0 84 #define CP_FLAG_UNK54_SET 1 85 #define CP_FLAG_ALWAYS ((3 * 32) + 8) 86 #define CP_FLAG_ALWAYS_FALSE 0 87 #define CP_FLAG_ALWAYS_TRUE 1 88 #define CP_FLAG_UNK57 ((3 * 32) + 9) 89 #define CP_FLAG_UNK57_CLEAR 0 90 #define CP_FLAG_UNK57_SET 1 91 92 #define CP_CTX 0x00100000 93 #define CP_CTX_COUNT 0x000fc000 94 #define CP_CTX_COUNT_SHIFT 14 95 #define CP_CTX_REG 0x00003fff 96 #define CP_LOAD_SR 0x00200000 97 #define CP_LOAD_SR_VALUE 0x000fffff 98 #define CP_BRA 0x00400000 99 #define CP_BRA_IP 0x0000ff00 100 #define CP_BRA_IP_SHIFT 8 101 #define CP_BRA_IF_CLEAR 0x00000080 102 #define CP_BRA_FLAG 0x0000007f 103 #define CP_WAIT 0x00500000 104 #define CP_WAIT_SET 0x00000080 105 #define CP_WAIT_FLAG 0x0000007f 106 #define CP_SET 0x00700000 107 #define CP_SET_1 0x00000080 108 #define CP_SET_FLAG 0x0000007f 109 #define CP_NEXT_TO_SWAP 0x00600007 110 #define CP_NEXT_TO_CURRENT 0x00600009 111 #define CP_SET_CONTEXT_POINTER 0x0060000a 112 #define CP_END 0x0060000e 113 #define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ 114 #define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ 115 #define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ 116 117 #include "ctxnv40.h" 118 #include "nv40.h" 119 120 /* TODO: 121 * - get vs count from 0x1540 122 */ 123 124 static int 125 nv40_gr_vs_count(struct nvkm_device *device) 126 { 127 128 switch (device->chipset) { 129 case 0x47: 130 case 0x49: 131 case 0x4b: 132 return 8; 133 case 0x40: 134 return 6; 135 case 0x41: 136 case 0x42: 137 return 5; 138 case 0x43: 139 case 0x44: 140 case 0x46: 141 case 0x4a: 142 return 3; 143 case 0x4c: 144 case 0x4e: 145 case 0x67: 146 default: 147 return 1; 148 } 149 } 150 151 152 enum cp_label { 153 cp_check_load = 1, 154 cp_setup_auto_load, 155 cp_setup_load, 156 cp_setup_save, 157 cp_swap_state, 158 cp_swap_state3d_3_is_save, 159 cp_prepare_exit, 160 cp_exit, 161 }; 162 163 static void 164 nv40_gr_construct_general(struct nvkm_grctx *ctx) 165 { 166 struct nvkm_device *device = ctx->device; 167 int i; 168 169 cp_ctx(ctx, 0x4000a4, 1); 170 gr_def(ctx, 0x4000a4, 0x00000008); 171 cp_ctx(ctx, 0x400144, 58); 172 gr_def(ctx, 0x400144, 0x00000001); 173 cp_ctx(ctx, 0x400314, 1); 174 gr_def(ctx, 0x400314, 0x00000000); 175 cp_ctx(ctx, 0x400400, 10); 176 cp_ctx(ctx, 0x400480, 10); 177 cp_ctx(ctx, 0x400500, 19); 178 gr_def(ctx, 0x400514, 0x00040000); 179 gr_def(ctx, 0x400524, 0x55555555); 180 gr_def(ctx, 0x400528, 0x55555555); 181 gr_def(ctx, 0x40052c, 0x55555555); 182 gr_def(ctx, 0x400530, 0x55555555); 183 cp_ctx(ctx, 0x400560, 6); 184 gr_def(ctx, 0x400568, 0x0000ffff); 185 gr_def(ctx, 0x40056c, 0x0000ffff); 186 cp_ctx(ctx, 0x40057c, 5); 187 cp_ctx(ctx, 0x400710, 3); 188 gr_def(ctx, 0x400710, 0x20010001); 189 gr_def(ctx, 0x400714, 0x0f73ef00); 190 cp_ctx(ctx, 0x400724, 1); 191 gr_def(ctx, 0x400724, 0x02008821); 192 cp_ctx(ctx, 0x400770, 3); 193 if (device->chipset == 0x40) { 194 cp_ctx(ctx, 0x400814, 4); 195 cp_ctx(ctx, 0x400828, 5); 196 cp_ctx(ctx, 0x400840, 5); 197 gr_def(ctx, 0x400850, 0x00000040); 198 cp_ctx(ctx, 0x400858, 4); 199 gr_def(ctx, 0x400858, 0x00000040); 200 gr_def(ctx, 0x40085c, 0x00000040); 201 gr_def(ctx, 0x400864, 0x80000000); 202 cp_ctx(ctx, 0x40086c, 9); 203 gr_def(ctx, 0x40086c, 0x80000000); 204 gr_def(ctx, 0x400870, 0x80000000); 205 gr_def(ctx, 0x400874, 0x80000000); 206 gr_def(ctx, 0x400878, 0x80000000); 207 gr_def(ctx, 0x400888, 0x00000040); 208 gr_def(ctx, 0x40088c, 0x80000000); 209 cp_ctx(ctx, 0x4009c0, 8); 210 gr_def(ctx, 0x4009cc, 0x80000000); 211 gr_def(ctx, 0x4009dc, 0x80000000); 212 } else { 213 cp_ctx(ctx, 0x400840, 20); 214 if (nv44_gr_class(ctx->device)) { 215 for (i = 0; i < 8; i++) 216 gr_def(ctx, 0x400860 + (i * 4), 0x00000001); 217 } 218 gr_def(ctx, 0x400880, 0x00000040); 219 gr_def(ctx, 0x400884, 0x00000040); 220 gr_def(ctx, 0x400888, 0x00000040); 221 cp_ctx(ctx, 0x400894, 11); 222 gr_def(ctx, 0x400894, 0x00000040); 223 if (!nv44_gr_class(ctx->device)) { 224 for (i = 0; i < 8; i++) 225 gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); 226 } 227 cp_ctx(ctx, 0x4008e0, 2); 228 cp_ctx(ctx, 0x4008f8, 2); 229 if (device->chipset == 0x4c || 230 (device->chipset & 0xf0) == 0x60) 231 cp_ctx(ctx, 0x4009f8, 1); 232 } 233 cp_ctx(ctx, 0x400a00, 73); 234 gr_def(ctx, 0x400b0c, 0x0b0b0b0c); 235 cp_ctx(ctx, 0x401000, 4); 236 cp_ctx(ctx, 0x405004, 1); 237 switch (device->chipset) { 238 case 0x47: 239 case 0x49: 240 case 0x4b: 241 cp_ctx(ctx, 0x403448, 1); 242 gr_def(ctx, 0x403448, 0x00001010); 243 break; 244 default: 245 cp_ctx(ctx, 0x403440, 1); 246 switch (device->chipset) { 247 case 0x40: 248 gr_def(ctx, 0x403440, 0x00000010); 249 break; 250 case 0x44: 251 case 0x46: 252 case 0x4a: 253 gr_def(ctx, 0x403440, 0x00003010); 254 break; 255 case 0x41: 256 case 0x42: 257 case 0x43: 258 case 0x4c: 259 case 0x4e: 260 case 0x67: 261 default: 262 gr_def(ctx, 0x403440, 0x00001010); 263 break; 264 } 265 break; 266 } 267 } 268 269 static void 270 nv40_gr_construct_state3d(struct nvkm_grctx *ctx) 271 { 272 struct nvkm_device *device = ctx->device; 273 int i; 274 275 if (device->chipset == 0x40) { 276 cp_ctx(ctx, 0x401880, 51); 277 gr_def(ctx, 0x401940, 0x00000100); 278 } else 279 if (device->chipset == 0x46 || device->chipset == 0x47 || 280 device->chipset == 0x49 || device->chipset == 0x4b) { 281 cp_ctx(ctx, 0x401880, 32); 282 for (i = 0; i < 16; i++) 283 gr_def(ctx, 0x401880 + (i * 4), 0x00000111); 284 if (device->chipset == 0x46) 285 cp_ctx(ctx, 0x401900, 16); 286 cp_ctx(ctx, 0x401940, 3); 287 } 288 cp_ctx(ctx, 0x40194c, 18); 289 gr_def(ctx, 0x401954, 0x00000111); 290 gr_def(ctx, 0x401958, 0x00080060); 291 gr_def(ctx, 0x401974, 0x00000080); 292 gr_def(ctx, 0x401978, 0xffff0000); 293 gr_def(ctx, 0x40197c, 0x00000001); 294 gr_def(ctx, 0x401990, 0x46400000); 295 if (device->chipset == 0x40) { 296 cp_ctx(ctx, 0x4019a0, 2); 297 cp_ctx(ctx, 0x4019ac, 5); 298 } else { 299 cp_ctx(ctx, 0x4019a0, 1); 300 cp_ctx(ctx, 0x4019b4, 3); 301 } 302 gr_def(ctx, 0x4019bc, 0xffff0000); 303 switch (device->chipset) { 304 case 0x46: 305 case 0x47: 306 case 0x49: 307 case 0x4b: 308 cp_ctx(ctx, 0x4019c0, 18); 309 for (i = 0; i < 16; i++) 310 gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); 311 break; 312 } 313 cp_ctx(ctx, 0x401a08, 8); 314 gr_def(ctx, 0x401a10, 0x0fff0000); 315 gr_def(ctx, 0x401a14, 0x0fff0000); 316 gr_def(ctx, 0x401a1c, 0x00011100); 317 cp_ctx(ctx, 0x401a2c, 4); 318 cp_ctx(ctx, 0x401a44, 26); 319 for (i = 0; i < 16; i++) 320 gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); 321 gr_def(ctx, 0x401a8c, 0x4b7fffff); 322 if (device->chipset == 0x40) { 323 cp_ctx(ctx, 0x401ab8, 3); 324 } else { 325 cp_ctx(ctx, 0x401ab8, 1); 326 cp_ctx(ctx, 0x401ac0, 1); 327 } 328 cp_ctx(ctx, 0x401ad0, 8); 329 gr_def(ctx, 0x401ad0, 0x30201000); 330 gr_def(ctx, 0x401ad4, 0x70605040); 331 gr_def(ctx, 0x401ad8, 0xb8a89888); 332 gr_def(ctx, 0x401adc, 0xf8e8d8c8); 333 cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); 334 gr_def(ctx, 0x401b10, 0x40100000); 335 cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); 336 gr_def(ctx, 0x401b28, device->chipset == 0x40 ? 337 0x00000004 : 0x00000000); 338 cp_ctx(ctx, 0x401b30, 25); 339 gr_def(ctx, 0x401b34, 0x0000ffff); 340 gr_def(ctx, 0x401b68, 0x435185d6); 341 gr_def(ctx, 0x401b6c, 0x2155b699); 342 gr_def(ctx, 0x401b70, 0xfedcba98); 343 gr_def(ctx, 0x401b74, 0x00000098); 344 gr_def(ctx, 0x401b84, 0xffffffff); 345 gr_def(ctx, 0x401b88, 0x00ff7000); 346 gr_def(ctx, 0x401b8c, 0x0000ffff); 347 if (device->chipset != 0x44 && device->chipset != 0x4a && 348 device->chipset != 0x4e) 349 cp_ctx(ctx, 0x401b94, 1); 350 cp_ctx(ctx, 0x401b98, 8); 351 gr_def(ctx, 0x401b9c, 0x00ff0000); 352 cp_ctx(ctx, 0x401bc0, 9); 353 gr_def(ctx, 0x401be0, 0x00ffff00); 354 cp_ctx(ctx, 0x401c00, 192); 355 for (i = 0; i < 16; i++) { /* fragment texture units */ 356 gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); 357 gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); 358 gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); 359 gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); 360 gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); 361 gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); 362 } 363 for (i = 0; i < 4; i++) { /* vertex texture units */ 364 gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); 365 gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); 366 gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); 367 gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); 368 } 369 cp_ctx(ctx, 0x400f5c, 3); 370 gr_def(ctx, 0x400f5c, 0x00000002); 371 cp_ctx(ctx, 0x400f84, 1); 372 } 373 374 static void 375 nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx) 376 { 377 struct nvkm_device *device = ctx->device; 378 int i; 379 380 cp_ctx(ctx, 0x402000, 1); 381 cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); 382 switch (device->chipset) { 383 case 0x40: 384 gr_def(ctx, 0x402404, 0x00000001); 385 break; 386 case 0x4c: 387 case 0x4e: 388 case 0x67: 389 gr_def(ctx, 0x402404, 0x00000020); 390 break; 391 case 0x46: 392 case 0x49: 393 case 0x4b: 394 gr_def(ctx, 0x402404, 0x00000421); 395 break; 396 default: 397 gr_def(ctx, 0x402404, 0x00000021); 398 } 399 if (device->chipset != 0x40) 400 gr_def(ctx, 0x402408, 0x030c30c3); 401 switch (device->chipset) { 402 case 0x44: 403 case 0x46: 404 case 0x4a: 405 case 0x4c: 406 case 0x4e: 407 case 0x67: 408 cp_ctx(ctx, 0x402440, 1); 409 gr_def(ctx, 0x402440, 0x00011001); 410 break; 411 default: 412 break; 413 } 414 cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); 415 gr_def(ctx, 0x402488, 0x3e020200); 416 gr_def(ctx, 0x40248c, 0x00ffffff); 417 switch (device->chipset) { 418 case 0x40: 419 gr_def(ctx, 0x402490, 0x60103f00); 420 break; 421 case 0x47: 422 gr_def(ctx, 0x402490, 0x40103f00); 423 break; 424 case 0x41: 425 case 0x42: 426 case 0x49: 427 case 0x4b: 428 gr_def(ctx, 0x402490, 0x20103f00); 429 break; 430 default: 431 gr_def(ctx, 0x402490, 0x0c103f00); 432 break; 433 } 434 gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? 435 0x00020000 : 0x00040000); 436 cp_ctx(ctx, 0x402500, 31); 437 gr_def(ctx, 0x402530, 0x00008100); 438 if (device->chipset == 0x40) 439 cp_ctx(ctx, 0x40257c, 6); 440 cp_ctx(ctx, 0x402594, 16); 441 cp_ctx(ctx, 0x402800, 17); 442 gr_def(ctx, 0x402800, 0x00000001); 443 switch (device->chipset) { 444 case 0x47: 445 case 0x49: 446 case 0x4b: 447 cp_ctx(ctx, 0x402864, 1); 448 gr_def(ctx, 0x402864, 0x00001001); 449 cp_ctx(ctx, 0x402870, 3); 450 gr_def(ctx, 0x402878, 0x00000003); 451 if (device->chipset != 0x47) { /* belong at end!! */ 452 cp_ctx(ctx, 0x402900, 1); 453 cp_ctx(ctx, 0x402940, 1); 454 cp_ctx(ctx, 0x402980, 1); 455 cp_ctx(ctx, 0x4029c0, 1); 456 cp_ctx(ctx, 0x402a00, 1); 457 cp_ctx(ctx, 0x402a40, 1); 458 cp_ctx(ctx, 0x402a80, 1); 459 cp_ctx(ctx, 0x402ac0, 1); 460 } 461 break; 462 case 0x40: 463 cp_ctx(ctx, 0x402844, 1); 464 gr_def(ctx, 0x402844, 0x00000001); 465 cp_ctx(ctx, 0x402850, 1); 466 break; 467 default: 468 cp_ctx(ctx, 0x402844, 1); 469 gr_def(ctx, 0x402844, 0x00001001); 470 cp_ctx(ctx, 0x402850, 2); 471 gr_def(ctx, 0x402854, 0x00000003); 472 break; 473 } 474 475 cp_ctx(ctx, 0x402c00, 4); 476 gr_def(ctx, 0x402c00, device->chipset == 0x40 ? 477 0x80800001 : 0x00888001); 478 switch (device->chipset) { 479 case 0x47: 480 case 0x49: 481 case 0x4b: 482 cp_ctx(ctx, 0x402c20, 40); 483 for (i = 0; i < 32; i++) 484 gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); 485 cp_ctx(ctx, 0x4030b8, 13); 486 gr_def(ctx, 0x4030dc, 0x00000005); 487 gr_def(ctx, 0x4030e8, 0x0000ffff); 488 break; 489 default: 490 cp_ctx(ctx, 0x402c10, 4); 491 if (device->chipset == 0x40) 492 cp_ctx(ctx, 0x402c20, 36); 493 else 494 if (device->chipset <= 0x42) 495 cp_ctx(ctx, 0x402c20, 24); 496 else 497 if (device->chipset <= 0x4a) 498 cp_ctx(ctx, 0x402c20, 16); 499 else 500 cp_ctx(ctx, 0x402c20, 8); 501 cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); 502 gr_def(ctx, 0x402cd4, 0x00000005); 503 if (device->chipset != 0x40) 504 gr_def(ctx, 0x402ce0, 0x0000ffff); 505 break; 506 } 507 508 cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); 509 cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); 510 cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device)); 511 for (i = 0; i < nv40_gr_vs_count(ctx->device); i++) 512 gr_def(ctx, 0x403420 + (i * 4), 0x00005555); 513 514 if (device->chipset != 0x40) { 515 cp_ctx(ctx, 0x403600, 1); 516 gr_def(ctx, 0x403600, 0x00000001); 517 } 518 cp_ctx(ctx, 0x403800, 1); 519 520 cp_ctx(ctx, 0x403c18, 1); 521 gr_def(ctx, 0x403c18, 0x00000001); 522 switch (device->chipset) { 523 case 0x46: 524 case 0x47: 525 case 0x49: 526 case 0x4b: 527 cp_ctx(ctx, 0x405018, 1); 528 gr_def(ctx, 0x405018, 0x08e00001); 529 cp_ctx(ctx, 0x405c24, 1); 530 gr_def(ctx, 0x405c24, 0x000e3000); 531 break; 532 } 533 if (device->chipset != 0x4e) 534 cp_ctx(ctx, 0x405800, 11); 535 cp_ctx(ctx, 0x407000, 1); 536 } 537 538 static void 539 nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx) 540 { 541 int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684; 542 543 cp_out (ctx, 0x300000); 544 cp_lsr (ctx, len - 4); 545 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); 546 cp_lsr (ctx, len); 547 cp_name(ctx, cp_swap_state3d_3_is_save); 548 cp_out (ctx, 0x800001); 549 550 ctx->ctxvals_pos += len; 551 } 552 553 static void 554 nv40_gr_construct_shader(struct nvkm_grctx *ctx) 555 { 556 struct nvkm_device *device = ctx->device; 557 struct nvkm_gpuobj *obj = ctx->data; 558 int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; 559 int offset, i; 560 561 vs_nr = nv40_gr_vs_count(ctx->device); 562 vs_nr_b0 = 363; 563 vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; 564 if (device->chipset == 0x40) { 565 b0_offset = 0x2200/4; /* 33a0 */ 566 b1_offset = 0x55a0/4; /* 1500 */ 567 vs_len = 0x6aa0/4; 568 } else 569 if (device->chipset == 0x41 || device->chipset == 0x42) { 570 b0_offset = 0x2200/4; /* 2200 */ 571 b1_offset = 0x4400/4; /* 0b00 */ 572 vs_len = 0x4f00/4; 573 } else { 574 b0_offset = 0x1d40/4; /* 2200 */ 575 b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ 576 vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4; 577 } 578 579 cp_lsr(ctx, vs_len * vs_nr + 0x300/4); 580 cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041); 581 582 offset = ctx->ctxvals_pos; 583 ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); 584 585 if (ctx->mode != NVKM_GRCTX_VALS) 586 return; 587 588 offset += 0x0280/4; 589 for (i = 0; i < 16; i++, offset += 2) 590 nvkm_wo32(obj, offset * 4, 0x3f800000); 591 592 for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { 593 for (i = 0; i < vs_nr_b0 * 6; i += 6) 594 nvkm_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); 595 for (i = 0; i < vs_nr_b1 * 4; i += 4) 596 nvkm_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); 597 } 598 } 599 600 static void 601 nv40_grctx_generate(struct nvkm_grctx *ctx) 602 { 603 /* decide whether we're loading/unloading the context */ 604 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); 605 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); 606 607 cp_name(ctx, cp_check_load); 608 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); 609 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); 610 cp_bra (ctx, ALWAYS, TRUE, cp_exit); 611 612 /* setup for context load */ 613 cp_name(ctx, cp_setup_auto_load); 614 cp_wait(ctx, STATUS, IDLE); 615 cp_out (ctx, CP_NEXT_TO_SWAP); 616 cp_name(ctx, cp_setup_load); 617 cp_wait(ctx, STATUS, IDLE); 618 cp_set (ctx, SWAP_DIRECTION, LOAD); 619 cp_out (ctx, 0x00910880); /* ?? */ 620 cp_out (ctx, 0x00901ffe); /* ?? */ 621 cp_out (ctx, 0x01940000); /* ?? */ 622 cp_lsr (ctx, 0x20); 623 cp_out (ctx, 0x0060000b); /* ?? */ 624 cp_wait(ctx, UNK57, CLEAR); 625 cp_out (ctx, 0x0060000c); /* ?? */ 626 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); 627 628 /* setup for context save */ 629 cp_name(ctx, cp_setup_save); 630 cp_set (ctx, SWAP_DIRECTION, SAVE); 631 632 /* general PGRAPH state */ 633 cp_name(ctx, cp_swap_state); 634 cp_pos (ctx, 0x00020/4); 635 nv40_gr_construct_general(ctx); 636 cp_wait(ctx, STATUS, IDLE); 637 638 /* 3D state, block 1 */ 639 cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); 640 nv40_gr_construct_state3d(ctx); 641 cp_wait(ctx, STATUS, IDLE); 642 643 /* 3D state, block 2 */ 644 nv40_gr_construct_state3d_2(ctx); 645 646 /* Some other block of "random" state */ 647 nv40_gr_construct_state3d_3(ctx); 648 649 /* Per-vertex shader state */ 650 cp_pos (ctx, ctx->ctxvals_pos); 651 nv40_gr_construct_shader(ctx); 652 653 /* pre-exit state updates */ 654 cp_name(ctx, cp_prepare_exit); 655 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); 656 cp_bra (ctx, USER_SAVE, PENDING, cp_exit); 657 cp_out (ctx, CP_NEXT_TO_CURRENT); 658 659 cp_name(ctx, cp_exit); 660 cp_set (ctx, USER_SAVE, NOT_PENDING); 661 cp_set (ctx, USER_LOAD, NOT_PENDING); 662 cp_out (ctx, CP_END); 663 } 664 665 void 666 nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem) 667 { 668 nv40_grctx_generate(&(struct nvkm_grctx) { 669 .device = device, 670 .mode = NVKM_GRCTX_VALS, 671 .data = mem, 672 }); 673 } 674 675 int 676 nv40_grctx_init(struct nvkm_device *device, u32 *size) 677 { 678 u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; 679 struct nvkm_grctx ctx = { 680 .device = device, 681 .mode = NVKM_GRCTX_PROG, 682 .ucode = ctxprog, 683 .ctxprog_max = 256, 684 }; 685 686 if (!ctxprog) 687 return -ENOMEM; 688 689 nv40_grctx_generate(&ctx); 690 691 nvkm_wr32(device, 0x400324, 0); 692 for (i = 0; i < ctx.ctxprog_len; i++) 693 nvkm_wr32(device, 0x400328, ctxprog[i]); 694 *size = ctx.ctxvals_pos * 4; 695 696 kfree(ctxprog); 697 return 0; 698 } 699
Indexes created Sat Sep 20 22:09:52 GMT 2025