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      1 /*	$NetBSD: nouveau_nvkm_engine_gr_nv44.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_nv44.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
     28 
     29 #include "nv40.h"
     30 #include "regs.h"
     31 
     32 #include <subdev/fb.h>
     33 #include <engine/fifo.h>
     34 
     35 static void
     36 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
     37 {
     38 	struct nv40_gr *gr = nv40_gr(base);
     39 	struct nvkm_device *device = gr->base.engine.subdev.device;
     40 	struct nvkm_fifo *fifo = device->fifo;
     41 	unsigned long flags;
     42 
     43 	nvkm_fifo_pause(fifo, &flags);
     44 	nv04_gr_idle(&gr->base);
     45 
     46 	switch (device->chipset) {
     47 	case 0x44:
     48 	case 0x4a:
     49 		nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
     50 		nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
     51 		nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
     52 		break;
     53 	case 0x46:
     54 	case 0x4c:
     55 	case 0x63:
     56 	case 0x67:
     57 	case 0x68:
     58 		nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
     59 		nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
     60 		nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
     61 		nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
     62 		nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
     63 		nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
     64 		break;
     65 	case 0x4e:
     66 		nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
     67 		nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
     68 		nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
     69 		nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
     70 		nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
     71 		nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
     72 		break;
     73 	default:
     74 		WARN_ON(1);
     75 		break;
     76 	}
     77 
     78 	nvkm_fifo_start(fifo, &flags);
     79 }
     80 
     81 static const struct nvkm_gr_func
     82 nv44_gr = {
     83 	.init = nv40_gr_init,
     84 	.intr = nv40_gr_intr,
     85 	.tile = nv44_gr_tile,
     86 	.units = nv40_gr_units,
     87 	.chan_new = nv40_gr_chan_new,
     88 	.sclass = {
     89 		{ -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */
     90 		{ -1, -1, 0x0019, &nv40_gr_object }, /* clip */
     91 		{ -1, -1, 0x0030, &nv40_gr_object }, /* null */
     92 		{ -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */
     93 		{ -1, -1, 0x0043, &nv40_gr_object }, /* rop */
     94 		{ -1, -1, 0x0044, &nv40_gr_object }, /* patt */
     95 		{ -1, -1, 0x004a, &nv40_gr_object }, /* gdi */
     96 		{ -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */
     97 		{ -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */
     98 		{ -1, -1, 0x0089, &nv40_gr_object }, /* sifm */
     99 		{ -1, -1, 0x008a, &nv40_gr_object }, /* ifc */
    100 		{ -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */
    101 		{ -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */
    102 		{ -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */
    103 		{ -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */
    104 		{ -1, -1, 0x4497, &nv40_gr_object }, /* curie */
    105 		{}
    106 	}
    107 };
    108 
    109 int
    110 nv44_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
    111 {
    112 	return nv40_gr_new_(&nv44_gr, device, index, pgr);
    113 }
    114