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      1 /*	$NetBSD: nouveau_nvkm_engine_dma_usernv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_dma_usernv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
     28 
     29 #define nv50_dmaobj(p) container_of((p), struct nv50_dmaobj, base)
     30 #include "user.h"
     31 
     32 #include <core/client.h>
     33 #include <core/gpuobj.h>
     34 #include <subdev/fb.h>
     35 
     36 #include <nvif/cl0002.h>
     37 #include <nvif/unpack.h>
     38 
     39 struct nv50_dmaobj {
     40 	struct nvkm_dmaobj base;
     41 	u32 flags0;
     42 	u32 flags5;
     43 };
     44 
     45 static int
     46 nv50_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
     47 		 int align, struct nvkm_gpuobj **pgpuobj)
     48 {
     49 	struct nv50_dmaobj *dmaobj = nv50_dmaobj(base);
     50 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
     51 	int ret;
     52 
     53 	ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
     54 	if (ret == 0) {
     55 		nvkm_kmap(*pgpuobj);
     56 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
     57 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
     58 		nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
     59 		nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
     60 					  upper_32_bits(dmaobj->base.start));
     61 		nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
     62 		nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
     63 		nvkm_done(*pgpuobj);
     64 	}
     65 
     66 	return ret;
     67 }
     68 
     69 static const struct nvkm_dmaobj_func
     70 nv50_dmaobj_func = {
     71 	.bind = nv50_dmaobj_bind,
     72 };
     73 
     74 int
     75 nv50_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
     76 		void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
     77 {
     78 	union {
     79 		struct nv50_dma_v0 v0;
     80 	} *args;
     81 	struct nvkm_object *parent = oclass->parent;
     82 	struct nv50_dmaobj *dmaobj;
     83 	u32 user, part, comp, kind;
     84 	int ret;
     85 
     86 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
     87 		return -ENOMEM;
     88 	*pdmaobj = &dmaobj->base;
     89 
     90 	ret = nvkm_dmaobj_ctor(&nv50_dmaobj_func, dma, oclass,
     91 			       &data, &size, &dmaobj->base);
     92 	if (ret)
     93 		return ret;
     94 
     95 	ret  = -ENOSYS;
     96 	args = data;
     97 
     98 	nvif_ioctl(parent, "create nv50 dma size %d\n", size);
     99 	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
    100 		nvif_ioctl(parent, "create nv50 dma vers %d priv %d part %d "
    101 				   "comp %d kind %02x\n", args->v0.version,
    102 			   args->v0.priv, args->v0.part, args->v0.comp,
    103 			   args->v0.kind);
    104 		user = args->v0.priv;
    105 		part = args->v0.part;
    106 		comp = args->v0.comp;
    107 		kind = args->v0.kind;
    108 	} else
    109 	if (size == 0) {
    110 		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
    111 			user = NV50_DMA_V0_PRIV_US;
    112 			part = NV50_DMA_V0_PART_256;
    113 			comp = NV50_DMA_V0_COMP_NONE;
    114 			kind = NV50_DMA_V0_KIND_PITCH;
    115 		} else {
    116 			user = NV50_DMA_V0_PRIV_VM;
    117 			part = NV50_DMA_V0_PART_VM;
    118 			comp = NV50_DMA_V0_COMP_VM;
    119 			kind = NV50_DMA_V0_KIND_VM;
    120 		}
    121 	} else
    122 		return ret;
    123 
    124 	if (user > 2 || part > 2 || comp > 3 || kind > 0x7f)
    125 		return -EINVAL;
    126 	dmaobj->flags0 = (comp << 29) | (kind << 22) | (user << 20) |
    127 			 oclass->base.oclass;
    128 	dmaobj->flags5 = (part << 16);
    129 
    130 	switch (dmaobj->base.target) {
    131 	case NV_MEM_TARGET_VM:
    132 		dmaobj->flags0 |= 0x00000000;
    133 		break;
    134 	case NV_MEM_TARGET_VRAM:
    135 		dmaobj->flags0 |= 0x00010000;
    136 		break;
    137 	case NV_MEM_TARGET_PCI:
    138 		dmaobj->flags0 |= 0x00020000;
    139 		break;
    140 	case NV_MEM_TARGET_PCI_NOSNOOP:
    141 		dmaobj->flags0 |= 0x00030000;
    142 		break;
    143 	default:
    144 		return -EINVAL;
    145 	}
    146 
    147 	switch (dmaobj->base.access) {
    148 	case NV_MEM_ACCESS_VM:
    149 		break;
    150 	case NV_MEM_ACCESS_RO:
    151 		dmaobj->flags0 |= 0x00040000;
    152 		break;
    153 	case NV_MEM_ACCESS_WO:
    154 	case NV_MEM_ACCESS_RW:
    155 		dmaobj->flags0 |= 0x00080000;
    156 		break;
    157 	default:
    158 		return -EINVAL;
    159 	}
    160 
    161 	return 0;
    162 }
    163