1 /* $NetBSD: nouveau_nvkm_engine_gr_ctxnv50.c,v 1.4 2021/12/18 23:45:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2009 Marcin Kocielnicki 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxnv50.c,v 1.4 2021/12/18 23:45:36 riastradh Exp $"); 27 28 #define CP_FLAG_CLEAR 0 29 #define CP_FLAG_SET 1 30 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) 31 #define CP_FLAG_SWAP_DIRECTION_LOAD 0 32 #define CP_FLAG_SWAP_DIRECTION_SAVE 1 33 #define CP_FLAG_UNK01 ((0 * 32) + 1) 34 #define CP_FLAG_UNK01_CLEAR 0 35 #define CP_FLAG_UNK01_SET 1 36 #define CP_FLAG_UNK03 ((0 * 32) + 3) 37 #define CP_FLAG_UNK03_CLEAR 0 38 #define CP_FLAG_UNK03_SET 1 39 #define CP_FLAG_USER_SAVE ((0 * 32) + 5) 40 #define CP_FLAG_USER_SAVE_NOT_PENDING 0 41 #define CP_FLAG_USER_SAVE_PENDING 1 42 #define CP_FLAG_USER_LOAD ((0 * 32) + 6) 43 #define CP_FLAG_USER_LOAD_NOT_PENDING 0 44 #define CP_FLAG_USER_LOAD_PENDING 1 45 #define CP_FLAG_UNK0B ((0 * 32) + 0xb) 46 #define CP_FLAG_UNK0B_CLEAR 0 47 #define CP_FLAG_UNK0B_SET 1 48 #define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe) 49 #define CP_FLAG_XFER_SWITCH_DISABLE 0 50 #define CP_FLAG_XFER_SWITCH_ENABLE 1 51 #define CP_FLAG_STATE ((0 * 32) + 0x1c) 52 #define CP_FLAG_STATE_STOPPED 0 53 #define CP_FLAG_STATE_RUNNING 1 54 #define CP_FLAG_UNK1D ((0 * 32) + 0x1d) 55 #define CP_FLAG_UNK1D_CLEAR 0 56 #define CP_FLAG_UNK1D_SET 1 57 #define CP_FLAG_UNK20 ((1 * 32) + 0) 58 #define CP_FLAG_UNK20_CLEAR 0 59 #define CP_FLAG_UNK20_SET 1 60 #define CP_FLAG_STATUS ((2 * 32) + 0) 61 #define CP_FLAG_STATUS_BUSY 0 62 #define CP_FLAG_STATUS_IDLE 1 63 #define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) 64 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 65 #define CP_FLAG_AUTO_SAVE_PENDING 1 66 #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) 67 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 68 #define CP_FLAG_AUTO_LOAD_PENDING 1 69 #define CP_FLAG_NEWCTX ((2 * 32) + 10) 70 #define CP_FLAG_NEWCTX_BUSY 0 71 #define CP_FLAG_NEWCTX_DONE 1 72 #define CP_FLAG_XFER ((2 * 32) + 11) 73 #define CP_FLAG_XFER_IDLE 0 74 #define CP_FLAG_XFER_BUSY 1 75 #define CP_FLAG_ALWAYS ((2 * 32) + 13) 76 #define CP_FLAG_ALWAYS_FALSE 0 77 #define CP_FLAG_ALWAYS_TRUE 1 78 #define CP_FLAG_INTR ((2 * 32) + 15) 79 #define CP_FLAG_INTR_NOT_PENDING 0 80 #define CP_FLAG_INTR_PENDING 1 81 82 #define CP_CTX 0x00100000 83 #define CP_CTX_COUNT 0x000f0000 84 #define CP_CTX_COUNT_SHIFT 16 85 #define CP_CTX_REG 0x00003fff 86 #define CP_LOAD_SR 0x00200000 87 #define CP_LOAD_SR_VALUE 0x000fffff 88 #define CP_BRA 0x00400000 89 #define CP_BRA_IP 0x0001ff00 90 #define CP_BRA_IP_SHIFT 8 91 #define CP_BRA_IF_CLEAR 0x00000080 92 #define CP_BRA_FLAG 0x0000007f 93 #define CP_WAIT 0x00500000 94 #define CP_WAIT_SET 0x00000080 95 #define CP_WAIT_FLAG 0x0000007f 96 #define CP_SET 0x00700000 97 #define CP_SET_1 0x00000080 98 #define CP_SET_FLAG 0x0000007f 99 #define CP_NEWCTX 0x00600004 100 #define CP_NEXT_TO_SWAP 0x00600005 101 #define CP_SET_CONTEXT_POINTER 0x00600006 102 #define CP_SET_XFER_POINTER 0x00600007 103 #define CP_ENABLE 0x00600009 104 #define CP_END 0x0060000c 105 #define CP_NEXT_TO_CURRENT 0x0060000d 106 #define CP_DISABLE1 0x0090ffff 107 #define CP_DISABLE2 0x0091ffff 108 #define CP_XFER_1 0x008000ff 109 #define CP_XFER_2 0x008800ff 110 #define CP_SEEK_1 0x00c000ff 111 #define CP_SEEK_2 0x00c800ff 112 113 #include "ctxnv40.h" 114 #include "nv50.h" 115 116 #include <subdev/fb.h> 117 118 #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) 119 #define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac) 120 121 /* 122 * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's 123 * the GPU itself that does context-switching, but it needs a special 124 * microcode to do it. And it's the driver's task to supply this microcode, 125 * further known as ctxprog, as well as the initial context values, known 126 * as ctxvals. 127 * 128 * Without ctxprog, you cannot switch contexts. Not even in software, since 129 * the majority of context [xfer strands] isn't accessible directly. You're 130 * stuck with a single channel, and you also suffer all the problems resulting 131 * from missing ctxvals, since you cannot load them. 132 * 133 * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to 134 * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, 135 * since you don't have... some sort of needed setup. 136 * 137 * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since 138 * it's too much hassle to handle no-ctxprog as a special case. 139 */ 140 141 /* 142 * How ctxprogs work. 143 * 144 * The ctxprog is written in its own kind of microcode, with very small and 145 * crappy set of available commands. You upload it to a small [512 insns] 146 * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to 147 * switch channel. or when the driver explicitely requests it. Stuff visible 148 * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, 149 * the per-channel context save area in VRAM [known as ctxvals or grctx], 150 * 4 flags registers, a scratch register, two grctx pointers, plus many 151 * random poorly-understood details. 152 * 153 * When ctxprog runs, it's supposed to check what operations are asked of it, 154 * save old context if requested, optionally reset PGRAPH and switch to the 155 * new channel, and load the new context. Context consists of three major 156 * parts: subset of MMIO registers and two "xfer areas". 157 */ 158 159 /* TODO: 160 * - document unimplemented bits compared to nvidia 161 * - NVAx: make a TP subroutine, use it. 162 * - use 0x4008fc instead of 0x1540? 163 */ 164 165 enum cp_label { 166 cp_check_load = 1, 167 cp_setup_auto_load, 168 cp_setup_load, 169 cp_setup_save, 170 cp_swap_state, 171 cp_prepare_exit, 172 cp_exit, 173 }; 174 175 static void nv50_gr_construct_mmio(struct nvkm_grctx *ctx); 176 static void nv50_gr_construct_xfer1(struct nvkm_grctx *ctx); 177 static void nv50_gr_construct_xfer2(struct nvkm_grctx *ctx); 178 179 /* Main function: construct the ctxprog skeleton, call the other functions. */ 180 181 static int 182 nv50_grctx_generate(struct nvkm_grctx *ctx) 183 { 184 cp_set (ctx, STATE, RUNNING); 185 cp_set (ctx, XFER_SWITCH, ENABLE); 186 /* decide whether we're loading/unloading the context */ 187 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); 188 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); 189 190 cp_name(ctx, cp_check_load); 191 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); 192 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); 193 cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit); 194 195 /* setup for context load */ 196 cp_name(ctx, cp_setup_auto_load); 197 cp_out (ctx, CP_DISABLE1); 198 cp_out (ctx, CP_DISABLE2); 199 cp_out (ctx, CP_ENABLE); 200 cp_out (ctx, CP_NEXT_TO_SWAP); 201 cp_set (ctx, UNK01, SET); 202 cp_name(ctx, cp_setup_load); 203 cp_out (ctx, CP_NEWCTX); 204 cp_wait(ctx, NEWCTX, BUSY); 205 cp_set (ctx, UNK1D, CLEAR); 206 cp_set (ctx, SWAP_DIRECTION, LOAD); 207 cp_bra (ctx, UNK0B, SET, cp_prepare_exit); 208 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); 209 210 /* setup for context save */ 211 cp_name(ctx, cp_setup_save); 212 cp_set (ctx, UNK1D, SET); 213 cp_wait(ctx, STATUS, BUSY); 214 cp_wait(ctx, INTR, PENDING); 215 cp_bra (ctx, STATUS, BUSY, cp_setup_save); 216 cp_set (ctx, UNK01, SET); 217 cp_set (ctx, SWAP_DIRECTION, SAVE); 218 219 /* general PGRAPH state */ 220 cp_name(ctx, cp_swap_state); 221 cp_set (ctx, UNK03, SET); 222 cp_pos (ctx, 0x00004/4); 223 cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ 224 cp_pos (ctx, 0x00100/4); 225 nv50_gr_construct_mmio(ctx); 226 nv50_gr_construct_xfer1(ctx); 227 nv50_gr_construct_xfer2(ctx); 228 229 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); 230 231 cp_set (ctx, UNK20, SET); 232 cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ 233 cp_lsr (ctx, ctx->ctxvals_base); 234 cp_out (ctx, CP_SET_XFER_POINTER); 235 cp_lsr (ctx, 4); 236 cp_out (ctx, CP_SEEK_1); 237 cp_out (ctx, CP_XFER_1); 238 cp_wait(ctx, XFER, BUSY); 239 240 /* pre-exit state updates */ 241 cp_name(ctx, cp_prepare_exit); 242 cp_set (ctx, UNK01, CLEAR); 243 cp_set (ctx, UNK03, CLEAR); 244 cp_set (ctx, UNK1D, CLEAR); 245 246 cp_bra (ctx, USER_SAVE, PENDING, cp_exit); 247 cp_out (ctx, CP_NEXT_TO_CURRENT); 248 249 cp_name(ctx, cp_exit); 250 cp_set (ctx, USER_SAVE, NOT_PENDING); 251 cp_set (ctx, USER_LOAD, NOT_PENDING); 252 cp_set (ctx, XFER_SWITCH, DISABLE); 253 cp_set (ctx, STATE, STOPPED); 254 cp_out (ctx, CP_END); 255 ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ 256 257 return 0; 258 } 259 260 void 261 nv50_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem) 262 { 263 nv50_grctx_generate(&(struct nvkm_grctx) { 264 .device = device, 265 .mode = NVKM_GRCTX_VALS, 266 .data = mem, 267 }); 268 } 269 270 int 271 nv50_grctx_init(struct nvkm_device *device, u32 *size) 272 { 273 u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i; 274 struct nvkm_grctx ctx = { 275 .device = device, 276 .mode = NVKM_GRCTX_PROG, 277 .ucode = ctxprog, 278 .ctxprog_max = 512, 279 }; 280 281 if (!ctxprog) 282 return -ENOMEM; 283 nv50_grctx_generate(&ctx); 284 285 nvkm_wr32(device, 0x400324, 0); 286 for (i = 0; i < ctx.ctxprog_len; i++) 287 nvkm_wr32(device, 0x400328, ctxprog[i]); 288 *size = ctx.ctxvals_pos * 4; 289 kfree(ctxprog); 290 return 0; 291 } 292 293 /* 294 * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which 295 * registers to save/restore and the default values for them. 296 */ 297 298 static void 299 nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx); 300 301 static void 302 nv50_gr_construct_mmio(struct nvkm_grctx *ctx) 303 { 304 struct nvkm_device *device = ctx->device; 305 int i, j; 306 int offset, base; 307 u32 units = nvkm_rd32(device, 0x1540); 308 309 /* 0800: DISPATCH */ 310 cp_ctx(ctx, 0x400808, 7); 311 gr_def(ctx, 0x400814, 0x00000030); 312 cp_ctx(ctx, 0x400834, 0x32); 313 if (device->chipset == 0x50) { 314 gr_def(ctx, 0x400834, 0xff400040); 315 gr_def(ctx, 0x400838, 0xfff00080); 316 gr_def(ctx, 0x40083c, 0xfff70090); 317 gr_def(ctx, 0x400840, 0xffe806a8); 318 } 319 gr_def(ctx, 0x400844, 0x00000002); 320 if (IS_NVA3F(device->chipset)) 321 gr_def(ctx, 0x400894, 0x00001000); 322 gr_def(ctx, 0x4008e8, 0x00000003); 323 gr_def(ctx, 0x4008ec, 0x00001000); 324 if (device->chipset == 0x50) 325 cp_ctx(ctx, 0x400908, 0xb); 326 else if (device->chipset < 0xa0) 327 cp_ctx(ctx, 0x400908, 0xc); 328 else 329 cp_ctx(ctx, 0x400908, 0xe); 330 331 if (device->chipset >= 0xa0) 332 cp_ctx(ctx, 0x400b00, 0x1); 333 if (IS_NVA3F(device->chipset)) { 334 cp_ctx(ctx, 0x400b10, 0x1); 335 gr_def(ctx, 0x400b10, 0x0001629d); 336 cp_ctx(ctx, 0x400b20, 0x1); 337 gr_def(ctx, 0x400b20, 0x0001629d); 338 } 339 340 nv50_gr_construct_mmio_ddata(ctx); 341 342 /* 0C00: VFETCH */ 343 cp_ctx(ctx, 0x400c08, 0x2); 344 gr_def(ctx, 0x400c08, 0x0000fe0c); 345 346 /* 1000 */ 347 if (device->chipset < 0xa0) { 348 cp_ctx(ctx, 0x401008, 0x4); 349 gr_def(ctx, 0x401014, 0x00001000); 350 } else if (!IS_NVA3F(device->chipset)) { 351 cp_ctx(ctx, 0x401008, 0x5); 352 gr_def(ctx, 0x401018, 0x00001000); 353 } else { 354 cp_ctx(ctx, 0x401008, 0x5); 355 gr_def(ctx, 0x401018, 0x00004000); 356 } 357 358 /* 1400 */ 359 cp_ctx(ctx, 0x401400, 0x8); 360 cp_ctx(ctx, 0x401424, 0x3); 361 if (device->chipset == 0x50) 362 gr_def(ctx, 0x40142c, 0x0001fd87); 363 else 364 gr_def(ctx, 0x40142c, 0x00000187); 365 cp_ctx(ctx, 0x401540, 0x5); 366 gr_def(ctx, 0x401550, 0x00001018); 367 368 /* 1800: STREAMOUT */ 369 cp_ctx(ctx, 0x401814, 0x1); 370 gr_def(ctx, 0x401814, 0x000000ff); 371 if (device->chipset == 0x50) { 372 cp_ctx(ctx, 0x40181c, 0xe); 373 gr_def(ctx, 0x401850, 0x00000004); 374 } else if (device->chipset < 0xa0) { 375 cp_ctx(ctx, 0x40181c, 0xf); 376 gr_def(ctx, 0x401854, 0x00000004); 377 } else { 378 cp_ctx(ctx, 0x40181c, 0x13); 379 gr_def(ctx, 0x401864, 0x00000004); 380 } 381 382 /* 1C00 */ 383 cp_ctx(ctx, 0x401c00, 0x1); 384 switch (device->chipset) { 385 case 0x50: 386 gr_def(ctx, 0x401c00, 0x0001005f); 387 break; 388 case 0x84: 389 case 0x86: 390 case 0x94: 391 gr_def(ctx, 0x401c00, 0x044d00df); 392 break; 393 case 0x92: 394 case 0x96: 395 case 0x98: 396 case 0xa0: 397 case 0xaa: 398 case 0xac: 399 gr_def(ctx, 0x401c00, 0x042500df); 400 break; 401 case 0xa3: 402 case 0xa5: 403 case 0xa8: 404 case 0xaf: 405 gr_def(ctx, 0x401c00, 0x142500df); 406 break; 407 } 408 409 /* 2000 */ 410 411 /* 2400 */ 412 cp_ctx(ctx, 0x402400, 0x1); 413 if (device->chipset == 0x50) 414 cp_ctx(ctx, 0x402408, 0x1); 415 else 416 cp_ctx(ctx, 0x402408, 0x2); 417 gr_def(ctx, 0x402408, 0x00000600); 418 419 /* 2800: CSCHED */ 420 cp_ctx(ctx, 0x402800, 0x1); 421 if (device->chipset == 0x50) 422 gr_def(ctx, 0x402800, 0x00000006); 423 424 /* 2C00: ZCULL */ 425 cp_ctx(ctx, 0x402c08, 0x6); 426 if (device->chipset != 0x50) 427 gr_def(ctx, 0x402c14, 0x01000000); 428 gr_def(ctx, 0x402c18, 0x000000ff); 429 if (device->chipset == 0x50) 430 cp_ctx(ctx, 0x402ca0, 0x1); 431 else 432 cp_ctx(ctx, 0x402ca0, 0x2); 433 if (device->chipset < 0xa0) 434 gr_def(ctx, 0x402ca0, 0x00000400); 435 else if (!IS_NVA3F(device->chipset)) 436 gr_def(ctx, 0x402ca0, 0x00000800); 437 else 438 gr_def(ctx, 0x402ca0, 0x00000400); 439 cp_ctx(ctx, 0x402cac, 0x4); 440 441 /* 3000: ENG2D */ 442 cp_ctx(ctx, 0x403004, 0x1); 443 gr_def(ctx, 0x403004, 0x00000001); 444 445 /* 3400 */ 446 if (device->chipset >= 0xa0) { 447 cp_ctx(ctx, 0x403404, 0x1); 448 gr_def(ctx, 0x403404, 0x00000001); 449 } 450 451 /* 5000: CCACHE */ 452 cp_ctx(ctx, 0x405000, 0x1); 453 switch (device->chipset) { 454 case 0x50: 455 gr_def(ctx, 0x405000, 0x00300080); 456 break; 457 case 0x84: 458 case 0xa0: 459 case 0xa3: 460 case 0xa5: 461 case 0xa8: 462 case 0xaa: 463 case 0xac: 464 case 0xaf: 465 gr_def(ctx, 0x405000, 0x000e0080); 466 break; 467 case 0x86: 468 case 0x92: 469 case 0x94: 470 case 0x96: 471 case 0x98: 472 gr_def(ctx, 0x405000, 0x00000080); 473 break; 474 } 475 cp_ctx(ctx, 0x405014, 0x1); 476 gr_def(ctx, 0x405014, 0x00000004); 477 cp_ctx(ctx, 0x40501c, 0x1); 478 cp_ctx(ctx, 0x405024, 0x1); 479 cp_ctx(ctx, 0x40502c, 0x1); 480 481 /* 6000? */ 482 if (device->chipset == 0x50) 483 cp_ctx(ctx, 0x4063e0, 0x1); 484 485 /* 6800: M2MF */ 486 if (device->chipset < 0x90) { 487 cp_ctx(ctx, 0x406814, 0x2b); 488 gr_def(ctx, 0x406818, 0x00000f80); 489 gr_def(ctx, 0x406860, 0x007f0080); 490 gr_def(ctx, 0x40689c, 0x007f0080); 491 } else { 492 cp_ctx(ctx, 0x406814, 0x4); 493 if (device->chipset == 0x98) 494 gr_def(ctx, 0x406818, 0x00000f80); 495 else 496 gr_def(ctx, 0x406818, 0x00001f80); 497 if (IS_NVA3F(device->chipset)) 498 gr_def(ctx, 0x40681c, 0x00000030); 499 cp_ctx(ctx, 0x406830, 0x3); 500 } 501 502 /* 7000: per-ROP group state */ 503 for (i = 0; i < 8; i++) { 504 if (units & (1<<(i+16))) { 505 cp_ctx(ctx, 0x407000 + (i<<8), 3); 506 if (device->chipset == 0x50) 507 gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); 508 else if (device->chipset != 0xa5) 509 gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); 510 else 511 gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); 512 gr_def(ctx, 0x407004 + (i<<8), 0x89058001); 513 514 if (device->chipset == 0x50) { 515 cp_ctx(ctx, 0x407010 + (i<<8), 1); 516 } else if (device->chipset < 0xa0) { 517 cp_ctx(ctx, 0x407010 + (i<<8), 2); 518 gr_def(ctx, 0x407010 + (i<<8), 0x00001000); 519 gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); 520 } else { 521 cp_ctx(ctx, 0x407010 + (i<<8), 3); 522 gr_def(ctx, 0x407010 + (i<<8), 0x00001000); 523 if (device->chipset != 0xa5) 524 gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); 525 else 526 gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); 527 } 528 529 cp_ctx(ctx, 0x407080 + (i<<8), 4); 530 if (device->chipset != 0xa5) 531 gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); 532 else 533 gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); 534 if (device->chipset == 0x50) 535 gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); 536 else 537 gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); 538 gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); 539 540 if (device->chipset < 0xa0) 541 cp_ctx(ctx, 0x407094 + (i<<8), 1); 542 else if (!IS_NVA3F(device->chipset)) 543 cp_ctx(ctx, 0x407094 + (i<<8), 3); 544 else { 545 cp_ctx(ctx, 0x407094 + (i<<8), 4); 546 gr_def(ctx, 0x4070a0 + (i<<8), 1); 547 } 548 } 549 } 550 551 cp_ctx(ctx, 0x407c00, 0x3); 552 if (device->chipset < 0x90) 553 gr_def(ctx, 0x407c00, 0x00010040); 554 else if (device->chipset < 0xa0) 555 gr_def(ctx, 0x407c00, 0x00390040); 556 else 557 gr_def(ctx, 0x407c00, 0x003d0040); 558 gr_def(ctx, 0x407c08, 0x00000022); 559 if (device->chipset >= 0xa0) { 560 cp_ctx(ctx, 0x407c10, 0x3); 561 cp_ctx(ctx, 0x407c20, 0x1); 562 cp_ctx(ctx, 0x407c2c, 0x1); 563 } 564 565 if (device->chipset < 0xa0) { 566 cp_ctx(ctx, 0x407d00, 0x9); 567 } else { 568 cp_ctx(ctx, 0x407d00, 0x15); 569 } 570 if (device->chipset == 0x98) 571 gr_def(ctx, 0x407d08, 0x00380040); 572 else { 573 if (device->chipset < 0x90) 574 gr_def(ctx, 0x407d08, 0x00010040); 575 else if (device->chipset < 0xa0) 576 gr_def(ctx, 0x407d08, 0x00390040); 577 else { 578 if (device->fb->ram->type != NVKM_RAM_TYPE_GDDR5) 579 gr_def(ctx, 0x407d08, 0x003d0040); 580 else 581 gr_def(ctx, 0x407d08, 0x003c0040); 582 } 583 gr_def(ctx, 0x407d0c, 0x00000022); 584 } 585 586 /* 8000+: per-TP state */ 587 for (i = 0; i < 10; i++) { 588 if (units & (1<<i)) { 589 if (device->chipset < 0xa0) 590 base = 0x408000 + (i<<12); 591 else 592 base = 0x408000 + (i<<11); 593 if (device->chipset < 0xa0) 594 offset = base + 0xc00; 595 else 596 offset = base + 0x80; 597 cp_ctx(ctx, offset + 0x00, 1); 598 gr_def(ctx, offset + 0x00, 0x0000ff0a); 599 cp_ctx(ctx, offset + 0x08, 1); 600 601 /* per-MP state */ 602 for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) { 603 if (!(units & (1 << (j+24)))) continue; 604 if (device->chipset < 0xa0) 605 offset = base + 0x200 + (j<<7); 606 else 607 offset = base + 0x100 + (j<<7); 608 cp_ctx(ctx, offset, 0x20); 609 gr_def(ctx, offset + 0x00, 0x01800000); 610 gr_def(ctx, offset + 0x04, 0x00160000); 611 gr_def(ctx, offset + 0x08, 0x01800000); 612 gr_def(ctx, offset + 0x18, 0x0003ffff); 613 switch (device->chipset) { 614 case 0x50: 615 gr_def(ctx, offset + 0x1c, 0x00080000); 616 break; 617 case 0x84: 618 gr_def(ctx, offset + 0x1c, 0x00880000); 619 break; 620 case 0x86: 621 gr_def(ctx, offset + 0x1c, 0x018c0000); 622 break; 623 case 0x92: 624 case 0x96: 625 case 0x98: 626 gr_def(ctx, offset + 0x1c, 0x118c0000); 627 break; 628 case 0x94: 629 gr_def(ctx, offset + 0x1c, 0x10880000); 630 break; 631 case 0xa0: 632 case 0xa5: 633 gr_def(ctx, offset + 0x1c, 0x310c0000); 634 break; 635 case 0xa3: 636 case 0xa8: 637 case 0xaa: 638 case 0xac: 639 case 0xaf: 640 gr_def(ctx, offset + 0x1c, 0x300c0000); 641 break; 642 } 643 gr_def(ctx, offset + 0x40, 0x00010401); 644 if (device->chipset == 0x50) 645 gr_def(ctx, offset + 0x48, 0x00000040); 646 else 647 gr_def(ctx, offset + 0x48, 0x00000078); 648 gr_def(ctx, offset + 0x50, 0x000000bf); 649 gr_def(ctx, offset + 0x58, 0x00001210); 650 if (device->chipset == 0x50) 651 gr_def(ctx, offset + 0x5c, 0x00000080); 652 else 653 gr_def(ctx, offset + 0x5c, 0x08000080); 654 if (device->chipset >= 0xa0) 655 gr_def(ctx, offset + 0x68, 0x0000003e); 656 } 657 658 if (device->chipset < 0xa0) 659 cp_ctx(ctx, base + 0x300, 0x4); 660 else 661 cp_ctx(ctx, base + 0x300, 0x5); 662 if (device->chipset == 0x50) 663 gr_def(ctx, base + 0x304, 0x00007070); 664 else if (device->chipset < 0xa0) 665 gr_def(ctx, base + 0x304, 0x00027070); 666 else if (!IS_NVA3F(device->chipset)) 667 gr_def(ctx, base + 0x304, 0x01127070); 668 else 669 gr_def(ctx, base + 0x304, 0x05127070); 670 671 if (device->chipset < 0xa0) 672 cp_ctx(ctx, base + 0x318, 1); 673 else 674 cp_ctx(ctx, base + 0x320, 1); 675 if (device->chipset == 0x50) 676 gr_def(ctx, base + 0x318, 0x0003ffff); 677 else if (device->chipset < 0xa0) 678 gr_def(ctx, base + 0x318, 0x03ffffff); 679 else 680 gr_def(ctx, base + 0x320, 0x07ffffff); 681 682 if (device->chipset < 0xa0) 683 cp_ctx(ctx, base + 0x324, 5); 684 else 685 cp_ctx(ctx, base + 0x328, 4); 686 687 if (device->chipset < 0xa0) { 688 cp_ctx(ctx, base + 0x340, 9); 689 offset = base + 0x340; 690 } else if (!IS_NVA3F(device->chipset)) { 691 cp_ctx(ctx, base + 0x33c, 0xb); 692 offset = base + 0x344; 693 } else { 694 cp_ctx(ctx, base + 0x33c, 0xd); 695 offset = base + 0x344; 696 } 697 gr_def(ctx, offset + 0x0, 0x00120407); 698 gr_def(ctx, offset + 0x4, 0x05091507); 699 if (device->chipset == 0x84) 700 gr_def(ctx, offset + 0x8, 0x05100202); 701 else 702 gr_def(ctx, offset + 0x8, 0x05010202); 703 gr_def(ctx, offset + 0xc, 0x00030201); 704 if (device->chipset == 0xa3) 705 cp_ctx(ctx, base + 0x36c, 1); 706 707 cp_ctx(ctx, base + 0x400, 2); 708 gr_def(ctx, base + 0x404, 0x00000040); 709 cp_ctx(ctx, base + 0x40c, 2); 710 gr_def(ctx, base + 0x40c, 0x0d0c0b0a); 711 gr_def(ctx, base + 0x410, 0x00141210); 712 713 if (device->chipset < 0xa0) 714 offset = base + 0x800; 715 else 716 offset = base + 0x500; 717 cp_ctx(ctx, offset, 6); 718 gr_def(ctx, offset + 0x0, 0x000001f0); 719 gr_def(ctx, offset + 0x4, 0x00000001); 720 gr_def(ctx, offset + 0x8, 0x00000003); 721 if (device->chipset == 0x50 || IS_NVAAF(device->chipset)) 722 gr_def(ctx, offset + 0xc, 0x00008000); 723 gr_def(ctx, offset + 0x14, 0x00039e00); 724 cp_ctx(ctx, offset + 0x1c, 2); 725 if (device->chipset == 0x50) 726 gr_def(ctx, offset + 0x1c, 0x00000040); 727 else 728 gr_def(ctx, offset + 0x1c, 0x00000100); 729 gr_def(ctx, offset + 0x20, 0x00003800); 730 731 if (device->chipset >= 0xa0) { 732 cp_ctx(ctx, base + 0x54c, 2); 733 if (!IS_NVA3F(device->chipset)) 734 gr_def(ctx, base + 0x54c, 0x003fe006); 735 else 736 gr_def(ctx, base + 0x54c, 0x003fe007); 737 gr_def(ctx, base + 0x550, 0x003fe000); 738 } 739 740 if (device->chipset < 0xa0) 741 offset = base + 0xa00; 742 else 743 offset = base + 0x680; 744 cp_ctx(ctx, offset, 1); 745 gr_def(ctx, offset, 0x00404040); 746 747 if (device->chipset < 0xa0) 748 offset = base + 0xe00; 749 else 750 offset = base + 0x700; 751 cp_ctx(ctx, offset, 2); 752 if (device->chipset < 0xa0) 753 gr_def(ctx, offset, 0x0077f005); 754 else if (device->chipset == 0xa5) 755 gr_def(ctx, offset, 0x6cf7f007); 756 else if (device->chipset == 0xa8) 757 gr_def(ctx, offset, 0x6cfff007); 758 else if (device->chipset == 0xac) 759 gr_def(ctx, offset, 0x0cfff007); 760 else 761 gr_def(ctx, offset, 0x0cf7f007); 762 if (device->chipset == 0x50) 763 gr_def(ctx, offset + 0x4, 0x00007fff); 764 else if (device->chipset < 0xa0) 765 gr_def(ctx, offset + 0x4, 0x003f7fff); 766 else 767 gr_def(ctx, offset + 0x4, 0x02bf7fff); 768 cp_ctx(ctx, offset + 0x2c, 1); 769 if (device->chipset == 0x50) { 770 cp_ctx(ctx, offset + 0x50, 9); 771 gr_def(ctx, offset + 0x54, 0x000003ff); 772 gr_def(ctx, offset + 0x58, 0x00000003); 773 gr_def(ctx, offset + 0x5c, 0x00000003); 774 gr_def(ctx, offset + 0x60, 0x000001ff); 775 gr_def(ctx, offset + 0x64, 0x0000001f); 776 gr_def(ctx, offset + 0x68, 0x0000000f); 777 gr_def(ctx, offset + 0x6c, 0x0000000f); 778 } else if (device->chipset < 0xa0) { 779 cp_ctx(ctx, offset + 0x50, 1); 780 cp_ctx(ctx, offset + 0x70, 1); 781 } else { 782 cp_ctx(ctx, offset + 0x50, 1); 783 cp_ctx(ctx, offset + 0x60, 5); 784 } 785 } 786 } 787 } 788 789 static void 790 dd_emit(struct nvkm_grctx *ctx, int num, u32 val) { 791 int i; 792 if (val && ctx->mode == NVKM_GRCTX_VALS) { 793 for (i = 0; i < num; i++) 794 nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); 795 } 796 ctx->ctxvals_pos += num; 797 } 798 799 static void 800 nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx) 801 { 802 struct nvkm_device *device = ctx->device; 803 int base, num; 804 base = ctx->ctxvals_pos; 805 806 /* tesla state */ 807 dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */ 808 dd_emit(ctx, 1, 0); /* 00000001 UNK135C */ 809 810 /* SRC_TIC state */ 811 dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */ 812 dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */ 813 dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */ 814 dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */ 815 dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */ 816 if (device->chipset >= 0x94) 817 dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */ 818 dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */ 819 dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */ 820 821 /* turing state */ 822 dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */ 823 dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */ 824 dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ 825 dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ 826 dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ 827 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ 828 dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */ 829 dd_emit(ctx, 1, 1); /* 00000001 LANES32 */ 830 dd_emit(ctx, 1, 0); /* 000000ff UNK370 */ 831 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */ 832 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */ 833 dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */ 834 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 835 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 836 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ 837 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */ 838 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */ 839 dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */ 840 dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */ 841 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */ 842 dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */ 843 dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */ 844 dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */ 845 if (IS_NVA3F(device->chipset)) 846 dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */ 847 dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */ 848 dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */ 849 dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */ 850 dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */ 851 dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */ 852 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */ 853 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */ 854 dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */ 855 856 /* compat 2d state */ 857 if (device->chipset == 0x50) { 858 dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */ 859 860 dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */ 861 862 dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */ 863 dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */ 864 dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */ 865 866 dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */ 867 dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */ 868 dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */ 869 dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */ 870 dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */ 871 dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */ 872 dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */ 873 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */ 874 dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */ 875 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */ 876 877 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */ 878 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */ 879 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */ 880 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */ 881 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */ 882 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */ 883 dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */ 884 dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */ 885 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */ 886 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */ 887 888 dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */ 889 dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */ 890 891 dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */ 892 893 dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */ 894 dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */ 895 dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */ 896 dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */ 897 } 898 899 /* m2mf state */ 900 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */ 901 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */ 902 dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */ 903 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */ 904 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */ 905 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */ 906 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */ 907 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */ 908 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */ 909 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */ 910 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */ 911 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */ 912 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */ 913 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */ 914 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */ 915 916 /* more compat 2d state */ 917 if (device->chipset == 0x50) { 918 dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */ 919 dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */ 920 921 dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */ 922 dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */ 923 924 dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */ 925 dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */ 926 dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */ 927 dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */ 928 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */ 929 dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */ 930 dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */ 931 dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */ 932 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */ 933 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */ 934 dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */ 935 dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */ 936 937 dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */ 938 } 939 940 /* tesla state */ 941 dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */ 942 dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */ 943 dd_emit(ctx, 1, 0); /* 000000ff */ 944 dd_emit(ctx, 1, 0); /* ffffffff */ 945 dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */ 946 dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */ 947 dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */ 948 dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */ 949 dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */ 950 dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */ 951 if (IS_NVA3F(device->chipset)) { 952 dd_emit(ctx, 1, 0); /* ffffffff */ 953 dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */ 954 } else { 955 dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */ 956 } 957 dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */ 958 if (device->chipset != 0x50) 959 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */ 960 dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */ 961 dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */ 962 if (device->chipset == 0x50) { 963 dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */ 964 dd_emit(ctx, 1, 0); /* 00000001 */ 965 } else { 966 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */ 967 dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */ 968 dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */ 969 dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 970 dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */ 971 dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */ 972 dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ 973 dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */ 974 } 975 dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */ 976 dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */ 977 dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */ 978 dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */ 979 dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */ 980 dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */ 981 dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */ 982 dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */ 983 dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */ 984 dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */ 985 dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ 986 dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */ 987 dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */ 988 if (device->chipset != 0x50) 989 dd_emit(ctx, 3, 0); /* 1, 1, 1 */ 990 else 991 dd_emit(ctx, 2, 0); /* 1, 1 */ 992 dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */ 993 dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/ 994 dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 995 dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 996 if (IS_NVA3F(device->chipset)) { 997 dd_emit(ctx, 1, 3); /* 00000003 */ 998 dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */ 999 } 1000 if (device->chipset != 0x50) 1001 dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */ 1002 dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */ 1003 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */ 1004 if (device->chipset != 0x50) 1005 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */ 1006 dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */ 1007 dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */ 1008 dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */ 1009 dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */ 1010 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */ 1011 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */ 1012 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */ 1013 dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ 1014 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ 1015 dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 1016 if (device->chipset >= 0xa0) 1017 dd_emit(ctx, 1, 0); /* ffffffff */ 1018 dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */ 1019 dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */ 1020 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 1021 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 1022 dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/ 1023 if (device->chipset != 0x50) 1024 dd_emit(ctx, 8, 0); /* 00000001 */ 1025 if (device->chipset >= 0xa0) { 1026 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */ 1027 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */ 1028 dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */ 1029 dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */ 1030 } 1031 dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1032 dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */ 1033 dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 1034 dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */ 1035 dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */ 1036 if (IS_NVA3F(device->chipset)) 1037 dd_emit(ctx, 1, 0); /* 00000001 */ 1038 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */ 1039 if (device->chipset >= 0xa0) 1040 dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */ 1041 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ 1042 if (device->chipset >= 0xa0) 1043 dd_emit(ctx, 1, 0); /* 00000003 */ 1044 dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */ 1045 dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */ 1046 dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */ 1047 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */ 1048 dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */ 1049 if (device->chipset != 0x50) { 1050 dd_emit(ctx, 1, 0xe00); /* 7fff */ 1051 dd_emit(ctx, 1, 0x1000); /* 7fff */ 1052 dd_emit(ctx, 1, 0x1e00); /* 7fff */ 1053 } 1054 dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */ 1055 dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */ 1056 dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */ 1057 dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */ 1058 dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */ 1059 dd_emit(ctx, 1, 1); /* 00000001 */ 1060 dd_emit(ctx, 1, 0); /* 00000001 */ 1061 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */ 1062 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */ 1063 dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */ 1064 if (IS_NVA3F(device->chipset)) 1065 dd_emit(ctx, 1, 0x200); 1066 dd_emit(ctx, 1, 0); /* 00000001 */ 1067 if (device->chipset < 0xa0) { 1068 dd_emit(ctx, 1, 1); /* 00000001 */ 1069 dd_emit(ctx, 1, 0x70); /* 000000ff */ 1070 dd_emit(ctx, 1, 0x80); /* 000000ff */ 1071 dd_emit(ctx, 1, 0); /* 000000ff */ 1072 dd_emit(ctx, 1, 0); /* 00000001 */ 1073 dd_emit(ctx, 1, 1); /* 00000001 */ 1074 dd_emit(ctx, 1, 0x70); /* 000000ff */ 1075 dd_emit(ctx, 1, 0x80); /* 000000ff */ 1076 dd_emit(ctx, 1, 0); /* 000000ff */ 1077 } else { 1078 dd_emit(ctx, 1, 1); /* 00000001 */ 1079 dd_emit(ctx, 1, 0xf0); /* 000000ff */ 1080 dd_emit(ctx, 1, 0xff); /* 000000ff */ 1081 dd_emit(ctx, 1, 0); /* 000000ff */ 1082 dd_emit(ctx, 1, 0); /* 00000001 */ 1083 dd_emit(ctx, 1, 1); /* 00000001 */ 1084 dd_emit(ctx, 1, 0xf0); /* 000000ff */ 1085 dd_emit(ctx, 1, 0xff); /* 000000ff */ 1086 dd_emit(ctx, 1, 0); /* 000000ff */ 1087 dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */ 1088 } 1089 1090 /* eng2d state */ 1091 dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */ 1092 dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */ 1093 dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */ 1094 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */ 1095 dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */ 1096 dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */ 1097 dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */ 1098 dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */ 1099 dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */ 1100 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */ 1101 dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */ 1102 dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */ 1103 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */ 1104 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */ 1105 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */ 1106 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */ 1107 dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */ 1108 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */ 1109 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */ 1110 dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */ 1111 1112 num = ctx->ctxvals_pos - base; 1113 ctx->ctxvals_pos = base; 1114 if (IS_NVA3F(device->chipset)) 1115 cp_ctx(ctx, 0x404800, num); 1116 else 1117 cp_ctx(ctx, 0x405400, num); 1118 } 1119 1120 /* 1121 * xfer areas. These are a pain. 1122 * 1123 * There are 2 xfer areas: the first one is big and contains all sorts of 1124 * stuff, the second is small and contains some per-TP context. 1125 * 1126 * Each area is split into 8 "strands". The areas, when saved to grctx, 1127 * are made of 8-word blocks. Each block contains a single word from 1128 * each strand. The strands are independent of each other, their 1129 * addresses are unrelated to each other, and data in them is closely 1130 * packed together. The strand layout varies a bit between cards: here 1131 * and there, a single word is thrown out in the middle and the whole 1132 * strand is offset by a bit from corresponding one on another chipset. 1133 * For this reason, addresses of stuff in strands are almost useless. 1134 * Knowing sequence of stuff and size of gaps between them is much more 1135 * useful, and that's how we build the strands in our generator. 1136 * 1137 * NVA0 takes this mess to a whole new level by cutting the old strands 1138 * into a few dozen pieces [known as genes], rearranging them randomly, 1139 * and putting them back together to make new strands. Hopefully these 1140 * genes correspond more or less directly to the same PGRAPH subunits 1141 * as in 400040 register. 1142 * 1143 * The most common value in default context is 0, and when the genes 1144 * are separated by 0's, gene bounduaries are quite speculative... 1145 * some of them can be clearly deduced, others can be guessed, and yet 1146 * others won't be resolved without figuring out the real meaning of 1147 * given ctxval. For the same reason, ending point of each strand 1148 * is unknown. Except for strand 0, which is the longest strand and 1149 * its end corresponds to end of the whole xfer. 1150 * 1151 * An unsolved mystery is the seek instruction: it takes an argument 1152 * in bits 8-18, and that argument is clearly the place in strands to 1153 * seek to... but the offsets don't seem to correspond to offsets as 1154 * seen in grctx. Perhaps there's another, real, not randomly-changing 1155 * addressing in strands, and the xfer insn just happens to skip over 1156 * the unused bits? NV10-NV30 PIPE comes to mind... 1157 * 1158 * As far as I know, there's no way to access the xfer areas directly 1159 * without the help of ctxprog. 1160 */ 1161 1162 static void 1163 xf_emit(struct nvkm_grctx *ctx, int num, u32 val) { 1164 int i; 1165 if (val && ctx->mode == NVKM_GRCTX_VALS) { 1166 for (i = 0; i < num; i++) 1167 nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); 1168 } 1169 ctx->ctxvals_pos += num << 3; 1170 } 1171 1172 /* Gene declarations... */ 1173 1174 static void nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx); 1175 static void nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx); 1176 static void nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx); 1177 static void nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx); 1178 static void nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx); 1179 static void nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx); 1180 static void nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx); 1181 static void nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx); 1182 static void nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx); 1183 static void nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx); 1184 static void nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx); 1185 static void nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx); 1186 static void nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx); 1187 static void nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx); 1188 static void nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx); 1189 static void nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx); 1190 static void nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx); 1191 static void nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx); 1192 1193 static void 1194 nv50_gr_construct_xfer1(struct nvkm_grctx *ctx) 1195 { 1196 struct nvkm_device *device = ctx->device; 1197 int i; 1198 int offset; 1199 int size = 0; 1200 u32 units = nvkm_rd32(device, 0x1540); 1201 1202 offset = (ctx->ctxvals_pos+0x3f)&~0x3f; 1203 ctx->ctxvals_base = offset; 1204 1205 if (device->chipset < 0xa0) { 1206 /* Strand 0 */ 1207 ctx->ctxvals_pos = offset; 1208 nv50_gr_construct_gene_dispatch(ctx); 1209 nv50_gr_construct_gene_m2mf(ctx); 1210 nv50_gr_construct_gene_unk24xx(ctx); 1211 nv50_gr_construct_gene_clipid(ctx); 1212 nv50_gr_construct_gene_zcull(ctx); 1213 if ((ctx->ctxvals_pos-offset)/8 > size) 1214 size = (ctx->ctxvals_pos-offset)/8; 1215 1216 /* Strand 1 */ 1217 ctx->ctxvals_pos = offset + 0x1; 1218 nv50_gr_construct_gene_vfetch(ctx); 1219 nv50_gr_construct_gene_eng2d(ctx); 1220 nv50_gr_construct_gene_csched(ctx); 1221 nv50_gr_construct_gene_ropm1(ctx); 1222 nv50_gr_construct_gene_ropm2(ctx); 1223 if ((ctx->ctxvals_pos-offset)/8 > size) 1224 size = (ctx->ctxvals_pos-offset)/8; 1225 1226 /* Strand 2 */ 1227 ctx->ctxvals_pos = offset + 0x2; 1228 nv50_gr_construct_gene_ccache(ctx); 1229 nv50_gr_construct_gene_unk1cxx(ctx); 1230 nv50_gr_construct_gene_strmout(ctx); 1231 nv50_gr_construct_gene_unk14xx(ctx); 1232 nv50_gr_construct_gene_unk10xx(ctx); 1233 nv50_gr_construct_gene_unk34xx(ctx); 1234 if ((ctx->ctxvals_pos-offset)/8 > size) 1235 size = (ctx->ctxvals_pos-offset)/8; 1236 1237 /* Strand 3: per-ROP group state */ 1238 ctx->ctxvals_pos = offset + 3; 1239 for (i = 0; i < 6; i++) 1240 if (units & (1 << (i + 16))) 1241 nv50_gr_construct_gene_ropc(ctx); 1242 if ((ctx->ctxvals_pos-offset)/8 > size) 1243 size = (ctx->ctxvals_pos-offset)/8; 1244 1245 /* Strands 4-7: per-TP state */ 1246 for (i = 0; i < 4; i++) { 1247 ctx->ctxvals_pos = offset + 4 + i; 1248 if (units & (1 << (2 * i))) 1249 nv50_gr_construct_xfer_tp(ctx); 1250 if (units & (1 << (2 * i + 1))) 1251 nv50_gr_construct_xfer_tp(ctx); 1252 if ((ctx->ctxvals_pos-offset)/8 > size) 1253 size = (ctx->ctxvals_pos-offset)/8; 1254 } 1255 } else { 1256 /* Strand 0 */ 1257 ctx->ctxvals_pos = offset; 1258 nv50_gr_construct_gene_dispatch(ctx); 1259 nv50_gr_construct_gene_m2mf(ctx); 1260 nv50_gr_construct_gene_unk34xx(ctx); 1261 nv50_gr_construct_gene_csched(ctx); 1262 nv50_gr_construct_gene_unk1cxx(ctx); 1263 nv50_gr_construct_gene_strmout(ctx); 1264 if ((ctx->ctxvals_pos-offset)/8 > size) 1265 size = (ctx->ctxvals_pos-offset)/8; 1266 1267 /* Strand 1 */ 1268 ctx->ctxvals_pos = offset + 1; 1269 nv50_gr_construct_gene_unk10xx(ctx); 1270 if ((ctx->ctxvals_pos-offset)/8 > size) 1271 size = (ctx->ctxvals_pos-offset)/8; 1272 1273 /* Strand 2 */ 1274 ctx->ctxvals_pos = offset + 2; 1275 if (device->chipset == 0xa0) 1276 nv50_gr_construct_gene_unk14xx(ctx); 1277 nv50_gr_construct_gene_unk24xx(ctx); 1278 if ((ctx->ctxvals_pos-offset)/8 > size) 1279 size = (ctx->ctxvals_pos-offset)/8; 1280 1281 /* Strand 3 */ 1282 ctx->ctxvals_pos = offset + 3; 1283 nv50_gr_construct_gene_vfetch(ctx); 1284 if ((ctx->ctxvals_pos-offset)/8 > size) 1285 size = (ctx->ctxvals_pos-offset)/8; 1286 1287 /* Strand 4 */ 1288 ctx->ctxvals_pos = offset + 4; 1289 nv50_gr_construct_gene_ccache(ctx); 1290 if ((ctx->ctxvals_pos-offset)/8 > size) 1291 size = (ctx->ctxvals_pos-offset)/8; 1292 1293 /* Strand 5 */ 1294 ctx->ctxvals_pos = offset + 5; 1295 nv50_gr_construct_gene_ropm2(ctx); 1296 nv50_gr_construct_gene_ropm1(ctx); 1297 /* per-ROP context */ 1298 for (i = 0; i < 8; i++) 1299 if (units & (1<<(i+16))) 1300 nv50_gr_construct_gene_ropc(ctx); 1301 if ((ctx->ctxvals_pos-offset)/8 > size) 1302 size = (ctx->ctxvals_pos-offset)/8; 1303 1304 /* Strand 6 */ 1305 ctx->ctxvals_pos = offset + 6; 1306 nv50_gr_construct_gene_zcull(ctx); 1307 nv50_gr_construct_gene_clipid(ctx); 1308 nv50_gr_construct_gene_eng2d(ctx); 1309 if (units & (1 << 0)) 1310 nv50_gr_construct_xfer_tp(ctx); 1311 if (units & (1 << 1)) 1312 nv50_gr_construct_xfer_tp(ctx); 1313 if (units & (1 << 2)) 1314 nv50_gr_construct_xfer_tp(ctx); 1315 if (units & (1 << 3)) 1316 nv50_gr_construct_xfer_tp(ctx); 1317 if ((ctx->ctxvals_pos-offset)/8 > size) 1318 size = (ctx->ctxvals_pos-offset)/8; 1319 1320 /* Strand 7 */ 1321 ctx->ctxvals_pos = offset + 7; 1322 if (device->chipset == 0xa0) { 1323 if (units & (1 << 4)) 1324 nv50_gr_construct_xfer_tp(ctx); 1325 if (units & (1 << 5)) 1326 nv50_gr_construct_xfer_tp(ctx); 1327 if (units & (1 << 6)) 1328 nv50_gr_construct_xfer_tp(ctx); 1329 if (units & (1 << 7)) 1330 nv50_gr_construct_xfer_tp(ctx); 1331 if (units & (1 << 8)) 1332 nv50_gr_construct_xfer_tp(ctx); 1333 if (units & (1 << 9)) 1334 nv50_gr_construct_xfer_tp(ctx); 1335 } else { 1336 nv50_gr_construct_gene_unk14xx(ctx); 1337 } 1338 if ((ctx->ctxvals_pos-offset)/8 > size) 1339 size = (ctx->ctxvals_pos-offset)/8; 1340 } 1341 1342 ctx->ctxvals_pos = offset + size * 8; 1343 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; 1344 cp_lsr (ctx, offset); 1345 cp_out (ctx, CP_SET_XFER_POINTER); 1346 cp_lsr (ctx, size); 1347 cp_out (ctx, CP_SEEK_1); 1348 cp_out (ctx, CP_XFER_1); 1349 cp_wait(ctx, XFER, BUSY); 1350 } 1351 1352 /* 1353 * non-trivial demagiced parts of ctx init go here 1354 */ 1355 1356 static void 1357 nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx) 1358 { 1359 /* start of strand 0 */ 1360 struct nvkm_device *device = ctx->device; 1361 /* SEEK */ 1362 if (device->chipset == 0x50) 1363 xf_emit(ctx, 5, 0); 1364 else if (!IS_NVA3F(device->chipset)) 1365 xf_emit(ctx, 6, 0); 1366 else 1367 xf_emit(ctx, 4, 0); 1368 /* SEEK */ 1369 /* the PGRAPH's internal FIFO */ 1370 if (device->chipset == 0x50) 1371 xf_emit(ctx, 8*3, 0); 1372 else 1373 xf_emit(ctx, 0x100*3, 0); 1374 /* and another bonus slot?!? */ 1375 xf_emit(ctx, 3, 0); 1376 /* and YET ANOTHER bonus slot? */ 1377 if (IS_NVA3F(device->chipset)) 1378 xf_emit(ctx, 3, 0); 1379 /* SEEK */ 1380 /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */ 1381 xf_emit(ctx, 9, 0); 1382 /* SEEK */ 1383 xf_emit(ctx, 9, 0); 1384 /* SEEK */ 1385 xf_emit(ctx, 9, 0); 1386 /* SEEK */ 1387 xf_emit(ctx, 9, 0); 1388 /* SEEK */ 1389 if (device->chipset < 0x90) 1390 xf_emit(ctx, 4, 0); 1391 /* SEEK */ 1392 xf_emit(ctx, 2, 0); 1393 /* SEEK */ 1394 xf_emit(ctx, 6*2, 0); 1395 xf_emit(ctx, 2, 0); 1396 /* SEEK */ 1397 xf_emit(ctx, 2, 0); 1398 /* SEEK */ 1399 xf_emit(ctx, 6*2, 0); 1400 xf_emit(ctx, 2, 0); 1401 /* SEEK */ 1402 if (device->chipset == 0x50) 1403 xf_emit(ctx, 0x1c, 0); 1404 else if (device->chipset < 0xa0) 1405 xf_emit(ctx, 0x1e, 0); 1406 else 1407 xf_emit(ctx, 0x22, 0); 1408 /* SEEK */ 1409 xf_emit(ctx, 0x15, 0); 1410 } 1411 1412 static void 1413 nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx) 1414 { 1415 /* Strand 0, right after dispatch */ 1416 struct nvkm_device *device = ctx->device; 1417 int smallm2mf = 0; 1418 if (device->chipset < 0x92 || device->chipset == 0x98) 1419 smallm2mf = 1; 1420 /* SEEK */ 1421 xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ 1422 xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ 1423 xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ 1424 xf_emit (ctx, 1, 0); /* OFFSET_IN */ 1425 xf_emit (ctx, 1, 0); /* OFFSET_OUT */ 1426 xf_emit (ctx, 1, 0); /* PITCH_IN */ 1427 xf_emit (ctx, 1, 0); /* PITCH_OUT */ 1428 xf_emit (ctx, 1, 0); /* LINE_LENGTH */ 1429 xf_emit (ctx, 1, 0); /* LINE_COUNT */ 1430 xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ 1431 xf_emit (ctx, 1, 1); /* LINEAR_IN */ 1432 xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ 1433 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ 1434 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ 1435 xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ 1436 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ 1437 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ 1438 xf_emit (ctx, 1, 1); /* LINEAR_OUT */ 1439 xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ 1440 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ 1441 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ 1442 xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ 1443 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ 1444 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ 1445 xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ 1446 xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ 1447 /* SEEK */ 1448 if (smallm2mf) 1449 xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */ 1450 else 1451 xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */ 1452 xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */ 1453 /* SEEK */ 1454 if (smallm2mf) 1455 xf_emit(ctx, 0x400, 0); /* ffffffff */ 1456 else 1457 xf_emit(ctx, 0x800, 0); /* ffffffff */ 1458 xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */ 1459 /* SEEK */ 1460 xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */ 1461 xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */ 1462 } 1463 1464 static void 1465 nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx) 1466 { 1467 struct nvkm_device *device = ctx->device; 1468 xf_emit(ctx, 2, 0); /* RO */ 1469 xf_emit(ctx, 0x800, 0); /* ffffffff */ 1470 switch (device->chipset) { 1471 case 0x50: 1472 case 0x92: 1473 case 0xa0: 1474 xf_emit(ctx, 0x2b, 0); 1475 break; 1476 case 0x84: 1477 xf_emit(ctx, 0x29, 0); 1478 break; 1479 case 0x94: 1480 case 0x96: 1481 case 0xa3: 1482 xf_emit(ctx, 0x27, 0); 1483 break; 1484 case 0x86: 1485 case 0x98: 1486 case 0xa5: 1487 case 0xa8: 1488 case 0xaa: 1489 case 0xac: 1490 case 0xaf: 1491 xf_emit(ctx, 0x25, 0); 1492 break; 1493 } 1494 /* CB bindings, 0x80 of them. first word is address >> 8, second is 1495 * size >> 4 | valid << 24 */ 1496 xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */ 1497 xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */ 1498 xf_emit(ctx, 1, 0); /* 0 */ 1499 xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */ 1500 xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */ 1501 xf_emit(ctx, 4, 0); /* RO */ 1502 xf_emit(ctx, 0x100, 0); /* ffffffff */ 1503 xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */ 1504 xf_emit(ctx, 8, 0); /* ffffffff */ 1505 xf_emit(ctx, 4, 0); /* ffffffff */ 1506 xf_emit(ctx, 1, 0); /* 3 */ 1507 xf_emit(ctx, 1, 0); /* ffffffff */ 1508 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */ 1509 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */ 1510 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */ 1511 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ 1512 xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */ 1513 xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */ 1514 xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ 1515 xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */ 1516 xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */ 1517 xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ 1518 xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */ 1519 xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */ 1520 xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */ 1521 xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ 1522 xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ 1523 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1524 xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */ 1525 xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */ 1526 xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */ 1527 xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */ 1528 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ 1529 xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */ 1530 } 1531 1532 static void 1533 nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx) 1534 { 1535 struct nvkm_device *device = ctx->device; 1536 int i; 1537 /* end of area 2 on pre-NVA0, area 1 on NVAx */ 1538 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1539 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1540 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1541 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 1542 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 1543 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1544 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1545 if (device->chipset == 0x50) 1546 xf_emit(ctx, 1, 0x3ff); 1547 else 1548 xf_emit(ctx, 1, 0x7ff); /* 000007ff */ 1549 xf_emit(ctx, 1, 0); /* 111/113 */ 1550 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1551 for (i = 0; i < 8; i++) { 1552 switch (device->chipset) { 1553 case 0x50: 1554 case 0x86: 1555 case 0x98: 1556 case 0xaa: 1557 case 0xac: 1558 xf_emit(ctx, 0xa0, 0); /* ffffffff */ 1559 break; 1560 case 0x84: 1561 case 0x92: 1562 case 0x94: 1563 case 0x96: 1564 xf_emit(ctx, 0x120, 0); 1565 break; 1566 case 0xa5: 1567 case 0xa8: 1568 xf_emit(ctx, 0x100, 0); /* ffffffff */ 1569 break; 1570 case 0xa0: 1571 case 0xa3: 1572 case 0xaf: 1573 xf_emit(ctx, 0x400, 0); /* ffffffff */ 1574 break; 1575 } 1576 xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */ 1577 xf_emit(ctx, 4, 0); /* ffffffff */ 1578 } 1579 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1580 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1581 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1582 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 1583 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */ 1584 xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */ 1585 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1586 xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ 1587 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1588 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1589 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1590 } 1591 1592 static void 1593 nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx) 1594 { 1595 struct nvkm_device *device = ctx->device; 1596 /* end of area 2 on pre-NVA0, area 1 on NVAx */ 1597 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ 1598 xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */ 1599 xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */ 1600 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ 1601 xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */ 1602 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 1603 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 1604 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ 1605 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ 1606 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1607 xf_emit(ctx, 1, 0); /* 00000007 */ 1608 xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */ 1609 if (device->chipset >= 0xa0) 1610 xf_emit(ctx, 1, 0x0fac6881); 1611 if (IS_NVA3F(device->chipset)) { 1612 xf_emit(ctx, 1, 1); 1613 xf_emit(ctx, 3, 0); 1614 } 1615 } 1616 1617 static void 1618 nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx) 1619 { 1620 struct nvkm_device *device = ctx->device; 1621 /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ 1622 if (device->chipset != 0x50) { 1623 xf_emit(ctx, 5, 0); /* ffffffff */ 1624 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1625 xf_emit(ctx, 1, 0); /* 00000001 */ 1626 xf_emit(ctx, 1, 0); /* 000003ff */ 1627 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ 1628 xf_emit(ctx, 1, 0); /* 00000001 */ 1629 xf_emit(ctx, 2, 4); /* 7f, ff */ 1630 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1631 } 1632 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1633 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1634 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1635 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1636 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 1637 xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */ 1638 if (device->chipset != 0x50) 1639 xf_emit(ctx, 1, 0); /* 3ff */ 1640 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */ 1641 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ 1642 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ 1643 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1644 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1645 if (device->chipset != 0x50) 1646 xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */ 1647 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1648 xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */ 1649 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1650 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1651 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1652 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1653 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1654 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1655 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 1656 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ 1657 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */ 1658 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1659 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1660 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1661 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ 1662 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1663 xf_emit(ctx, 1, 0); /* 0000000f */ 1664 if (device->chipset == 0x50) 1665 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ 1666 else 1667 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ 1668 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1669 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1670 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */ 1671 xf_emit(ctx, 3, 0); /* f, 0, 0 */ 1672 xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */ 1673 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1674 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ 1675 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1676 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 1677 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 1678 xf_emit(ctx, 1, 0); /* 00000001 */ 1679 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */ 1680 xf_emit(ctx, 3, 0); /* f, 0, 0 */ 1681 xf_emit(ctx, 3, 0); /* ffffffff */ 1682 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1683 xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */ 1684 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 1685 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1686 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 1687 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 1688 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 1689 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1690 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 1691 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1692 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1693 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1694 xf_emit(ctx, 1, 0); /* 0000000f */ 1695 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ 1696 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 1697 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 1698 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 1699 if (IS_NVA3F(device->chipset)) 1700 xf_emit(ctx, 1, 0); /* 00000001 */ 1701 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1702 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 1703 if (device->chipset != 0x50) { 1704 xf_emit(ctx, 1, 0); /* ffffffff */ 1705 xf_emit(ctx, 1, 0); /* 00000001 */ 1706 xf_emit(ctx, 1, 0); /* 000003ff */ 1707 } 1708 xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */ 1709 xf_emit(ctx, 1, 0); /* f */ 1710 xf_emit(ctx, 1, 0); /* 0? */ 1711 xf_emit(ctx, 1, 0); /* ffffffff */ 1712 xf_emit(ctx, 1, 0); /* 003fffff */ 1713 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1714 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ 1715 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1716 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ 1717 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 1718 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1719 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1720 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1721 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1722 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 1723 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 1724 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 1725 xf_emit(ctx, 1, 0); /* 0000000f */ 1726 } 1727 1728 static void 1729 nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx) 1730 { 1731 struct nvkm_device *device = ctx->device; 1732 /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */ 1733 /* SEEK */ 1734 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ 1735 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 1736 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 1737 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 1738 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 1739 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 1740 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 1741 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 1742 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 1743 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 1744 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ 1745 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 1746 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ 1747 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 1748 xf_emit(ctx, 1, 0); /* 00000001 */ 1749 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 1750 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 1751 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 1752 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 1753 xf_emit(ctx, 1, 0); /* 0000ffff */ 1754 xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */ 1755 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ 1756 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 1757 xf_emit(ctx, 1, 0); /* ffffffff */ 1758 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 1759 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ 1760 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 1761 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 1762 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 1763 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 1764 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 1765 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 1766 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 1767 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 1768 xf_emit(ctx, 1, 0); /* 00000007 */ 1769 if (device->chipset != 0x50) 1770 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */ 1771 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 1772 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 1773 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 1774 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ 1775 /* SEEK */ 1776 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 1777 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 1778 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 1779 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 1780 xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */ 1781 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ 1782 xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */ 1783 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */ 1784 if (device->chipset != 0x50) 1785 xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */ 1786 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */ 1787 } 1788 1789 static void 1790 nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx) 1791 { 1792 /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */ 1793 /* SEEK */ 1794 xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */ 1795 /* SEEK */ 1796 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */ 1797 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */ 1798 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 1799 xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */ 1800 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ 1801 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */ 1802 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */ 1803 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */ 1804 xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */ 1805 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */ 1806 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */ 1807 } 1808 1809 static void 1810 nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx) 1811 { 1812 struct nvkm_device *device = ctx->device; 1813 int i; 1814 /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */ 1815 /* SEEK */ 1816 xf_emit(ctx, 0x33, 0); 1817 /* SEEK */ 1818 xf_emit(ctx, 2, 0); 1819 /* SEEK */ 1820 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1821 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1822 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1823 /* SEEK */ 1824 if (IS_NVA3F(device->chipset)) { 1825 xf_emit(ctx, 4, 0); /* RO */ 1826 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1827 xf_emit(ctx, 1, 0); /* 1ff */ 1828 xf_emit(ctx, 8, 0); /* 0? */ 1829 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ 1830 1831 xf_emit(ctx, 4, 0); /* RO */ 1832 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1833 xf_emit(ctx, 1, 0); /* 1ff */ 1834 xf_emit(ctx, 8, 0); /* 0? */ 1835 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ 1836 } else { 1837 xf_emit(ctx, 0xc, 0); /* RO */ 1838 /* SEEK */ 1839 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1840 xf_emit(ctx, 1, 0); /* 1ff */ 1841 xf_emit(ctx, 8, 0); /* 0? */ 1842 1843 /* SEEK */ 1844 xf_emit(ctx, 0xc, 0); /* RO */ 1845 /* SEEK */ 1846 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ 1847 xf_emit(ctx, 1, 0); /* 1ff */ 1848 xf_emit(ctx, 8, 0); /* 0? */ 1849 } 1850 /* SEEK */ 1851 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1852 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 1853 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 1854 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1855 if (device->chipset != 0x50) 1856 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 1857 /* SEEK */ 1858 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1859 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1860 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1861 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1862 xf_emit(ctx, 1, 1); /* 00000001 */ 1863 /* SEEK */ 1864 if (device->chipset >= 0xa0) 1865 xf_emit(ctx, 2, 4); /* 000000ff */ 1866 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ 1867 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 1868 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 1869 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1870 xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */ 1871 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1872 xf_emit(ctx, 1, 0); /* 0000000f */ 1873 xf_emit(ctx, 1, 1); /* 00000001 */ 1874 for (i = 0; i < 10; i++) { 1875 /* SEEK */ 1876 xf_emit(ctx, 0x40, 0); /* ffffffff */ 1877 xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */ 1878 xf_emit(ctx, 0x10, 0); /* ffffffff */ 1879 } 1880 /* SEEK */ 1881 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */ 1882 xf_emit(ctx, 1, 1); /* 00000001 */ 1883 xf_emit(ctx, 1, 0); /* ffffffff */ 1884 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ 1885 xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */ 1886 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 1887 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 1888 if (device->chipset != 0x50) 1889 xf_emit(ctx, 1, 0); /* 000003ff */ 1890 } 1891 1892 static void 1893 nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx) 1894 { 1895 struct nvkm_device *device = ctx->device; 1896 int acnt = 0x10, rep, i; 1897 /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */ 1898 if (IS_NVA3F(device->chipset)) 1899 acnt = 0x20; 1900 /* SEEK */ 1901 if (device->chipset >= 0xa0) { 1902 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */ 1903 xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */ 1904 } 1905 xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */ 1906 xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */ 1907 xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */ 1908 xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */ 1909 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 1910 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 1911 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */ 1912 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1913 xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */ 1914 xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */ 1915 xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */ 1916 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 1917 /* SEEK */ 1918 if (IS_NVA3F(device->chipset)) 1919 xf_emit(ctx, 0xb, 0); /* RO */ 1920 else if (device->chipset >= 0xa0) 1921 xf_emit(ctx, 0x9, 0); /* RO */ 1922 else 1923 xf_emit(ctx, 0x8, 0); /* RO */ 1924 /* SEEK */ 1925 xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */ 1926 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 1927 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1928 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 1929 /* SEEK */ 1930 xf_emit(ctx, 0xc, 0); /* RO */ 1931 /* SEEK */ 1932 xf_emit(ctx, 1, 0); /* 7f/ff */ 1933 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 1934 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 1935 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1936 xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */ 1937 xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */ 1938 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 1939 if (device->chipset == 0x50) 1940 xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */ 1941 else 1942 xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */ 1943 if (device->chipset == 0xa8) 1944 xf_emit(ctx, 1, 0x1e00); /* 7fff */ 1945 /* SEEK */ 1946 xf_emit(ctx, 0xc, 0); /* RO or close */ 1947 /* SEEK */ 1948 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 1949 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 1950 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 1951 if (device->chipset > 0x50 && device->chipset < 0xa0) 1952 xf_emit(ctx, 2, 0); /* ffffffff */ 1953 else 1954 xf_emit(ctx, 1, 0); /* ffffffff */ 1955 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */ 1956 /* SEEK */ 1957 if (IS_NVA3F(device->chipset)) { 1958 xf_emit(ctx, 0x10, 0); /* 0? */ 1959 xf_emit(ctx, 2, 0); /* weird... */ 1960 xf_emit(ctx, 2, 0); /* RO */ 1961 } else { 1962 xf_emit(ctx, 8, 0); /* 0? */ 1963 xf_emit(ctx, 1, 0); /* weird... */ 1964 xf_emit(ctx, 2, 0); /* RO */ 1965 } 1966 /* SEEK */ 1967 xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */ 1968 xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */ 1969 xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */ 1970 if (device->chipset >= 0xa0) 1971 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */ 1972 /* SEEK */ 1973 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ 1974 xf_emit(ctx, 1, 0); /* f/1f */ 1975 /* SEEK */ 1976 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ 1977 xf_emit(ctx, 1, 0); /* f/1f */ 1978 /* SEEK */ 1979 xf_emit(ctx, acnt, 0); /* RO */ 1980 xf_emit(ctx, 2, 0); /* RO */ 1981 /* SEEK */ 1982 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */ 1983 xf_emit(ctx, 1, 0); /* RO */ 1984 /* SEEK */ 1985 xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */ 1986 xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */ 1987 xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */ 1988 xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */ 1989 /* SEEK */ 1990 xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */ 1991 xf_emit(ctx, 3, 0); /* f/1f */ 1992 /* SEEK */ 1993 xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */ 1994 xf_emit(ctx, 3, 0); /* f/1f */ 1995 /* SEEK */ 1996 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */ 1997 xf_emit(ctx, 3, 0); /* f/1f */ 1998 /* SEEK */ 1999 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */ 2000 xf_emit(ctx, 3, 0); /* f/1f */ 2001 /* SEEK */ 2002 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */ 2003 xf_emit(ctx, 3, 0); /* f/1f */ 2004 /* SEEK */ 2005 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */ 2006 xf_emit(ctx, 3, 0); /* f/1f */ 2007 /* SEEK */ 2008 if (IS_NVA3F(device->chipset)) { 2009 xf_emit(ctx, acnt, 0); /* f */ 2010 xf_emit(ctx, 3, 0); /* f/1f */ 2011 } 2012 /* SEEK */ 2013 if (IS_NVA3F(device->chipset)) 2014 xf_emit(ctx, 2, 0); /* RO */ 2015 else 2016 xf_emit(ctx, 5, 0); /* RO */ 2017 /* SEEK */ 2018 xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */ 2019 /* SEEK */ 2020 if (device->chipset < 0xa0) { 2021 xf_emit(ctx, 0x41, 0); /* RO */ 2022 /* SEEK */ 2023 xf_emit(ctx, 0x11, 0); /* RO */ 2024 } else if (!IS_NVA3F(device->chipset)) 2025 xf_emit(ctx, 0x50, 0); /* RO */ 2026 else 2027 xf_emit(ctx, 0x58, 0); /* RO */ 2028 /* SEEK */ 2029 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2030 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2031 xf_emit(ctx, 1, 1); /* 1 UNK0DEC */ 2032 /* SEEK */ 2033 xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */ 2034 xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */ 2035 /* SEEK */ 2036 if (IS_NVA3F(device->chipset)) 2037 xf_emit(ctx, 0x1d, 0); /* RO */ 2038 else 2039 xf_emit(ctx, 0x16, 0); /* RO */ 2040 /* SEEK */ 2041 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2042 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2043 /* SEEK */ 2044 if (device->chipset < 0xa0) 2045 xf_emit(ctx, 8, 0); /* RO */ 2046 else if (IS_NVA3F(device->chipset)) 2047 xf_emit(ctx, 0xc, 0); /* RO */ 2048 else 2049 xf_emit(ctx, 7, 0); /* RO */ 2050 /* SEEK */ 2051 xf_emit(ctx, 0xa, 0); /* RO */ 2052 if (device->chipset == 0xa0) 2053 rep = 0xc; 2054 else 2055 rep = 4; 2056 for (i = 0; i < rep; i++) { 2057 /* SEEK */ 2058 if (IS_NVA3F(device->chipset)) 2059 xf_emit(ctx, 0x20, 0); /* ffffffff */ 2060 xf_emit(ctx, 0x200, 0); /* ffffffff */ 2061 xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */ 2062 xf_emit(ctx, 4, 0); /* ffffffff */ 2063 } 2064 /* SEEK */ 2065 xf_emit(ctx, 1, 0); /* 113/111 */ 2066 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ 2067 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ 2068 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */ 2069 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ 2070 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2071 /* SEEK */ 2072 if (IS_NVA3F(device->chipset)) 2073 xf_emit(ctx, 7, 0); /* weird... */ 2074 else 2075 xf_emit(ctx, 5, 0); /* weird... */ 2076 } 2077 2078 static void 2079 nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx) 2080 { 2081 struct nvkm_device *device = ctx->device; 2082 /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */ 2083 /* SEEK */ 2084 xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */ 2085 xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */ 2086 xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */ 2087 if (device->chipset < 0xa0) { 2088 /* this is useless on everything but the original NV50, 2089 * guess they forgot to nuke it. Or just didn't bother. */ 2090 xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */ 2091 xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */ 2092 xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */ 2093 } 2094 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2095 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ 2096 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ 2097 xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */ 2098 xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */ 2099 xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */ 2100 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */ 2101 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */ 2102 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */ 2103 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */ 2104 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */ 2105 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */ 2106 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */ 2107 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */ 2108 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */ 2109 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */ 2110 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ 2111 xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */ 2112 xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */ 2113 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */ 2114 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */ 2115 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */ 2116 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */ 2117 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ 2118 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ 2119 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ 2120 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ 2121 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */ 2122 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */ 2123 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */ 2124 xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */ 2125 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */ 2126 xf_emit(ctx, 1, 0); /* 00000001 UNK888 */ 2127 xf_emit(ctx, 1, 4); /* 0000003f UNK884 */ 2128 xf_emit(ctx, 1, 0); /* 00000007 UNK880 */ 2129 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */ 2130 xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */ 2131 xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */ 2132 xf_emit(ctx, 1, 0); /* 00000001 UNK260 */ 2133 xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */ 2134 /* SEEK */ 2135 xf_emit(ctx, 0x10, 0); 2136 /* SEEK */ 2137 xf_emit(ctx, 0x27, 0); 2138 } 2139 2140 static void 2141 nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx) 2142 { 2143 struct nvkm_device *device = ctx->device; 2144 /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */ 2145 /* SEEK */ 2146 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */ 2147 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ 2148 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2149 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 2150 xf_emit(ctx, 1, 0); /* 000003ff */ 2151 /* SEEK */ 2152 xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */ 2153 xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */ 2154 xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */ 2155 xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */ 2156 xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */ 2157 xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */ 2158 xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */ 2159 xf_emit(ctx, 1, 0); /* ffffffff */ 2160 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ 2161 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ 2162 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ 2163 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ 2164 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 2165 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 2166 /* SEEK */ 2167 xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */ 2168 switch (device->chipset) { 2169 case 0x50: 2170 case 0x92: 2171 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2172 xf_emit(ctx, 0x80, 0); /* fff */ 2173 xf_emit(ctx, 2, 0); /* ff, fff */ 2174 xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */ 2175 break; 2176 case 0x84: 2177 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2178 xf_emit(ctx, 0x60, 0); /* fff */ 2179 xf_emit(ctx, 2, 0); /* ff, fff */ 2180 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ 2181 break; 2182 case 0x94: 2183 case 0x96: 2184 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2185 xf_emit(ctx, 0x40, 0); /* fff */ 2186 xf_emit(ctx, 2, 0); /* ff, fff */ 2187 xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */ 2188 break; 2189 case 0x86: 2190 case 0x98: 2191 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ 2192 xf_emit(ctx, 0x10, 0); /* fff */ 2193 xf_emit(ctx, 2, 0); /* ff, fff */ 2194 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ 2195 break; 2196 case 0xa0: 2197 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2198 xf_emit(ctx, 0xf0, 0); /* fff */ 2199 xf_emit(ctx, 2, 0); /* ff, fff */ 2200 xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */ 2201 break; 2202 case 0xa3: 2203 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2204 xf_emit(ctx, 0x60, 0); /* fff */ 2205 xf_emit(ctx, 2, 0); /* ff, fff */ 2206 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ 2207 break; 2208 case 0xa5: 2209 case 0xaf: 2210 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ 2211 xf_emit(ctx, 0x30, 0); /* fff */ 2212 xf_emit(ctx, 2, 0); /* ff, fff */ 2213 xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */ 2214 break; 2215 case 0xaa: 2216 xf_emit(ctx, 0x12, 0); 2217 break; 2218 case 0xa8: 2219 case 0xac: 2220 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ 2221 xf_emit(ctx, 0x10, 0); /* fff */ 2222 xf_emit(ctx, 2, 0); /* ff, fff */ 2223 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ 2224 break; 2225 } 2226 xf_emit(ctx, 1, 0); /* 0000000f */ 2227 xf_emit(ctx, 1, 0); /* 00000000 */ 2228 xf_emit(ctx, 1, 0); /* ffffffff */ 2229 xf_emit(ctx, 1, 0); /* 0000001f */ 2230 xf_emit(ctx, 4, 0); /* ffffffff */ 2231 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ 2232 xf_emit(ctx, 1, 0); /* ffffffff */ 2233 xf_emit(ctx, 4, 0); /* ffffffff */ 2234 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ 2235 xf_emit(ctx, 1, 0); /* ffffffff */ 2236 xf_emit(ctx, 1, 0); /* 000000ff */ 2237 } 2238 2239 static void 2240 nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx) 2241 { 2242 struct nvkm_device *device = ctx->device; 2243 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 2244 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ 2245 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 2246 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ 2247 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ 2248 xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */ 2249 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ 2250 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 2251 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2252 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 2253 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ 2254 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ 2255 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2256 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 2257 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 2258 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */ 2259 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */ 2260 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ 2261 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ 2262 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 2263 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2264 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2265 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2266 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ 2267 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ 2268 xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */ 2269 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2270 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2271 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2272 if (IS_NVA3F(device->chipset)) 2273 xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */ 2274 else if (device->chipset >= 0xa0) 2275 xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */ 2276 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 2277 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ 2278 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2279 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ 2280 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2281 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2282 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2283 xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */ 2284 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ 2285 xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */ 2286 xf_emit(ctx, 1, 0); /* 00000001 */ 2287 xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */ 2288 if (device->chipset != 0x50) { 2289 xf_emit(ctx, 1, 0); /* 3ff */ 2290 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */ 2291 } 2292 if (IS_NVA3F(device->chipset)) 2293 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ 2294 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 2295 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 2296 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ 2297 xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */ 2298 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */ 2299 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2300 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2301 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2302 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2303 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2304 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 2305 xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */ 2306 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2307 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */ 2308 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2309 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 2310 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 2311 if (device->chipset != 0x50) 2312 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 2313 if (device->chipset < 0xa0) 2314 xf_emit(ctx, 0x1c, 0); /* RO */ 2315 else if (IS_NVA3F(device->chipset)) 2316 xf_emit(ctx, 0x9, 0); 2317 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 2318 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 2319 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 2320 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 2321 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 2322 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ 2323 if (device->chipset != 0x50) { 2324 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ 2325 xf_emit(ctx, 1, 0); /* 3ff */ 2326 } 2327 /* XXX: the following block could belong either to unk1cxx, or 2328 * to STRMOUT. Rather hard to tell. */ 2329 if (device->chipset < 0xa0) 2330 xf_emit(ctx, 0x25, 0); 2331 else 2332 xf_emit(ctx, 0x3b, 0); 2333 } 2334 2335 static void 2336 nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx) 2337 { 2338 struct nvkm_device *device = ctx->device; 2339 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ 2340 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ 2341 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ 2342 if (device->chipset >= 0xa0) { 2343 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ 2344 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ 2345 } 2346 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2347 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ 2348 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2349 if (device->chipset == 0x50) 2350 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ 2351 else 2352 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ 2353 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2354 /* SEEK */ 2355 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ 2356 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ 2357 xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */ 2358 xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */ 2359 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ 2360 if (device->chipset >= 0xa0) { 2361 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ 2362 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ 2363 } 2364 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */ 2365 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2366 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2367 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */ 2368 xf_emit(ctx, 2, 0); /* ffffffff */ 2369 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2370 /* SEEK */ 2371 xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */ 2372 xf_emit(ctx, 1, 0); /* 0000000f */ 2373 xf_emit(ctx, 1, 0); /* 00000000? */ 2374 xf_emit(ctx, 2, 0); /* ffffffff */ 2375 } 2376 2377 static void 2378 nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx) 2379 { 2380 struct nvkm_device *device = ctx->device; 2381 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ 2382 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ 2383 xf_emit(ctx, 1, 0); /* 00000007 */ 2384 xf_emit(ctx, 1, 0); /* 000003ff */ 2385 if (IS_NVA3F(device->chipset)) 2386 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ 2387 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2388 } 2389 2390 static void 2391 nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx) 2392 { 2393 struct nvkm_device *device = ctx->device; 2394 /* SEEK */ 2395 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2396 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2397 xf_emit(ctx, 2, 0); /* ffffffff */ 2398 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2399 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ 2400 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2401 xf_emit(ctx, 1, 0); /* 7 */ 2402 /* SEEK */ 2403 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ 2404 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ 2405 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ 2406 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ 2407 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ 2408 xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */ 2409 xf_emit(ctx, 1, 0); /* ff/3ff */ 2410 xf_emit(ctx, 1, 0); /* 00000007 */ 2411 if (IS_NVA3F(device->chipset)) 2412 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ 2413 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2414 } 2415 2416 static void 2417 nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx) 2418 { 2419 struct nvkm_device *device = ctx->device; 2420 int magic2; 2421 if (device->chipset == 0x50) { 2422 magic2 = 0x00003e60; 2423 } else if (!IS_NVA3F(device->chipset)) { 2424 magic2 = 0x001ffe67; 2425 } else { 2426 magic2 = 0x00087e67; 2427 } 2428 xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */ 2429 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2430 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2431 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2432 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2433 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2434 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2435 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2436 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2437 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2438 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2439 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2440 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2441 if (IS_NVA3F(device->chipset)) 2442 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2443 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2444 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2445 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2446 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2447 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2448 if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset)) 2449 xf_emit(ctx, 1, 0x15); /* 000000ff */ 2450 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2451 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2452 xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */ 2453 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 2454 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2455 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2456 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2457 if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) { 2458 xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */ 2459 xf_emit(ctx, 1, 4); /* 7 */ 2460 xf_emit(ctx, 1, 0x400); /* fffffff */ 2461 xf_emit(ctx, 1, 0x300); /* ffff */ 2462 xf_emit(ctx, 1, 0x1001); /* 1fff */ 2463 if (device->chipset != 0xa0) { 2464 if (IS_NVA3F(device->chipset)) 2465 xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */ 2466 else 2467 xf_emit(ctx, 1, 0x15); /* ff */ 2468 } 2469 } 2470 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2471 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2472 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2473 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2474 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2475 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2476 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2477 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2478 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2479 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2480 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2481 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2482 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2483 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2484 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2485 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2486 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2487 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2488 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2489 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2490 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ 2491 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2492 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2493 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 2494 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 2495 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2496 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2497 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2498 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2499 xf_emit(ctx, 1, 0); /* 0000000f */ 2500 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2501 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2502 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2503 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 2504 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2505 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2506 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2507 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ 2508 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ 2509 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2510 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2511 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ 2512 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ 2513 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ 2514 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2515 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2516 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ 2517 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2518 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ 2519 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2520 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2521 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ 2522 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ 2523 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ 2524 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ 2525 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2526 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2527 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2528 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2529 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ 2530 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2531 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ 2532 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2533 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2534 xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */ 2535 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2536 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2537 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2538 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2539 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2540 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ 2541 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2542 if (device->chipset >= 0xa0) { 2543 xf_emit(ctx, 2, 0); 2544 xf_emit(ctx, 1, 0x1001); 2545 xf_emit(ctx, 0xb, 0); 2546 } else { 2547 xf_emit(ctx, 1, 0); /* 00000007 */ 2548 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2549 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2550 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2551 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2552 } 2553 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2554 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2555 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2556 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2557 xf_emit(ctx, 1, 0x11); /* 3f/7f */ 2558 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2559 if (device->chipset != 0x50) { 2560 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ 2561 xf_emit(ctx, 1, 0); /* 000000ff */ 2562 } 2563 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2564 xf_emit(ctx, 1, 0); /* ff/3ff */ 2565 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2566 xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */ 2567 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2568 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2569 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2570 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2571 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2572 xf_emit(ctx, 1, 0); /* 00000001 */ 2573 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2574 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2575 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2576 if (IS_NVA3F(device->chipset)) { 2577 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */ 2578 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2579 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2580 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2581 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 2582 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 2583 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 2584 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 2585 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ 2586 xf_emit(ctx, 2, 0); /* 00000001 */ 2587 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2588 xf_emit(ctx, 1, 0); /* 0000000f */ 2589 xf_emit(ctx, 1, 0); /* 00000003 */ 2590 xf_emit(ctx, 1, 0); /* ffffffff */ 2591 xf_emit(ctx, 2, 0); /* 00000001 */ 2592 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2593 xf_emit(ctx, 1, 0); /* 00000001 */ 2594 xf_emit(ctx, 1, 0); /* 000003ff */ 2595 } else if (device->chipset >= 0xa0) { 2596 xf_emit(ctx, 2, 0); /* 00000001 */ 2597 xf_emit(ctx, 1, 0); /* 00000007 */ 2598 xf_emit(ctx, 1, 0); /* 00000003 */ 2599 xf_emit(ctx, 1, 0); /* ffffffff */ 2600 xf_emit(ctx, 2, 0); /* 00000001 */ 2601 } else { 2602 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ 2603 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */ 2604 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2605 } 2606 xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */ 2607 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */ 2608 xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */ 2609 if (device->chipset >= 0xa0) 2610 xf_emit(ctx, 2, 0); /* 00000001 */ 2611 xf_emit(ctx, 1, 0); /* 000003ff */ 2612 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2613 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2614 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2615 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2616 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2617 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2618 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2619 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2620 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ 2621 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2622 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ 2623 if (device->chipset >= 0xa0) 2624 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */ 2625 if (IS_NVA3F(device->chipset)) { 2626 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2627 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2628 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 2629 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 2630 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2631 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 2632 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 2633 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */ 2634 xf_emit(ctx, 1, 0); /* 00000001 */ 2635 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ 2636 } 2637 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2638 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2639 xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */ 2640 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */ 2641 xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */ 2642 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */ 2643 xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */ 2644 xf_emit(ctx, 1, 0); /* 000000ff ROP */ 2645 xf_emit(ctx, 1, 0); /* ffffffff BETA1 */ 2646 xf_emit(ctx, 1, 0); /* ffffffff BETA4 */ 2647 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2648 xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */ 2649 } 2650 2651 static void 2652 nv50_gr_construct_xfer_unk84xx(struct nvkm_grctx *ctx) 2653 { 2654 struct nvkm_device *device = ctx->device; 2655 int magic3; 2656 switch (device->chipset) { 2657 case 0x50: 2658 magic3 = 0x1000; 2659 break; 2660 case 0x86: 2661 case 0x98: 2662 case 0xa8: 2663 case 0xaa: 2664 case 0xac: 2665 case 0xaf: 2666 magic3 = 0x1e00; 2667 break; 2668 default: 2669 magic3 = 0; 2670 } 2671 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2672 xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */ 2673 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2674 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2675 xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */ 2676 if (IS_NVA3F(device->chipset)) 2677 xf_emit(ctx, 0x1f, 0); /* ffffffff */ 2678 else if (device->chipset >= 0xa0) 2679 xf_emit(ctx, 0x0f, 0); /* ffffffff */ 2680 else 2681 xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */ 2682 xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */ 2683 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 2684 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2685 if (device->chipset >= 0xa0) 2686 xf_emit(ctx, 1, 0x03020100); /* ffffffff */ 2687 else 2688 xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */ 2689 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2690 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2691 xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */ 2692 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2693 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2694 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2695 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 2696 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2697 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 2698 if (magic3) 2699 xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */ 2700 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2701 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2702 xf_emit(ctx, 1, 0); /* 111/113 */ 2703 xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */ 2704 xf_emit(ctx, 1, 0); /* 0000001f */ 2705 xf_emit(ctx, 1, 0); /* ffffffff */ 2706 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2707 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ 2708 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ 2709 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2710 xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */ 2711 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2712 if (magic3) 2713 xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */ 2714 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ 2715 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2716 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2717 xf_emit(ctx, 1, 0); /* 111/113 */ 2718 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2719 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2720 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2721 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2722 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2723 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */ 2724 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ 2725 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2726 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2727 xf_emit(ctx, 1, 0); /* 111/113 */ 2728 if (device->chipset == 0x94 || device->chipset == 0x96) 2729 xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ 2730 else if (device->chipset < 0xa0) 2731 xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ 2732 else if (!IS_NVA3F(device->chipset)) 2733 xf_emit(ctx, 0x210, 0); /* ffffffff */ 2734 else 2735 xf_emit(ctx, 0x410, 0); /* ffffffff */ 2736 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 2737 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ 2738 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ 2739 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ 2740 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 2741 } 2742 2743 static void 2744 nv50_gr_construct_xfer_tprop(struct nvkm_grctx *ctx) 2745 { 2746 struct nvkm_device *device = ctx->device; 2747 int magic1, magic2; 2748 if (device->chipset == 0x50) { 2749 magic1 = 0x3ff; 2750 magic2 = 0x00003e60; 2751 } else if (!IS_NVA3F(device->chipset)) { 2752 magic1 = 0x7ff; 2753 magic2 = 0x001ffe67; 2754 } else { 2755 magic1 = 0x7ff; 2756 magic2 = 0x00087e67; 2757 } 2758 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2759 xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */ 2760 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2761 if (IS_NVA3F(device->chipset)) 2762 xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */ 2763 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2764 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2765 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ 2766 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ 2767 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */ 2768 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ 2769 xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */ 2770 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2771 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2772 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2773 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2774 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2775 xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */ 2776 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2777 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 2778 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2779 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ 2780 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2781 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ 2782 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ 2783 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 2784 xf_emit(ctx, 1, 0); /* 7 */ 2785 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2786 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2787 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2788 xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */ 2789 xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */ 2790 xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */ 2791 xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */ 2792 xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */ 2793 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 2794 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 2795 if (IS_NVA3F(device->chipset)) { 2796 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ 2797 xf_emit(ctx, 1, 0); /* 00000003 */ 2798 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */ 2799 } else if (device->chipset >= 0xa0) { 2800 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */ 2801 xf_emit(ctx, 1, 0); /* 00000003 */ 2802 } else { 2803 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 2804 } 2805 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2806 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2807 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2808 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2809 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2810 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2811 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2812 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2813 if (IS_NVA3F(device->chipset)) { 2814 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ 2815 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 2816 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 2817 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 2818 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */ 2819 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */ 2820 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */ 2821 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */ 2822 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 2823 } 2824 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2825 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2826 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2827 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2828 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2829 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2830 xf_emit(ctx, 1, 0); /* ff/3ff */ 2831 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2832 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2833 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 2834 xf_emit(ctx, 1, 0); /* 7 */ 2835 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2836 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2837 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ 2838 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ 2839 xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */ 2840 xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */ 2841 if (IS_NVA3F(device->chipset)) 2842 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2843 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2844 xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */ 2845 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2846 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 2847 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 2848 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 2849 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 2850 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 2851 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 2852 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 2853 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2854 xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */ 2855 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2856 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2857 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2858 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2859 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2860 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2861 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2862 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2863 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2864 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2865 if (IS_NVA3F(device->chipset)) 2866 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2867 if (device->chipset == 0x50) 2868 xf_emit(ctx, 1, 0); /* ff */ 2869 else 2870 xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ 2871 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 2872 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2873 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2874 xf_emit(ctx, 1, 0); /* 00000007 */ 2875 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 2876 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2877 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2878 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2879 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2880 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2881 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2882 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2883 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2884 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2885 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2886 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2887 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2888 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2889 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2890 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ 2891 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ 2892 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ 2893 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ 2894 xf_emit(ctx, 1, 0); /* ff/3ff */ 2895 xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */ 2896 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2897 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2898 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2899 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2900 xf_emit(ctx, 1, 0); /* 00000007 */ 2901 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2902 if (IS_NVA3F(device->chipset)) 2903 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2904 xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */ 2905 xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */ 2906 xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */ 2907 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */ 2908 xf_emit(ctx, 1, 0); /* ff/3ff */ 2909 xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */ 2910 xf_emit(ctx, 1, 0); /* 7 */ 2911 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2912 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2913 xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */ 2914 xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */ 2915 xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ 2916 xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */ 2917 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2918 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2919 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2920 xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */ 2921 xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */ 2922 xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */ 2923 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2924 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2925 xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */ 2926 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2927 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ 2928 xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */ 2929 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ 2930 xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */ 2931 xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */ 2932 xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */ 2933 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ 2934 xf_emit(ctx, 1, 0); /* 0000ffff */ 2935 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */ 2936 xf_emit(ctx, 1, 0); /* ff/3ff */ 2937 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2938 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2939 xf_emit(ctx, 1, 0); /* 00000007 */ 2940 if (IS_NVA3F(device->chipset)) 2941 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2942 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2943 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2944 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 2945 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2946 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ 2947 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2948 xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */ 2949 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2950 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2951 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2952 xf_emit(ctx, 2, 0); /* ffff, ff/3ff */ 2953 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ 2954 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 2955 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ 2956 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 2957 xf_emit(ctx, 1, 0); /* 00000007 */ 2958 xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */ 2959 xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */ 2960 xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */ 2961 xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */ 2962 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 2963 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 2964 xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */ 2965 xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */ 2966 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ 2967 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 2968 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2969 if (IS_NVA3F(device->chipset)) 2970 xf_emit(ctx, 1, 0); /* 00000001 */ 2971 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2972 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ 2973 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ 2974 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ 2975 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ 2976 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ 2977 xf_emit(ctx, 1, 0); /* ff/3ff */ 2978 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 2979 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ 2980 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 2981 xf_emit(ctx, 1, 0); /* 7 */ 2982 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 2983 if (IS_NVA3F(device->chipset)) { 2984 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 2985 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 2986 } 2987 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 2988 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 2989 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 2990 if (device->chipset >= 0xa0) 2991 xf_emit(ctx, 1, 0x0fac6881); /* fffffff */ 2992 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ 2993 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ 2994 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 2995 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ 2996 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 2997 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ 2998 xf_emit(ctx, 1, 0); /* ff/3ff */ 2999 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 3000 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ 3001 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ 3002 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ 3003 xf_emit(ctx, 1, 0); /* 00000007 */ 3004 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ 3005 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ 3006 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ 3007 if (IS_NVA3F(device->chipset)) { 3008 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3009 xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */ 3010 } 3011 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ 3012 if (device->chipset >= 0xa0) { 3013 xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */ 3014 xf_emit(ctx, 1, 0xfac6881); /* fffffff */ 3015 xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */ 3016 xf_emit(ctx, 1, 4); /* 7 */ 3017 xf_emit(ctx, 1, 0); /* 1 */ 3018 xf_emit(ctx, 2, 1); /* 1 */ 3019 xf_emit(ctx, 2, 0); /* 7, f */ 3020 xf_emit(ctx, 1, 1); /* 1 */ 3021 xf_emit(ctx, 1, 0); /* 7/f */ 3022 if (IS_NVA3F(device->chipset)) 3023 xf_emit(ctx, 0x9, 0); /* 1 */ 3024 else 3025 xf_emit(ctx, 0x8, 0); /* 1 */ 3026 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 3027 xf_emit(ctx, 8, 1); /* 1 */ 3028 xf_emit(ctx, 1, 0x11); /* 7f */ 3029 xf_emit(ctx, 7, 0); /* 7f */ 3030 xf_emit(ctx, 1, 0xfac6881); /* fffffff */ 3031 xf_emit(ctx, 1, 0xf); /* f */ 3032 xf_emit(ctx, 7, 0); /* f */ 3033 xf_emit(ctx, 1, 0x11); /* 7f */ 3034 xf_emit(ctx, 1, 1); /* 1 */ 3035 xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */ 3036 if (IS_NVA3F(device->chipset)) { 3037 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 3038 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3039 } 3040 } 3041 } 3042 3043 static void 3044 nv50_gr_construct_xfer_tex(struct nvkm_grctx *ctx) 3045 { 3046 struct nvkm_device *device = ctx->device; 3047 xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */ 3048 if (device->chipset != 0x50) 3049 xf_emit(ctx, 1, 0); /* 3 */ 3050 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */ 3051 xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */ 3052 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */ 3053 xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */ 3054 if (device->chipset == 0x50) 3055 xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */ 3056 else 3057 xf_emit(ctx, 2, 0); /* 3ff, 1 */ 3058 xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */ 3059 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */ 3060 xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */ 3061 xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */ 3062 xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */ 3063 xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */ 3064 xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */ 3065 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */ 3066 if (device->chipset == 0x50) { 3067 xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */ 3068 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ 3069 xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */ 3070 xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */ 3071 xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */ 3072 } else if (!IS_NVAAF(device->chipset)) { 3073 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ 3074 xf_emit(ctx, 1, 0); /* 00000003 */ 3075 xf_emit(ctx, 1, 0); /* 000003ff */ 3076 xf_emit(ctx, 1, 0); /* 00000003 */ 3077 xf_emit(ctx, 1, 0); /* 000003ff */ 3078 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */ 3079 xf_emit(ctx, 1, 0); /* 00000003 */ 3080 xf_emit(ctx, 1, 0); /* 000003ff */ 3081 } else { 3082 xf_emit(ctx, 0x6, 0); 3083 } 3084 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ 3085 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */ 3086 xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */ 3087 } 3088 3089 static void 3090 nv50_gr_construct_xfer_unk8cxx(struct nvkm_grctx *ctx) 3091 { 3092 struct nvkm_device *device = ctx->device; 3093 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 3094 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3095 xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */ 3096 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 3097 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ 3098 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ 3099 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ 3100 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ 3101 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 3102 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 3103 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */ 3104 if (IS_NVA3F(device->chipset)) 3105 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3106 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ 3107 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ 3108 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ 3109 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ 3110 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ 3111 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3112 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ 3113 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ 3114 xf_emit(ctx, 1, 0); /* ffff0ff3 */ 3115 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ 3116 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ 3117 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ 3118 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ 3119 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ 3120 xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */ 3121 xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */ 3122 xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */ 3123 xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */ 3124 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ 3125 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ 3126 } 3127 3128 static void 3129 nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx) 3130 { 3131 struct nvkm_device *device = ctx->device; 3132 if (device->chipset < 0xa0) { 3133 nv50_gr_construct_xfer_unk84xx(ctx); 3134 nv50_gr_construct_xfer_tprop(ctx); 3135 nv50_gr_construct_xfer_tex(ctx); 3136 nv50_gr_construct_xfer_unk8cxx(ctx); 3137 } else { 3138 nv50_gr_construct_xfer_tex(ctx); 3139 nv50_gr_construct_xfer_tprop(ctx); 3140 nv50_gr_construct_xfer_unk8cxx(ctx); 3141 nv50_gr_construct_xfer_unk84xx(ctx); 3142 } 3143 } 3144 3145 static void 3146 nv50_gr_construct_xfer_mpc(struct nvkm_grctx *ctx) 3147 { 3148 struct nvkm_device *device = ctx->device; 3149 int i, mpcnt = 2; 3150 switch (device->chipset) { 3151 case 0x98: 3152 case 0xaa: 3153 mpcnt = 1; 3154 break; 3155 case 0x50: 3156 case 0x84: 3157 case 0x86: 3158 case 0x92: 3159 case 0x94: 3160 case 0x96: 3161 case 0xa8: 3162 case 0xac: 3163 mpcnt = 2; 3164 break; 3165 case 0xa0: 3166 case 0xa3: 3167 case 0xa5: 3168 case 0xaf: 3169 mpcnt = 3; 3170 break; 3171 } 3172 for (i = 0; i < mpcnt; i++) { 3173 xf_emit(ctx, 1, 0); /* ff */ 3174 xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */ 3175 xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */ 3176 xf_emit(ctx, 1, 0x04000400); /* ffffffff */ 3177 if (device->chipset >= 0xa0) 3178 xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */ 3179 xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */ 3180 xf_emit(ctx, 1, 0); /* ff/3ff */ 3181 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ 3182 if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) { 3183 xf_emit(ctx, 1, 0xe00); /* 7fff */ 3184 xf_emit(ctx, 1, 0x1e00); /* 7fff */ 3185 } 3186 xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */ 3187 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ 3188 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 3189 if (device->chipset == 0x50) 3190 xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */ 3191 xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */ 3192 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ 3193 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ 3194 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 3195 if (IS_NVAAF(device->chipset)) 3196 xf_emit(ctx, 0xb, 0); /* RO */ 3197 else if (device->chipset >= 0xa0) 3198 xf_emit(ctx, 0xc, 0); /* RO */ 3199 else 3200 xf_emit(ctx, 0xa, 0); /* RO */ 3201 } 3202 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 3203 xf_emit(ctx, 1, 0); /* ff/3ff */ 3204 if (device->chipset >= 0xa0) { 3205 xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */ 3206 } 3207 xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */ 3208 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ 3209 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ 3210 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ 3211 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ 3212 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ 3213 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ 3214 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ 3215 xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ 3216 xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */ 3217 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ 3218 if (IS_NVA3F(device->chipset)) 3219 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ 3220 xf_emit(ctx, 1, 0); /* ff/3ff */ 3221 xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */ 3222 xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */ 3223 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ 3224 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ 3225 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ 3226 xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */ 3227 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ 3228 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ 3229 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ 3230 xf_emit(ctx, 1, 0); /* 00000007 */ 3231 xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */ 3232 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ 3233 if (IS_NVA3F(device->chipset)) 3234 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ 3235 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ 3236 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ 3237 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ 3238 xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */ 3239 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ 3240 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ 3241 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ 3242 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ 3243 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ 3244 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ 3245 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ 3246 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ 3247 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ 3248 if (IS_NVA3F(device->chipset)) { 3249 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ 3250 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ 3251 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ 3252 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ 3253 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ 3254 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ 3255 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ 3256 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ 3257 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ 3258 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ 3259 } 3260 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ 3261 xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ 3262 /* XXX: demagic this part some day */ 3263 if (device->chipset == 0x50) 3264 xf_emit(ctx, 0x3a0, 0); 3265 else if (device->chipset < 0x94) 3266 xf_emit(ctx, 0x3a2, 0); 3267 else if (device->chipset == 0x98 || device->chipset == 0xaa) 3268 xf_emit(ctx, 0x39f, 0); 3269 else 3270 xf_emit(ctx, 0x3a3, 0); 3271 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ 3272 xf_emit(ctx, 1, 0); /* 7 OPERATION */ 3273 xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */ 3274 xf_emit(ctx, 0x2d, 0); 3275 } 3276 3277 static void 3278 nv50_gr_construct_xfer2(struct nvkm_grctx *ctx) 3279 { 3280 struct nvkm_device *device = ctx->device; 3281 int i; 3282 u32 offset; 3283 u32 units = nvkm_rd32(device, 0x1540); 3284 int size = 0; 3285 3286 offset = (ctx->ctxvals_pos+0x3f)&~0x3f; 3287 3288 if (device->chipset < 0xa0) { 3289 for (i = 0; i < 8; i++) { 3290 ctx->ctxvals_pos = offset + i; 3291 /* that little bugger belongs to csched. No idea 3292 * what it's doing here. */ 3293 if (i == 0) 3294 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ 3295 if (units & (1 << i)) 3296 nv50_gr_construct_xfer_mpc(ctx); 3297 if ((ctx->ctxvals_pos-offset)/8 > size) 3298 size = (ctx->ctxvals_pos-offset)/8; 3299 } 3300 } else { 3301 /* Strand 0: TPs 0, 1 */ 3302 ctx->ctxvals_pos = offset; 3303 /* that little bugger belongs to csched. No idea 3304 * what it's doing here. */ 3305 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ 3306 if (units & (1 << 0)) 3307 nv50_gr_construct_xfer_mpc(ctx); 3308 if (units & (1 << 1)) 3309 nv50_gr_construct_xfer_mpc(ctx); 3310 if ((ctx->ctxvals_pos-offset)/8 > size) 3311 size = (ctx->ctxvals_pos-offset)/8; 3312 3313 /* Strand 1: TPs 2, 3 */ 3314 ctx->ctxvals_pos = offset + 1; 3315 if (units & (1 << 2)) 3316 nv50_gr_construct_xfer_mpc(ctx); 3317 if (units & (1 << 3)) 3318 nv50_gr_construct_xfer_mpc(ctx); 3319 if ((ctx->ctxvals_pos-offset)/8 > size) 3320 size = (ctx->ctxvals_pos-offset)/8; 3321 3322 /* Strand 2: TPs 4, 5, 6 */ 3323 ctx->ctxvals_pos = offset + 2; 3324 if (units & (1 << 4)) 3325 nv50_gr_construct_xfer_mpc(ctx); 3326 if (units & (1 << 5)) 3327 nv50_gr_construct_xfer_mpc(ctx); 3328 if (units & (1 << 6)) 3329 nv50_gr_construct_xfer_mpc(ctx); 3330 if ((ctx->ctxvals_pos-offset)/8 > size) 3331 size = (ctx->ctxvals_pos-offset)/8; 3332 3333 /* Strand 3: TPs 7, 8, 9 */ 3334 ctx->ctxvals_pos = offset + 3; 3335 if (units & (1 << 7)) 3336 nv50_gr_construct_xfer_mpc(ctx); 3337 if (units & (1 << 8)) 3338 nv50_gr_construct_xfer_mpc(ctx); 3339 if (units & (1 << 9)) 3340 nv50_gr_construct_xfer_mpc(ctx); 3341 if ((ctx->ctxvals_pos-offset)/8 > size) 3342 size = (ctx->ctxvals_pos-offset)/8; 3343 } 3344 ctx->ctxvals_pos = offset + size * 8; 3345 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; 3346 cp_lsr (ctx, offset); 3347 cp_out (ctx, CP_SET_XFER_POINTER); 3348 cp_lsr (ctx, size); 3349 cp_out (ctx, CP_SEEK_2); 3350 cp_out (ctx, CP_XFER_2); 3351 cp_wait(ctx, XFER, BUSY); 3352 } 3353
Indexes created Tue Sep 23 02:09:52 GMT 2025