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      1 /*	$NetBSD: disp.h,v 1.3 2021/12/18 23:45:32 riastradh Exp $	*/
      2 
      3 /* SPDX-License-Identifier: MIT */
      4 #ifndef __NV04_DISPLAY_H__
      5 #define __NV04_DISPLAY_H__
      6 #include <subdev/bios.h>
      7 #include <subdev/bios/pll.h>
      8 
      9 #include "nouveau_display.h"
     10 
     11 enum nv04_fp_display_regs {
     12 	FP_DISPLAY_END,
     13 	FP_TOTAL,
     14 	FP_CRTC,
     15 	FP_SYNC_START,
     16 	FP_SYNC_END,
     17 	FP_VALID_START,
     18 	FP_VALID_END
     19 };
     20 
     21 struct nv04_crtc_reg {
     22 	unsigned char MiscOutReg;
     23 	uint8_t CRTC[0xa0];
     24 	uint8_t CR58[0x10];
     25 	uint8_t Sequencer[5];
     26 	uint8_t Graphics[9];
     27 	uint8_t Attribute[21];
     28 	unsigned char DAC[768];
     29 
     30 	/* PCRTC regs */
     31 	uint32_t fb_start;
     32 	uint32_t crtc_cfg;
     33 	uint32_t cursor_cfg;
     34 	uint32_t gpio_ext;
     35 	uint32_t crtc_830;
     36 	uint32_t crtc_834;
     37 	uint32_t crtc_850;
     38 	uint32_t crtc_eng_ctrl;
     39 
     40 	/* PRAMDAC regs */
     41 	uint32_t nv10_cursync;
     42 	struct nvkm_pll_vals pllvals;
     43 	uint32_t ramdac_gen_ctrl;
     44 	uint32_t ramdac_630;
     45 	uint32_t ramdac_634;
     46 	uint32_t tv_setup;
     47 	uint32_t tv_vtotal;
     48 	uint32_t tv_vskew;
     49 	uint32_t tv_vsync_delay;
     50 	uint32_t tv_htotal;
     51 	uint32_t tv_hskew;
     52 	uint32_t tv_hsync_delay;
     53 	uint32_t tv_hsync_delay2;
     54 	uint32_t fp_horiz_regs[7];
     55 	uint32_t fp_vert_regs[7];
     56 	uint32_t dither;
     57 	uint32_t fp_control;
     58 	uint32_t dither_regs[6];
     59 	uint32_t fp_debug_0;
     60 	uint32_t fp_debug_1;
     61 	uint32_t fp_debug_2;
     62 	uint32_t fp_margin_color;
     63 	uint32_t ramdac_8c0;
     64 	uint32_t ramdac_a20;
     65 	uint32_t ramdac_a24;
     66 	uint32_t ramdac_a34;
     67 	uint32_t ctv_regs[38];
     68 };
     69 
     70 struct nv04_output_reg {
     71 	uint32_t output;
     72 	int head;
     73 };
     74 
     75 struct nv04_mode_state {
     76 	struct nv04_crtc_reg crtc_reg[2];
     77 	uint32_t pllsel;
     78 	uint32_t sel_clk;
     79 };
     80 
     81 struct nv04_display {
     82 	struct nv04_mode_state mode_reg;
     83 	struct nv04_mode_state saved_reg;
     84 	uint32_t saved_vga_font[4][16384];
     85 	uint32_t dac_users[4];
     86 	struct nouveau_bo *image[2];
     87 	struct nvif_notify flip;
     88 };
     89 
     90 static inline struct nv04_display *
     91 nv04_display(struct drm_device *dev)
     92 {
     93 	return nouveau_display(dev)->priv;
     94 }
     95 
     96 /* nv04_display.c */
     97 int nv04_display_create(struct drm_device *);
     98 
     99 /* nv04_crtc.c */
    100 int nv04_crtc_create(struct drm_device *, int index);
    101 
    102 /* nv04_dac.c */
    103 int nv04_dac_create(struct drm_connector *, struct dcb_output *);
    104 uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
    105 int nv04_dac_output_offset(struct drm_encoder *encoder);
    106 void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
    107 bool nv04_dac_in_use(struct drm_encoder *encoder);
    108 
    109 /* nv04_dfp.c */
    110 int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
    111 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
    112 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
    113 			       int head, bool dl);
    114 void nv04_dfp_disable(struct drm_device *dev, int head);
    115 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
    116 
    117 /* nv04_tv.c */
    118 int nv04_tv_identify(struct drm_device *dev, int i2c_index);
    119 int nv04_tv_create(struct drm_connector *, struct dcb_output *);
    120 
    121 /* nv17_tv.c */
    122 int nv17_tv_create(struct drm_connector *, struct dcb_output *);
    123 
    124 /* overlay.c */
    125 void nouveau_overlay_init(struct drm_device *dev);
    126 
    127 static inline bool
    128 nv_two_heads(struct drm_device *dev)
    129 {
    130 	struct nouveau_drm *drm = nouveau_drm(dev);
    131 	const int impl = dev->pdev->device & 0x0ff0;
    132 
    133 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
    134 	    impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
    135 		return true;
    136 
    137 	return false;
    138 }
    139 
    140 static inline bool
    141 nv_gf4_disp_arch(struct drm_device *dev)
    142 {
    143 	return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
    144 }
    145 
    146 static inline bool
    147 nv_two_reg_pll(struct drm_device *dev)
    148 {
    149 	struct nouveau_drm *drm = nouveau_drm(dev);
    150 	const int impl = dev->pdev->device & 0x0ff0;
    151 
    152 	if (impl == 0x0310 || impl == 0x0340 || drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE)
    153 		return true;
    154 	return false;
    155 }
    156 
    157 static inline bool
    158 nv_match_device(struct drm_device *dev, unsigned device,
    159 		unsigned sub_vendor, unsigned sub_device)
    160 {
    161 	return dev->pdev->device == device &&
    162 		dev->pdev->subsystem_vendor == sub_vendor &&
    163 		dev->pdev->subsystem_device == sub_device;
    164 }
    165 
    166 #include <subdev/bios/init.h>
    167 
    168 static inline void
    169 nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
    170 			    struct dcb_output *outp, int crtc)
    171 {
    172 	nvbios_init(&nvxx_bios(&nouveau_drm(dev)->client.device)->subdev, table,
    173 		init.outp = outp;
    174 		init.head = crtc;
    175 	);
    176 }
    177 
    178 int nv04_flip_complete(struct nvif_notify *);
    179 #endif
    180