1 /* $NetBSD: nouveau_nvkm_subdev_bios_init.c,v 1.3 2021/12/18 23:45:38 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_bios_init.c,v 1.3 2021/12/18 23:45:38 riastradh Exp $"); 28 29 #include <subdev/bios.h> 30 #include <subdev/bios/bit.h> 31 #include <subdev/bios/bmp.h> 32 #include <subdev/bios/conn.h> 33 #include <subdev/bios/dcb.h> 34 #include <subdev/bios/dp.h> 35 #include <subdev/bios/gpio.h> 36 #include <subdev/bios/init.h> 37 #include <subdev/bios/ramcfg.h> 38 39 #include <subdev/devinit.h> 40 #include <subdev/gpio.h> 41 #include <subdev/i2c.h> 42 #include <subdev/vga.h> 43 44 #include <linux/kernel.h> 45 46 #define bioslog(lvl, fmt, args...) do { \ 47 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \ 48 init->offset, init_exec(init) ? \ 49 '0' + (init->nested - 1) : ' ', ##args); \ 50 } while(0) 51 #define cont(fmt, args...) do { \ 52 if (init->subdev->debug >= NV_DBG_TRACE) \ 53 printk(fmt, ##args); \ 54 } while(0) 55 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) 56 #define warn(fmt, args...) bioslog(WARN, fmt, ##args) 57 #define error(fmt, args...) bioslog(ERROR, fmt, ##args) 58 59 /****************************************************************************** 60 * init parser control flow helpers 61 *****************************************************************************/ 62 63 static inline bool 64 init_exec(struct nvbios_init *init) 65 { 66 return (init->execute == 1) || ((init->execute & 5) == 5); 67 } 68 69 static inline void 70 init_exec_set(struct nvbios_init *init, bool exec) 71 { 72 if (exec) init->execute &= 0xfd; 73 else init->execute |= 0x02; 74 } 75 76 static inline void 77 init_exec_inv(struct nvbios_init *init) 78 { 79 init->execute ^= 0x02; 80 } 81 82 static inline void 83 init_exec_force(struct nvbios_init *init, bool exec) 84 { 85 if (exec) init->execute |= 0x04; 86 else init->execute &= 0xfb; 87 } 88 89 /****************************************************************************** 90 * init parser wrappers for normal register/i2c/whatever accessors 91 *****************************************************************************/ 92 93 static inline int 94 init_or(struct nvbios_init *init) 95 { 96 if (init_exec(init)) { 97 if (init->or >= 0) 98 return init->or; 99 error("script needs OR!!\n"); 100 } 101 return 0; 102 } 103 104 static inline int 105 init_link(struct nvbios_init *init) 106 { 107 if (init_exec(init)) { 108 if (init->link) 109 return init->link == 2; 110 error("script needs OR link\n"); 111 } 112 return 0; 113 } 114 115 static inline int 116 init_head(struct nvbios_init *init) 117 { 118 if (init_exec(init)) { 119 if (init->head >= 0) 120 return init->head; 121 error("script needs head\n"); 122 } 123 return 0; 124 } 125 126 static u8 127 init_conn(struct nvbios_init *init) 128 { 129 struct nvkm_bios *bios = init->subdev->device->bios; 130 struct nvbios_connE connE; 131 u8 ver, hdr; 132 u32 conn; 133 134 if (init_exec(init)) { 135 if (init->outp) { 136 conn = init->outp->connector; 137 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE); 138 if (conn) 139 return connE.type; 140 } 141 142 error("script needs connector type\n"); 143 } 144 145 return 0xff; 146 } 147 148 static inline u32 149 init_nvreg(struct nvbios_init *init, u32 reg) 150 { 151 struct nvkm_devinit *devinit = init->subdev->device->devinit; 152 153 /* C51 (at least) sometimes has the lower bits set which the VBIOS 154 * interprets to mean that access needs to go through certain IO 155 * ports instead. The NVIDIA binary driver has been seen to access 156 * these through the NV register address, so lets assume we can 157 * do the same 158 */ 159 reg &= ~0x00000003; 160 161 /* GF8+ display scripts need register addresses mangled a bit to 162 * select a specific CRTC/OR 163 */ 164 if (init->subdev->device->card_type >= NV_50) { 165 if (reg & 0x80000000) { 166 reg += init_head(init) * 0x800; 167 reg &= ~0x80000000; 168 } 169 170 if (reg & 0x40000000) { 171 reg += init_or(init) * 0x800; 172 reg &= ~0x40000000; 173 if (reg & 0x20000000) { 174 reg += init_link(init) * 0x80; 175 reg &= ~0x20000000; 176 } 177 } 178 } 179 180 if (reg & ~0x00fffffc) 181 warn("unknown bits in register 0x%08x\n", reg); 182 183 return nvkm_devinit_mmio(devinit, reg); 184 } 185 186 static u32 187 init_rd32(struct nvbios_init *init, u32 reg) 188 { 189 struct nvkm_device *device = init->subdev->device; 190 reg = init_nvreg(init, reg); 191 if (reg != ~0 && init_exec(init)) 192 return nvkm_rd32(device, reg); 193 return 0x00000000; 194 } 195 196 static void 197 init_wr32(struct nvbios_init *init, u32 reg, u32 val) 198 { 199 struct nvkm_device *device = init->subdev->device; 200 reg = init_nvreg(init, reg); 201 if (reg != ~0 && init_exec(init)) 202 nvkm_wr32(device, reg, val); 203 } 204 205 static u32 206 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) 207 { 208 struct nvkm_device *device = init->subdev->device; 209 reg = init_nvreg(init, reg); 210 if (reg != ~0 && init_exec(init)) { 211 u32 tmp = nvkm_rd32(device, reg); 212 nvkm_wr32(device, reg, (tmp & ~mask) | val); 213 return tmp; 214 } 215 return 0x00000000; 216 } 217 218 static u8 219 init_rdport(struct nvbios_init *init, u16 port) 220 { 221 if (init_exec(init)) 222 return nvkm_rdport(init->subdev->device, init->head, port); 223 return 0x00; 224 } 225 226 static void 227 init_wrport(struct nvbios_init *init, u16 port, u8 value) 228 { 229 if (init_exec(init)) 230 nvkm_wrport(init->subdev->device, init->head, port, value); 231 } 232 233 static u8 234 init_rdvgai(struct nvbios_init *init, u16 port, u8 index) 235 { 236 struct nvkm_subdev *subdev = init->subdev; 237 if (init_exec(init)) { 238 int head = init->head < 0 ? 0 : init->head; 239 return nvkm_rdvgai(subdev->device, head, port, index); 240 } 241 return 0x00; 242 } 243 244 static void 245 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) 246 { 247 struct nvkm_device *device = init->subdev->device; 248 249 /* force head 0 for updates to cr44, it only exists on first head */ 250 if (device->card_type < NV_50) { 251 if (port == 0x03d4 && index == 0x44) 252 init->head = 0; 253 } 254 255 if (init_exec(init)) { 256 int head = init->head < 0 ? 0 : init->head; 257 nvkm_wrvgai(device, head, port, index, value); 258 } 259 260 /* select head 1 if cr44 write selected it */ 261 if (device->card_type < NV_50) { 262 if (port == 0x03d4 && index == 0x44 && value == 3) 263 init->head = 1; 264 } 265 } 266 267 static struct i2c_adapter * 268 init_i2c(struct nvbios_init *init, int index) 269 { 270 struct nvkm_i2c *i2c = init->subdev->device->i2c; 271 struct nvkm_i2c_bus *bus; 272 273 if (index == 0xff) { 274 index = NVKM_I2C_BUS_PRI; 275 if (init->outp && init->outp->i2c_upper_default) 276 index = NVKM_I2C_BUS_SEC; 277 } else 278 if (index == 0x80) { 279 index = NVKM_I2C_BUS_PRI; 280 } else 281 if (index == 0x81) { 282 index = NVKM_I2C_BUS_SEC; 283 } 284 285 bus = nvkm_i2c_bus_find(i2c, index); 286 return bus ? &bus->i2c : NULL; 287 } 288 289 static int 290 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) 291 { 292 struct i2c_adapter *adap = init_i2c(init, index); 293 if (adap && init_exec(init)) 294 return nvkm_rdi2cr(adap, addr, reg); 295 return -ENODEV; 296 } 297 298 static int 299 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) 300 { 301 struct i2c_adapter *adap = init_i2c(init, index); 302 if (adap && init_exec(init)) 303 return nvkm_wri2cr(adap, addr, reg, val); 304 return -ENODEV; 305 } 306 307 static struct nvkm_i2c_aux * 308 init_aux(struct nvbios_init *init) 309 { 310 struct nvkm_i2c *i2c = init->subdev->device->i2c; 311 if (!init->outp) { 312 if (init_exec(init)) 313 error("script needs output for aux\n"); 314 return NULL; 315 } 316 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index); 317 } 318 319 static u8 320 init_rdauxr(struct nvbios_init *init, u32 addr) 321 { 322 struct nvkm_i2c_aux *aux = init_aux(init); 323 u8 data; 324 325 if (aux && init_exec(init)) { 326 int ret = nvkm_rdaux(aux, addr, &data, 1); 327 if (ret == 0) 328 return data; 329 trace("auxch read failed with %d\n", ret); 330 } 331 332 return 0x00; 333 } 334 335 static int 336 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) 337 { 338 struct nvkm_i2c_aux *aux = init_aux(init); 339 if (aux && init_exec(init)) { 340 int ret = nvkm_wraux(aux, addr, &data, 1); 341 if (ret) 342 trace("auxch write failed with %d\n", ret); 343 return ret; 344 } 345 return -ENODEV; 346 } 347 348 static void 349 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) 350 { 351 struct nvkm_devinit *devinit = init->subdev->device->devinit; 352 if (init_exec(init)) { 353 int ret = nvkm_devinit_pll_set(devinit, id, freq); 354 if (ret) 355 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); 356 } 357 } 358 359 /****************************************************************************** 360 * parsing of bios structures that are required to execute init tables 361 *****************************************************************************/ 362 363 static u16 364 init_table(struct nvkm_bios *bios, u16 *len) 365 { 366 struct bit_entry bit_I; 367 368 if (!bit_entry(bios, 'I', &bit_I)) { 369 *len = bit_I.length; 370 return bit_I.offset; 371 } 372 373 if (bmp_version(bios) >= 0x0510) { 374 *len = 14; 375 return bios->bmp_offset + 75; 376 } 377 378 return 0x0000; 379 } 380 381 static u16 382 init_table_(struct nvbios_init *init, u16 offset, const char *name) 383 { 384 struct nvkm_bios *bios = init->subdev->device->bios; 385 u16 len, data = init_table(bios, &len); 386 if (data) { 387 if (len >= offset + 2) { 388 data = nvbios_rd16(bios, data + offset); 389 if (data) 390 return data; 391 392 warn("%s pointer invalid\n", name); 393 return 0x0000; 394 } 395 396 warn("init data too short for %s pointer", name); 397 return 0x0000; 398 } 399 400 warn("init data not found\n"); 401 return 0x0000; 402 } 403 404 #define init_script_table(b) init_table_((b), 0x00, "script table") 405 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") 406 #define init_macro_table(b) init_table_((b), 0x04, "macro table") 407 #define init_condition_table(b) init_table_((b), 0x06, "condition table") 408 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") 409 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") 410 #define init_function_table(b) init_table_((b), 0x0c, "function table") 411 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); 412 413 static u16 414 init_script(struct nvkm_bios *bios, int index) 415 { 416 struct nvbios_init init = { .subdev = &bios->subdev }; 417 u16 bmp_ver = bmp_version(bios), data; 418 419 if (bmp_ver && bmp_ver < 0x0510) { 420 if (index > 1 || bmp_ver < 0x0100) 421 return 0x0000; 422 423 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); 424 return nvbios_rd16(bios, data + (index * 2)); 425 } 426 427 data = init_script_table(&init); 428 if (data) 429 return nvbios_rd16(bios, data + (index * 2)); 430 431 return 0x0000; 432 } 433 434 static u16 435 init_unknown_script(struct nvkm_bios *bios) 436 { 437 u16 len, data = init_table(bios, &len); 438 if (data && len >= 16) 439 return nvbios_rd16(bios, data + 14); 440 return 0x0000; 441 } 442 443 static u8 444 init_ram_restrict_group_count(struct nvbios_init *init) 445 { 446 return nvbios_ramcfg_count(init->subdev->device->bios); 447 } 448 449 static u8 450 init_ram_restrict(struct nvbios_init *init) 451 { 452 /* This appears to be the behaviour of the VBIOS parser, and *is* 453 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to 454 * avoid fucking up the memory controller (somehow) by reading it 455 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. 456 * 457 * Preserving the non-caching behaviour on earlier chipsets just 458 * in case *not* re-reading the strap causes similar breakage. 459 */ 460 if (!init->ramcfg || init->subdev->device->bios->version.major < 0x70) 461 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); 462 return (init->ramcfg & 0x7fffffff); 463 } 464 465 static u8 466 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) 467 { 468 struct nvkm_bios *bios = init->subdev->device->bios; 469 u16 table = init_xlat_table(init); 470 if (table) { 471 u16 data = nvbios_rd16(bios, table + (index * 2)); 472 if (data) 473 return nvbios_rd08(bios, data + offset); 474 warn("xlat table pointer %d invalid\n", index); 475 } 476 return 0x00; 477 } 478 479 /****************************************************************************** 480 * utility functions used by various init opcode handlers 481 *****************************************************************************/ 482 483 static bool 484 init_condition_met(struct nvbios_init *init, u8 cond) 485 { 486 struct nvkm_bios *bios = init->subdev->device->bios; 487 u16 table = init_condition_table(init); 488 if (table) { 489 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0); 490 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4); 491 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8); 492 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", 493 cond, reg, msk, val); 494 return (init_rd32(init, reg) & msk) == val; 495 } 496 return false; 497 } 498 499 static bool 500 init_io_condition_met(struct nvbios_init *init, u8 cond) 501 { 502 struct nvkm_bios *bios = init->subdev->device->bios; 503 u16 table = init_io_condition_table(init); 504 if (table) { 505 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0); 506 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2); 507 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3); 508 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4); 509 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", 510 cond, port, index, mask, value); 511 return (init_rdvgai(init, port, index) & mask) == value; 512 } 513 return false; 514 } 515 516 static bool 517 init_io_flag_condition_met(struct nvbios_init *init, u8 cond) 518 { 519 struct nvkm_bios *bios = init->subdev->device->bios; 520 u16 table = init_io_flag_condition_table(init); 521 if (table) { 522 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0); 523 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2); 524 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3); 525 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4); 526 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5); 527 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7); 528 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8); 529 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; 530 return (nvbios_rd08(bios, data + ioval) & dmask) == value; 531 } 532 return false; 533 } 534 535 static inline u32 536 init_shift(u32 data, u8 shift) 537 { 538 if (shift < 0x80) 539 return data >> shift; 540 return data << (0x100 - shift); 541 } 542 543 static u32 544 init_tmds_reg(struct nvbios_init *init, u8 tmds) 545 { 546 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. 547 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 548 * CR58 for CR57 = 0 to index a table of offsets to the basic 549 * 0x6808b0 address. 550 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 551 * CR58 for CR57 = 0 to index a table of offsets to the basic 552 * 0x6808b0 address, and then flip the offset by 8. 553 */ 554 const int pramdac_offset[13] = { 555 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 556 const u32 pramdac_table[4] = { 557 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 558 559 if (tmds >= 0x80) { 560 if (init->outp) { 561 u32 dacoffset = pramdac_offset[init->outp->or]; 562 if (tmds == 0x81) 563 dacoffset ^= 8; 564 return 0x6808b0 + dacoffset; 565 } 566 567 if (init_exec(init)) 568 error("tmds opcodes need dcb\n"); 569 } else { 570 if (tmds < ARRAY_SIZE(pramdac_table)) 571 return pramdac_table[tmds]; 572 573 error("tmds selector 0x%02x unknown\n", tmds); 574 } 575 576 return 0; 577 } 578 579 /****************************************************************************** 580 * init opcode handlers 581 *****************************************************************************/ 582 583 /** 584 * init_reserved - stub for various unknown/unused single-byte opcodes 585 * 586 */ 587 static void 588 init_reserved(struct nvbios_init *init) 589 { 590 struct nvkm_bios *bios = init->subdev->device->bios; 591 u8 opcode = nvbios_rd08(bios, init->offset); 592 u8 length, i; 593 594 switch (opcode) { 595 case 0xaa: 596 length = 4; 597 break; 598 default: 599 length = 1; 600 break; 601 } 602 603 trace("RESERVED 0x%02x\t", opcode); 604 for (i = 1; i < length; i++) 605 cont(" 0x%02x", nvbios_rd08(bios, init->offset + i)); 606 cont("\n"); 607 init->offset += length; 608 } 609 610 /** 611 * INIT_DONE - opcode 0x71 612 * 613 */ 614 static void 615 init_done(struct nvbios_init *init) 616 { 617 trace("DONE\n"); 618 init->offset = 0x0000; 619 } 620 621 /** 622 * INIT_IO_RESTRICT_PROG - opcode 0x32 623 * 624 */ 625 static void 626 init_io_restrict_prog(struct nvbios_init *init) 627 { 628 struct nvkm_bios *bios = init->subdev->device->bios; 629 u16 port = nvbios_rd16(bios, init->offset + 1); 630 u8 index = nvbios_rd08(bios, init->offset + 3); 631 u8 mask = nvbios_rd08(bios, init->offset + 4); 632 u8 shift = nvbios_rd08(bios, init->offset + 5); 633 u8 count = nvbios_rd08(bios, init->offset + 6); 634 u32 reg = nvbios_rd32(bios, init->offset + 7); 635 u8 conf, i; 636 637 trace("IO_RESTRICT_PROG\tR[0x%06x] = " 638 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", 639 reg, port, index, mask, shift); 640 init->offset += 11; 641 642 conf = (init_rdvgai(init, port, index) & mask) >> shift; 643 for (i = 0; i < count; i++) { 644 u32 data = nvbios_rd32(bios, init->offset); 645 646 if (i == conf) { 647 trace("\t0x%08x *\n", data); 648 init_wr32(init, reg, data); 649 } else { 650 trace("\t0x%08x\n", data); 651 } 652 653 init->offset += 4; 654 } 655 trace("}]\n"); 656 } 657 658 /** 659 * INIT_REPEAT - opcode 0x33 660 * 661 */ 662 static void 663 init_repeat(struct nvbios_init *init) 664 { 665 struct nvkm_bios *bios = init->subdev->device->bios; 666 u8 count = nvbios_rd08(bios, init->offset + 1); 667 u16 repeat = init->repeat; 668 669 trace("REPEAT\t0x%02x\n", count); 670 init->offset += 2; 671 672 init->repeat = init->offset; 673 init->repend = init->offset; 674 while (count--) { 675 init->offset = init->repeat; 676 nvbios_exec(init); 677 if (count) 678 trace("REPEAT\t0x%02x\n", count); 679 } 680 init->offset = init->repend; 681 init->repeat = repeat; 682 } 683 684 /** 685 * INIT_IO_RESTRICT_PLL - opcode 0x34 686 * 687 */ 688 static void 689 init_io_restrict_pll(struct nvbios_init *init) 690 { 691 struct nvkm_bios *bios = init->subdev->device->bios; 692 u16 port = nvbios_rd16(bios, init->offset + 1); 693 u8 index = nvbios_rd08(bios, init->offset + 3); 694 u8 mask = nvbios_rd08(bios, init->offset + 4); 695 u8 shift = nvbios_rd08(bios, init->offset + 5); 696 s8 iofc = nvbios_rd08(bios, init->offset + 6); 697 u8 count = nvbios_rd08(bios, init->offset + 7); 698 u32 reg = nvbios_rd32(bios, init->offset + 8); 699 u8 conf, i; 700 701 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " 702 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", 703 reg, port, index, mask, shift, iofc); 704 init->offset += 12; 705 706 conf = (init_rdvgai(init, port, index) & mask) >> shift; 707 for (i = 0; i < count; i++) { 708 u32 freq = nvbios_rd16(bios, init->offset) * 10; 709 710 if (i == conf) { 711 trace("\t%dkHz *\n", freq); 712 if (iofc > 0 && init_io_flag_condition_met(init, iofc)) 713 freq *= 2; 714 init_prog_pll(init, reg, freq); 715 } else { 716 trace("\t%dkHz\n", freq); 717 } 718 719 init->offset += 2; 720 } 721 trace("}]\n"); 722 } 723 724 /** 725 * INIT_END_REPEAT - opcode 0x36 726 * 727 */ 728 static void 729 init_end_repeat(struct nvbios_init *init) 730 { 731 trace("END_REPEAT\n"); 732 init->offset += 1; 733 734 if (init->repeat) { 735 init->repend = init->offset; 736 init->offset = 0; 737 } 738 } 739 740 /** 741 * INIT_COPY - opcode 0x37 742 * 743 */ 744 static void 745 init_copy(struct nvbios_init *init) 746 { 747 struct nvkm_bios *bios = init->subdev->device->bios; 748 u32 reg = nvbios_rd32(bios, init->offset + 1); 749 u8 shift = nvbios_rd08(bios, init->offset + 5); 750 u8 smask = nvbios_rd08(bios, init->offset + 6); 751 u16 port = nvbios_rd16(bios, init->offset + 7); 752 u8 index = nvbios_rd08(bios, init->offset + 9); 753 u8 mask = nvbios_rd08(bios, init->offset + 10); 754 u8 data; 755 756 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " 757 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", 758 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", 759 (shift & 0x80) ? (0x100 - shift) : shift, smask); 760 init->offset += 11; 761 762 data = init_rdvgai(init, port, index) & mask; 763 data |= init_shift(init_rd32(init, reg), shift) & smask; 764 init_wrvgai(init, port, index, data); 765 } 766 767 /** 768 * INIT_NOT - opcode 0x38 769 * 770 */ 771 static void 772 init_not(struct nvbios_init *init) 773 { 774 trace("NOT\n"); 775 init->offset += 1; 776 init_exec_inv(init); 777 } 778 779 /** 780 * INIT_IO_FLAG_CONDITION - opcode 0x39 781 * 782 */ 783 static void 784 init_io_flag_condition(struct nvbios_init *init) 785 { 786 struct nvkm_bios *bios = init->subdev->device->bios; 787 u8 cond = nvbios_rd08(bios, init->offset + 1); 788 789 trace("IO_FLAG_CONDITION\t0x%02x\n", cond); 790 init->offset += 2; 791 792 if (!init_io_flag_condition_met(init, cond)) 793 init_exec_set(init, false); 794 } 795 796 /** 797 * INIT_GENERIC_CONDITION - opcode 0x3a 798 * 799 */ 800 static void 801 init_generic_condition(struct nvbios_init *init) 802 { 803 struct nvkm_bios *bios = init->subdev->device->bios; 804 struct nvbios_dpout info; 805 u8 cond = nvbios_rd08(bios, init->offset + 1); 806 u8 size = nvbios_rd08(bios, init->offset + 2); 807 u8 ver, hdr, cnt, len; 808 u16 data; 809 810 trace("GENERIC_CONDITION\t0x%02x 0x%02x\n", cond, size); 811 init->offset += 3; 812 813 switch (cond) { 814 case 0: /* CONDITION_ID_INT_DP. */ 815 if (init_conn(init) != DCB_CONNECTOR_eDP) 816 init_exec_set(init, false); 817 break; 818 case 1: /* CONDITION_ID_USE_SPPLL0. */ 819 case 2: /* CONDITION_ID_USE_SPPLL1. */ 820 if ( init->outp && 821 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, 822 (init->outp->or << 0) | 823 (init->outp->sorconf.link << 6), 824 &ver, &hdr, &cnt, &len, &info))) 825 { 826 if (!(info.flags & cond)) 827 init_exec_set(init, false); 828 break; 829 } 830 831 if (init_exec(init)) 832 warn("script needs dp output table data\n"); 833 break; 834 case 5: /* CONDITION_ID_ASSR_SUPPORT. */ 835 if (!(init_rdauxr(init, 0x0d) & 1)) 836 init_exec_set(init, false); 837 break; 838 case 7: /* CONDITION_ID_NO_PANEL_SEQ_DELAYS. */ 839 init_exec_set(init, false); 840 break; 841 default: 842 warn("INIT_GENERIC_CONDITION: unknown 0x%02x\n", cond); 843 init->offset += size; 844 break; 845 } 846 } 847 848 /** 849 * INIT_IO_MASK_OR - opcode 0x3b 850 * 851 */ 852 static void 853 init_io_mask_or(struct nvbios_init *init) 854 { 855 struct nvkm_bios *bios = init->subdev->device->bios; 856 u8 index = nvbios_rd08(bios, init->offset + 1); 857 u8 or = init_or(init); 858 u8 data; 859 860 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); 861 init->offset += 2; 862 863 data = init_rdvgai(init, 0x03d4, index); 864 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); 865 } 866 867 /** 868 * INIT_IO_OR - opcode 0x3c 869 * 870 */ 871 static void 872 init_io_or(struct nvbios_init *init) 873 { 874 struct nvkm_bios *bios = init->subdev->device->bios; 875 u8 index = nvbios_rd08(bios, init->offset + 1); 876 u8 or = init_or(init); 877 u8 data; 878 879 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); 880 init->offset += 2; 881 882 data = init_rdvgai(init, 0x03d4, index); 883 init_wrvgai(init, 0x03d4, index, data | (1 << or)); 884 } 885 886 /** 887 * INIT_ANDN_REG - opcode 0x47 888 * 889 */ 890 static void 891 init_andn_reg(struct nvbios_init *init) 892 { 893 struct nvkm_bios *bios = init->subdev->device->bios; 894 u32 reg = nvbios_rd32(bios, init->offset + 1); 895 u32 mask = nvbios_rd32(bios, init->offset + 5); 896 897 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); 898 init->offset += 9; 899 900 init_mask(init, reg, mask, 0); 901 } 902 903 /** 904 * INIT_OR_REG - opcode 0x48 905 * 906 */ 907 static void 908 init_or_reg(struct nvbios_init *init) 909 { 910 struct nvkm_bios *bios = init->subdev->device->bios; 911 u32 reg = nvbios_rd32(bios, init->offset + 1); 912 u32 mask = nvbios_rd32(bios, init->offset + 5); 913 914 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); 915 init->offset += 9; 916 917 init_mask(init, reg, 0, mask); 918 } 919 920 /** 921 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 922 * 923 */ 924 static void 925 init_idx_addr_latched(struct nvbios_init *init) 926 { 927 struct nvkm_bios *bios = init->subdev->device->bios; 928 u32 creg = nvbios_rd32(bios, init->offset + 1); 929 u32 dreg = nvbios_rd32(bios, init->offset + 5); 930 u32 mask = nvbios_rd32(bios, init->offset + 9); 931 u32 data = nvbios_rd32(bios, init->offset + 13); 932 u8 count = nvbios_rd08(bios, init->offset + 17); 933 934 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); 935 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); 936 init->offset += 18; 937 938 while (count--) { 939 u8 iaddr = nvbios_rd08(bios, init->offset + 0); 940 u8 idata = nvbios_rd08(bios, init->offset + 1); 941 942 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); 943 init->offset += 2; 944 945 init_wr32(init, dreg, idata); 946 init_mask(init, creg, ~mask, data | iaddr); 947 } 948 } 949 950 /** 951 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a 952 * 953 */ 954 static void 955 init_io_restrict_pll2(struct nvbios_init *init) 956 { 957 struct nvkm_bios *bios = init->subdev->device->bios; 958 u16 port = nvbios_rd16(bios, init->offset + 1); 959 u8 index = nvbios_rd08(bios, init->offset + 3); 960 u8 mask = nvbios_rd08(bios, init->offset + 4); 961 u8 shift = nvbios_rd08(bios, init->offset + 5); 962 u8 count = nvbios_rd08(bios, init->offset + 6); 963 u32 reg = nvbios_rd32(bios, init->offset + 7); 964 u8 conf, i; 965 966 trace("IO_RESTRICT_PLL2\t" 967 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", 968 reg, port, index, mask, shift); 969 init->offset += 11; 970 971 conf = (init_rdvgai(init, port, index) & mask) >> shift; 972 for (i = 0; i < count; i++) { 973 u32 freq = nvbios_rd32(bios, init->offset); 974 if (i == conf) { 975 trace("\t%dkHz *\n", freq); 976 init_prog_pll(init, reg, freq); 977 } else { 978 trace("\t%dkHz\n", freq); 979 } 980 init->offset += 4; 981 } 982 trace("}]\n"); 983 } 984 985 /** 986 * INIT_PLL2 - opcode 0x4b 987 * 988 */ 989 static void 990 init_pll2(struct nvbios_init *init) 991 { 992 struct nvkm_bios *bios = init->subdev->device->bios; 993 u32 reg = nvbios_rd32(bios, init->offset + 1); 994 u32 freq = nvbios_rd32(bios, init->offset + 5); 995 996 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 997 init->offset += 9; 998 999 init_prog_pll(init, reg, freq); 1000 } 1001 1002 /** 1003 * INIT_I2C_BYTE - opcode 0x4c 1004 * 1005 */ 1006 static void 1007 init_i2c_byte(struct nvbios_init *init) 1008 { 1009 struct nvkm_bios *bios = init->subdev->device->bios; 1010 u8 index = nvbios_rd08(bios, init->offset + 1); 1011 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1012 u8 count = nvbios_rd08(bios, init->offset + 3); 1013 1014 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1015 init->offset += 4; 1016 1017 while (count--) { 1018 u8 reg = nvbios_rd08(bios, init->offset + 0); 1019 u8 mask = nvbios_rd08(bios, init->offset + 1); 1020 u8 data = nvbios_rd08(bios, init->offset + 2); 1021 int val; 1022 1023 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); 1024 init->offset += 3; 1025 1026 val = init_rdi2cr(init, index, addr, reg); 1027 if (val < 0) 1028 continue; 1029 init_wri2cr(init, index, addr, reg, (val & mask) | data); 1030 } 1031 } 1032 1033 /** 1034 * INIT_ZM_I2C_BYTE - opcode 0x4d 1035 * 1036 */ 1037 static void 1038 init_zm_i2c_byte(struct nvbios_init *init) 1039 { 1040 struct nvkm_bios *bios = init->subdev->device->bios; 1041 u8 index = nvbios_rd08(bios, init->offset + 1); 1042 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1043 u8 count = nvbios_rd08(bios, init->offset + 3); 1044 1045 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1046 init->offset += 4; 1047 1048 while (count--) { 1049 u8 reg = nvbios_rd08(bios, init->offset + 0); 1050 u8 data = nvbios_rd08(bios, init->offset + 1); 1051 1052 trace("\t[0x%02x] = 0x%02x\n", reg, data); 1053 init->offset += 2; 1054 1055 init_wri2cr(init, index, addr, reg, data); 1056 } 1057 } 1058 1059 /** 1060 * INIT_ZM_I2C - opcode 0x4e 1061 * 1062 */ 1063 static void 1064 init_zm_i2c(struct nvbios_init *init) 1065 { 1066 struct nvkm_bios *bios = init->subdev->device->bios; 1067 u8 index = nvbios_rd08(bios, init->offset + 1); 1068 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1069 u8 count = nvbios_rd08(bios, init->offset + 3); 1070 u8 data[256], i; 1071 1072 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); 1073 init->offset += 4; 1074 1075 for (i = 0; i < count; i++) { 1076 data[i] = nvbios_rd08(bios, init->offset); 1077 trace("\t0x%02x\n", data[i]); 1078 init->offset++; 1079 } 1080 1081 if (init_exec(init)) { 1082 struct i2c_adapter *adap = init_i2c(init, index); 1083 struct i2c_msg msg = { 1084 .addr = addr, .flags = 0, .len = count, .buf = data, 1085 }; 1086 int ret; 1087 1088 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1) 1089 warn("i2c wr failed, %d\n", ret); 1090 } 1091 } 1092 1093 /** 1094 * INIT_TMDS - opcode 0x4f 1095 * 1096 */ 1097 static void 1098 init_tmds(struct nvbios_init *init) 1099 { 1100 struct nvkm_bios *bios = init->subdev->device->bios; 1101 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1102 u8 addr = nvbios_rd08(bios, init->offset + 2); 1103 u8 mask = nvbios_rd08(bios, init->offset + 3); 1104 u8 data = nvbios_rd08(bios, init->offset + 4); 1105 u32 reg = init_tmds_reg(init, tmds); 1106 1107 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", 1108 tmds, addr, mask, data); 1109 init->offset += 5; 1110 1111 if (reg == 0) 1112 return; 1113 1114 init_wr32(init, reg + 0, addr | 0x00010000); 1115 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); 1116 init_wr32(init, reg + 0, addr); 1117 } 1118 1119 /** 1120 * INIT_ZM_TMDS_GROUP - opcode 0x50 1121 * 1122 */ 1123 static void 1124 init_zm_tmds_group(struct nvbios_init *init) 1125 { 1126 struct nvkm_bios *bios = init->subdev->device->bios; 1127 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1128 u8 count = nvbios_rd08(bios, init->offset + 2); 1129 u32 reg = init_tmds_reg(init, tmds); 1130 1131 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); 1132 init->offset += 3; 1133 1134 while (count--) { 1135 u8 addr = nvbios_rd08(bios, init->offset + 0); 1136 u8 data = nvbios_rd08(bios, init->offset + 1); 1137 1138 trace("\t[0x%02x] = 0x%02x\n", addr, data); 1139 init->offset += 2; 1140 1141 init_wr32(init, reg + 4, data); 1142 init_wr32(init, reg + 0, addr); 1143 } 1144 } 1145 1146 /** 1147 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 1148 * 1149 */ 1150 static void 1151 init_cr_idx_adr_latch(struct nvbios_init *init) 1152 { 1153 struct nvkm_bios *bios = init->subdev->device->bios; 1154 u8 addr0 = nvbios_rd08(bios, init->offset + 1); 1155 u8 addr1 = nvbios_rd08(bios, init->offset + 2); 1156 u8 base = nvbios_rd08(bios, init->offset + 3); 1157 u8 count = nvbios_rd08(bios, init->offset + 4); 1158 u8 save0; 1159 1160 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); 1161 init->offset += 5; 1162 1163 save0 = init_rdvgai(init, 0x03d4, addr0); 1164 while (count--) { 1165 u8 data = nvbios_rd08(bios, init->offset); 1166 1167 trace("\t\t[0x%02x] = 0x%02x\n", base, data); 1168 init->offset += 1; 1169 1170 init_wrvgai(init, 0x03d4, addr0, base++); 1171 init_wrvgai(init, 0x03d4, addr1, data); 1172 } 1173 init_wrvgai(init, 0x03d4, addr0, save0); 1174 } 1175 1176 /** 1177 * INIT_CR - opcode 0x52 1178 * 1179 */ 1180 static void 1181 init_cr(struct nvbios_init *init) 1182 { 1183 struct nvkm_bios *bios = init->subdev->device->bios; 1184 u8 addr = nvbios_rd08(bios, init->offset + 1); 1185 u8 mask = nvbios_rd08(bios, init->offset + 2); 1186 u8 data = nvbios_rd08(bios, init->offset + 3); 1187 u8 val; 1188 1189 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 1190 init->offset += 4; 1191 1192 val = init_rdvgai(init, 0x03d4, addr) & mask; 1193 init_wrvgai(init, 0x03d4, addr, val | data); 1194 } 1195 1196 /** 1197 * INIT_ZM_CR - opcode 0x53 1198 * 1199 */ 1200 static void 1201 init_zm_cr(struct nvbios_init *init) 1202 { 1203 struct nvkm_bios *bios = init->subdev->device->bios; 1204 u8 addr = nvbios_rd08(bios, init->offset + 1); 1205 u8 data = nvbios_rd08(bios, init->offset + 2); 1206 1207 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); 1208 init->offset += 3; 1209 1210 init_wrvgai(init, 0x03d4, addr, data); 1211 } 1212 1213 /** 1214 * INIT_ZM_CR_GROUP - opcode 0x54 1215 * 1216 */ 1217 static void 1218 init_zm_cr_group(struct nvbios_init *init) 1219 { 1220 struct nvkm_bios *bios = init->subdev->device->bios; 1221 u8 count = nvbios_rd08(bios, init->offset + 1); 1222 1223 trace("ZM_CR_GROUP\n"); 1224 init->offset += 2; 1225 1226 while (count--) { 1227 u8 addr = nvbios_rd08(bios, init->offset + 0); 1228 u8 data = nvbios_rd08(bios, init->offset + 1); 1229 1230 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); 1231 init->offset += 2; 1232 1233 init_wrvgai(init, 0x03d4, addr, data); 1234 } 1235 } 1236 1237 /** 1238 * INIT_CONDITION_TIME - opcode 0x56 1239 * 1240 */ 1241 static void 1242 init_condition_time(struct nvbios_init *init) 1243 { 1244 struct nvkm_bios *bios = init->subdev->device->bios; 1245 u8 cond = nvbios_rd08(bios, init->offset + 1); 1246 u8 retry = nvbios_rd08(bios, init->offset + 2); 1247 u8 wait = min((u16)retry * 50, 100); 1248 1249 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); 1250 init->offset += 3; 1251 1252 if (!init_exec(init)) 1253 return; 1254 1255 while (wait--) { 1256 if (init_condition_met(init, cond)) 1257 return; 1258 mdelay(20); 1259 } 1260 1261 init_exec_set(init, false); 1262 } 1263 1264 /** 1265 * INIT_LTIME - opcode 0x57 1266 * 1267 */ 1268 static void 1269 init_ltime(struct nvbios_init *init) 1270 { 1271 struct nvkm_bios *bios = init->subdev->device->bios; 1272 u16 msec = nvbios_rd16(bios, init->offset + 1); 1273 1274 trace("LTIME\t0x%04x\n", msec); 1275 init->offset += 3; 1276 1277 if (init_exec(init)) 1278 mdelay(msec); 1279 } 1280 1281 /** 1282 * INIT_ZM_REG_SEQUENCE - opcode 0x58 1283 * 1284 */ 1285 static void 1286 init_zm_reg_sequence(struct nvbios_init *init) 1287 { 1288 struct nvkm_bios *bios = init->subdev->device->bios; 1289 u32 base = nvbios_rd32(bios, init->offset + 1); 1290 u8 count = nvbios_rd08(bios, init->offset + 5); 1291 1292 trace("ZM_REG_SEQUENCE\t0x%02x\n", count); 1293 init->offset += 6; 1294 1295 while (count--) { 1296 u32 data = nvbios_rd32(bios, init->offset); 1297 1298 trace("\t\tR[0x%06x] = 0x%08x\n", base, data); 1299 init->offset += 4; 1300 1301 init_wr32(init, base, data); 1302 base += 4; 1303 } 1304 } 1305 1306 /** 1307 * INIT_PLL_INDIRECT - opcode 0x59 1308 * 1309 */ 1310 static void 1311 init_pll_indirect(struct nvbios_init *init) 1312 { 1313 struct nvkm_bios *bios = init->subdev->device->bios; 1314 u32 reg = nvbios_rd32(bios, init->offset + 1); 1315 u16 addr = nvbios_rd16(bios, init->offset + 5); 1316 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000; 1317 1318 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n", 1319 reg, addr, freq); 1320 init->offset += 7; 1321 1322 init_prog_pll(init, reg, freq); 1323 } 1324 1325 /** 1326 * INIT_ZM_REG_INDIRECT - opcode 0x5a 1327 * 1328 */ 1329 static void 1330 init_zm_reg_indirect(struct nvbios_init *init) 1331 { 1332 struct nvkm_bios *bios = init->subdev->device->bios; 1333 u32 reg = nvbios_rd32(bios, init->offset + 1); 1334 u16 addr = nvbios_rd16(bios, init->offset + 5); 1335 u32 data = nvbios_rd32(bios, addr); 1336 1337 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n", 1338 reg, addr, data); 1339 init->offset += 7; 1340 1341 init_wr32(init, addr, data); 1342 } 1343 1344 /** 1345 * INIT_SUB_DIRECT - opcode 0x5b 1346 * 1347 */ 1348 static void 1349 init_sub_direct(struct nvbios_init *init) 1350 { 1351 struct nvkm_bios *bios = init->subdev->device->bios; 1352 u16 addr = nvbios_rd16(bios, init->offset + 1); 1353 u16 save; 1354 1355 trace("SUB_DIRECT\t0x%04x\n", addr); 1356 1357 if (init_exec(init)) { 1358 save = init->offset; 1359 init->offset = addr; 1360 if (nvbios_exec(init)) { 1361 error("error parsing sub-table\n"); 1362 return; 1363 } 1364 init->offset = save; 1365 } 1366 1367 init->offset += 3; 1368 } 1369 1370 /** 1371 * INIT_JUMP - opcode 0x5c 1372 * 1373 */ 1374 static void 1375 init_jump(struct nvbios_init *init) 1376 { 1377 struct nvkm_bios *bios = init->subdev->device->bios; 1378 u16 offset = nvbios_rd16(bios, init->offset + 1); 1379 1380 trace("JUMP\t0x%04x\n", offset); 1381 1382 if (init_exec(init)) 1383 init->offset = offset; 1384 else 1385 init->offset += 3; 1386 } 1387 1388 /** 1389 * INIT_I2C_IF - opcode 0x5e 1390 * 1391 */ 1392 static void 1393 init_i2c_if(struct nvbios_init *init) 1394 { 1395 struct nvkm_bios *bios = init->subdev->device->bios; 1396 u8 index = nvbios_rd08(bios, init->offset + 1); 1397 u8 addr = nvbios_rd08(bios, init->offset + 2); 1398 u8 reg = nvbios_rd08(bios, init->offset + 3); 1399 u8 mask = nvbios_rd08(bios, init->offset + 4); 1400 u8 data = nvbios_rd08(bios, init->offset + 5); 1401 u8 value; 1402 1403 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", 1404 index, addr, reg, mask, data); 1405 init->offset += 6; 1406 init_exec_force(init, true); 1407 1408 value = init_rdi2cr(init, index, addr, reg); 1409 if ((value & mask) != data) 1410 init_exec_set(init, false); 1411 1412 init_exec_force(init, false); 1413 } 1414 1415 /** 1416 * INIT_COPY_NV_REG - opcode 0x5f 1417 * 1418 */ 1419 static void 1420 init_copy_nv_reg(struct nvbios_init *init) 1421 { 1422 struct nvkm_bios *bios = init->subdev->device->bios; 1423 u32 sreg = nvbios_rd32(bios, init->offset + 1); 1424 u8 shift = nvbios_rd08(bios, init->offset + 5); 1425 u32 smask = nvbios_rd32(bios, init->offset + 6); 1426 u32 sxor = nvbios_rd32(bios, init->offset + 10); 1427 u32 dreg = nvbios_rd32(bios, init->offset + 14); 1428 u32 dmask = nvbios_rd32(bios, init->offset + 18); 1429 u32 data; 1430 1431 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " 1432 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", 1433 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", 1434 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); 1435 init->offset += 22; 1436 1437 data = init_shift(init_rd32(init, sreg), shift); 1438 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); 1439 } 1440 1441 /** 1442 * INIT_ZM_INDEX_IO - opcode 0x62 1443 * 1444 */ 1445 static void 1446 init_zm_index_io(struct nvbios_init *init) 1447 { 1448 struct nvkm_bios *bios = init->subdev->device->bios; 1449 u16 port = nvbios_rd16(bios, init->offset + 1); 1450 u8 index = nvbios_rd08(bios, init->offset + 3); 1451 u8 data = nvbios_rd08(bios, init->offset + 4); 1452 1453 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); 1454 init->offset += 5; 1455 1456 init_wrvgai(init, port, index, data); 1457 } 1458 1459 /** 1460 * INIT_COMPUTE_MEM - opcode 0x63 1461 * 1462 */ 1463 static void 1464 init_compute_mem(struct nvbios_init *init) 1465 { 1466 struct nvkm_devinit *devinit = init->subdev->device->devinit; 1467 1468 trace("COMPUTE_MEM\n"); 1469 init->offset += 1; 1470 1471 init_exec_force(init, true); 1472 if (init_exec(init)) 1473 nvkm_devinit_meminit(devinit); 1474 init_exec_force(init, false); 1475 } 1476 1477 /** 1478 * INIT_RESET - opcode 0x65 1479 * 1480 */ 1481 static void 1482 init_reset(struct nvbios_init *init) 1483 { 1484 struct nvkm_bios *bios = init->subdev->device->bios; 1485 u32 reg = nvbios_rd32(bios, init->offset + 1); 1486 u32 data1 = nvbios_rd32(bios, init->offset + 5); 1487 u32 data2 = nvbios_rd32(bios, init->offset + 9); 1488 u32 savepci19; 1489 1490 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); 1491 init->offset += 13; 1492 init_exec_force(init, true); 1493 1494 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); 1495 init_wr32(init, reg, data1); 1496 udelay(10); 1497 init_wr32(init, reg, data2); 1498 init_wr32(init, 0x00184c, savepci19); 1499 init_mask(init, 0x001850, 0x00000001, 0x00000000); 1500 1501 init_exec_force(init, false); 1502 } 1503 1504 /** 1505 * INIT_CONFIGURE_MEM - opcode 0x66 1506 * 1507 */ 1508 static u16 1509 init_configure_mem_clk(struct nvbios_init *init) 1510 { 1511 u16 mdata = bmp_mem_init_table(init->subdev->device->bios); 1512 if (mdata) 1513 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; 1514 return mdata; 1515 } 1516 1517 static void 1518 init_configure_mem(struct nvbios_init *init) 1519 { 1520 struct nvkm_bios *bios = init->subdev->device->bios; 1521 u16 mdata, sdata; 1522 u32 addr, data; 1523 1524 trace("CONFIGURE_MEM\n"); 1525 init->offset += 1; 1526 1527 if (bios->version.major > 2) { 1528 init_done(init); 1529 return; 1530 } 1531 init_exec_force(init, true); 1532 1533 mdata = init_configure_mem_clk(init); 1534 sdata = bmp_sdr_seq_table(bios); 1535 if (nvbios_rd08(bios, mdata) & 0x01) 1536 sdata = bmp_ddr_seq_table(bios); 1537 mdata += 6; /* skip to data */ 1538 1539 data = init_rdvgai(init, 0x03c4, 0x01); 1540 init_wrvgai(init, 0x03c4, 0x01, data | 0x20); 1541 1542 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) { 1543 switch (addr) { 1544 case 0x10021c: /* CKE_NORMAL */ 1545 case 0x1002d0: /* CMD_REFRESH */ 1546 case 0x1002d4: /* CMD_PRECHARGE */ 1547 data = 0x00000001; 1548 break; 1549 default: 1550 data = nvbios_rd32(bios, mdata); 1551 mdata += 4; 1552 if (data == 0xffffffff) 1553 continue; 1554 break; 1555 } 1556 1557 init_wr32(init, addr, data); 1558 } 1559 1560 init_exec_force(init, false); 1561 } 1562 1563 /** 1564 * INIT_CONFIGURE_CLK - opcode 0x67 1565 * 1566 */ 1567 static void 1568 init_configure_clk(struct nvbios_init *init) 1569 { 1570 struct nvkm_bios *bios = init->subdev->device->bios; 1571 u16 mdata, clock; 1572 1573 trace("CONFIGURE_CLK\n"); 1574 init->offset += 1; 1575 1576 if (bios->version.major > 2) { 1577 init_done(init); 1578 return; 1579 } 1580 init_exec_force(init, true); 1581 1582 mdata = init_configure_mem_clk(init); 1583 1584 /* NVPLL */ 1585 clock = nvbios_rd16(bios, mdata + 4) * 10; 1586 init_prog_pll(init, 0x680500, clock); 1587 1588 /* MPLL */ 1589 clock = nvbios_rd16(bios, mdata + 2) * 10; 1590 if (nvbios_rd08(bios, mdata) & 0x01) 1591 clock *= 2; 1592 init_prog_pll(init, 0x680504, clock); 1593 1594 init_exec_force(init, false); 1595 } 1596 1597 /** 1598 * INIT_CONFIGURE_PREINIT - opcode 0x68 1599 * 1600 */ 1601 static void 1602 init_configure_preinit(struct nvbios_init *init) 1603 { 1604 struct nvkm_bios *bios = init->subdev->device->bios; 1605 u32 strap; 1606 1607 trace("CONFIGURE_PREINIT\n"); 1608 init->offset += 1; 1609 1610 if (bios->version.major > 2) { 1611 init_done(init); 1612 return; 1613 } 1614 init_exec_force(init, true); 1615 1616 strap = init_rd32(init, 0x101000); 1617 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); 1618 init_wrvgai(init, 0x03d4, 0x3c, strap); 1619 1620 init_exec_force(init, false); 1621 } 1622 1623 /** 1624 * INIT_IO - opcode 0x69 1625 * 1626 */ 1627 static void 1628 init_io(struct nvbios_init *init) 1629 { 1630 struct nvkm_bios *bios = init->subdev->device->bios; 1631 u16 port = nvbios_rd16(bios, init->offset + 1); 1632 u8 mask = nvbios_rd16(bios, init->offset + 3); 1633 u8 data = nvbios_rd16(bios, init->offset + 4); 1634 u8 value; 1635 1636 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); 1637 init->offset += 5; 1638 1639 /* ummm.. yes.. should really figure out wtf this is and why it's 1640 * needed some day.. it's almost certainly wrong, but, it also 1641 * somehow makes things work... 1642 */ 1643 if (bios->subdev.device->card_type >= NV_50 && 1644 port == 0x03c3 && data == 0x01) { 1645 init_mask(init, 0x614100, 0xf0800000, 0x00800000); 1646 init_mask(init, 0x00e18c, 0x00020000, 0x00020000); 1647 init_mask(init, 0x614900, 0xf0800000, 0x00800000); 1648 init_mask(init, 0x000200, 0x40000000, 0x00000000); 1649 mdelay(10); 1650 init_mask(init, 0x00e18c, 0x00020000, 0x00000000); 1651 init_mask(init, 0x000200, 0x40000000, 0x40000000); 1652 init_wr32(init, 0x614100, 0x00800018); 1653 init_wr32(init, 0x614900, 0x00800018); 1654 mdelay(10); 1655 init_wr32(init, 0x614100, 0x10000018); 1656 init_wr32(init, 0x614900, 0x10000018); 1657 } 1658 1659 value = init_rdport(init, port) & mask; 1660 init_wrport(init, port, data | value); 1661 } 1662 1663 /** 1664 * INIT_SUB - opcode 0x6b 1665 * 1666 */ 1667 static void 1668 init_sub(struct nvbios_init *init) 1669 { 1670 struct nvkm_bios *bios = init->subdev->device->bios; 1671 u8 index = nvbios_rd08(bios, init->offset + 1); 1672 u16 addr, save; 1673 1674 trace("SUB\t0x%02x\n", index); 1675 1676 addr = init_script(bios, index); 1677 if (addr && init_exec(init)) { 1678 save = init->offset; 1679 init->offset = addr; 1680 if (nvbios_exec(init)) { 1681 error("error parsing sub-table\n"); 1682 return; 1683 } 1684 init->offset = save; 1685 } 1686 1687 init->offset += 2; 1688 } 1689 1690 /** 1691 * INIT_RAM_CONDITION - opcode 0x6d 1692 * 1693 */ 1694 static void 1695 init_ram_condition(struct nvbios_init *init) 1696 { 1697 struct nvkm_bios *bios = init->subdev->device->bios; 1698 u8 mask = nvbios_rd08(bios, init->offset + 1); 1699 u8 value = nvbios_rd08(bios, init->offset + 2); 1700 1701 trace("RAM_CONDITION\t" 1702 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); 1703 init->offset += 3; 1704 1705 if ((init_rd32(init, 0x100000) & mask) != value) 1706 init_exec_set(init, false); 1707 } 1708 1709 /** 1710 * INIT_NV_REG - opcode 0x6e 1711 * 1712 */ 1713 static void 1714 init_nv_reg(struct nvbios_init *init) 1715 { 1716 struct nvkm_bios *bios = init->subdev->device->bios; 1717 u32 reg = nvbios_rd32(bios, init->offset + 1); 1718 u32 mask = nvbios_rd32(bios, init->offset + 5); 1719 u32 data = nvbios_rd32(bios, init->offset + 9); 1720 1721 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); 1722 init->offset += 13; 1723 1724 init_mask(init, reg, ~mask, data); 1725 } 1726 1727 /** 1728 * INIT_MACRO - opcode 0x6f 1729 * 1730 */ 1731 static void 1732 init_macro(struct nvbios_init *init) 1733 { 1734 struct nvkm_bios *bios = init->subdev->device->bios; 1735 u8 macro = nvbios_rd08(bios, init->offset + 1); 1736 u16 table; 1737 1738 trace("MACRO\t0x%02x\n", macro); 1739 1740 table = init_macro_table(init); 1741 if (table) { 1742 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0); 1743 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4); 1744 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); 1745 init_wr32(init, addr, data); 1746 } 1747 1748 init->offset += 2; 1749 } 1750 1751 /** 1752 * INIT_RESUME - opcode 0x72 1753 * 1754 */ 1755 static void 1756 init_resume(struct nvbios_init *init) 1757 { 1758 trace("RESUME\n"); 1759 init->offset += 1; 1760 init_exec_set(init, true); 1761 } 1762 1763 /** 1764 * INIT_STRAP_CONDITION - opcode 0x73 1765 * 1766 */ 1767 static void 1768 init_strap_condition(struct nvbios_init *init) 1769 { 1770 struct nvkm_bios *bios = init->subdev->device->bios; 1771 u32 mask = nvbios_rd32(bios, init->offset + 1); 1772 u32 value = nvbios_rd32(bios, init->offset + 5); 1773 1774 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); 1775 init->offset += 9; 1776 1777 if ((init_rd32(init, 0x101000) & mask) != value) 1778 init_exec_set(init, false); 1779 } 1780 1781 /** 1782 * INIT_TIME - opcode 0x74 1783 * 1784 */ 1785 static void 1786 init_time(struct nvbios_init *init) 1787 { 1788 struct nvkm_bios *bios = init->subdev->device->bios; 1789 u16 usec = nvbios_rd16(bios, init->offset + 1); 1790 1791 trace("TIME\t0x%04x\n", usec); 1792 init->offset += 3; 1793 1794 if (init_exec(init)) { 1795 if (usec < 1000) 1796 udelay(usec); 1797 else 1798 mdelay((usec + 900) / 1000); 1799 } 1800 } 1801 1802 /** 1803 * INIT_CONDITION - opcode 0x75 1804 * 1805 */ 1806 static void 1807 init_condition(struct nvbios_init *init) 1808 { 1809 struct nvkm_bios *bios = init->subdev->device->bios; 1810 u8 cond = nvbios_rd08(bios, init->offset + 1); 1811 1812 trace("CONDITION\t0x%02x\n", cond); 1813 init->offset += 2; 1814 1815 if (!init_condition_met(init, cond)) 1816 init_exec_set(init, false); 1817 } 1818 1819 /** 1820 * INIT_IO_CONDITION - opcode 0x76 1821 * 1822 */ 1823 static void 1824 init_io_condition(struct nvbios_init *init) 1825 { 1826 struct nvkm_bios *bios = init->subdev->device->bios; 1827 u8 cond = nvbios_rd08(bios, init->offset + 1); 1828 1829 trace("IO_CONDITION\t0x%02x\n", cond); 1830 init->offset += 2; 1831 1832 if (!init_io_condition_met(init, cond)) 1833 init_exec_set(init, false); 1834 } 1835 1836 /** 1837 * INIT_ZM_REG16 - opcode 0x77 1838 * 1839 */ 1840 static void 1841 init_zm_reg16(struct nvbios_init *init) 1842 { 1843 struct nvkm_bios *bios = init->subdev->device->bios; 1844 u32 addr = nvbios_rd32(bios, init->offset + 1); 1845 u16 data = nvbios_rd16(bios, init->offset + 5); 1846 1847 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data); 1848 init->offset += 7; 1849 1850 init_wr32(init, addr, data); 1851 } 1852 1853 /** 1854 * INIT_INDEX_IO - opcode 0x78 1855 * 1856 */ 1857 static void 1858 init_index_io(struct nvbios_init *init) 1859 { 1860 struct nvkm_bios *bios = init->subdev->device->bios; 1861 u16 port = nvbios_rd16(bios, init->offset + 1); 1862 u8 index = nvbios_rd16(bios, init->offset + 3); 1863 u8 mask = nvbios_rd08(bios, init->offset + 4); 1864 u8 data = nvbios_rd08(bios, init->offset + 5); 1865 u8 value; 1866 1867 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", 1868 port, index, mask, data); 1869 init->offset += 6; 1870 1871 value = init_rdvgai(init, port, index) & mask; 1872 init_wrvgai(init, port, index, data | value); 1873 } 1874 1875 /** 1876 * INIT_PLL - opcode 0x79 1877 * 1878 */ 1879 static void 1880 init_pll(struct nvbios_init *init) 1881 { 1882 struct nvkm_bios *bios = init->subdev->device->bios; 1883 u32 reg = nvbios_rd32(bios, init->offset + 1); 1884 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10; 1885 1886 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 1887 init->offset += 7; 1888 1889 init_prog_pll(init, reg, freq); 1890 } 1891 1892 /** 1893 * INIT_ZM_REG - opcode 0x7a 1894 * 1895 */ 1896 static void 1897 init_zm_reg(struct nvbios_init *init) 1898 { 1899 struct nvkm_bios *bios = init->subdev->device->bios; 1900 u32 addr = nvbios_rd32(bios, init->offset + 1); 1901 u32 data = nvbios_rd32(bios, init->offset + 5); 1902 1903 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); 1904 init->offset += 9; 1905 1906 if (addr == 0x000200) 1907 data |= 0x00000001; 1908 1909 init_wr32(init, addr, data); 1910 } 1911 1912 /** 1913 * INIT_RAM_RESTRICT_PLL - opcde 0x87 1914 * 1915 */ 1916 static void 1917 init_ram_restrict_pll(struct nvbios_init *init) 1918 { 1919 struct nvkm_bios *bios = init->subdev->device->bios; 1920 u8 type = nvbios_rd08(bios, init->offset + 1); 1921 u8 count = init_ram_restrict_group_count(init); 1922 u8 strap = init_ram_restrict(init); 1923 u8 cconf; 1924 1925 trace("RAM_RESTRICT_PLL\t0x%02x\n", type); 1926 init->offset += 2; 1927 1928 for (cconf = 0; cconf < count; cconf++) { 1929 u32 freq = nvbios_rd32(bios, init->offset); 1930 1931 if (cconf == strap) { 1932 trace("%dkHz *\n", freq); 1933 init_prog_pll(init, type, freq); 1934 } else { 1935 trace("%dkHz\n", freq); 1936 } 1937 1938 init->offset += 4; 1939 } 1940 } 1941 1942 /** 1943 * INIT_RESET_BEGUN - opcode 0x8c 1944 * 1945 */ 1946 static void 1947 init_reset_begun(struct nvbios_init *init) 1948 { 1949 trace("RESET_BEGUN\n"); 1950 init->offset += 1; 1951 } 1952 1953 /** 1954 * INIT_RESET_END - opcode 0x8d 1955 * 1956 */ 1957 static void 1958 init_reset_end(struct nvbios_init *init) 1959 { 1960 trace("RESET_END\n"); 1961 init->offset += 1; 1962 } 1963 1964 /** 1965 * INIT_GPIO - opcode 0x8e 1966 * 1967 */ 1968 static void 1969 init_gpio(struct nvbios_init *init) 1970 { 1971 struct nvkm_gpio *gpio = init->subdev->device->gpio; 1972 1973 trace("GPIO\n"); 1974 init->offset += 1; 1975 1976 if (init_exec(init)) 1977 nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED); 1978 } 1979 1980 /** 1981 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f 1982 * 1983 */ 1984 static void 1985 init_ram_restrict_zm_reg_group(struct nvbios_init *init) 1986 { 1987 struct nvkm_bios *bios = init->subdev->device->bios; 1988 u32 addr = nvbios_rd32(bios, init->offset + 1); 1989 u8 incr = nvbios_rd08(bios, init->offset + 5); 1990 u8 num = nvbios_rd08(bios, init->offset + 6); 1991 u8 count = init_ram_restrict_group_count(init); 1992 u8 index = init_ram_restrict(init); 1993 u8 i, j; 1994 1995 trace("RAM_RESTRICT_ZM_REG_GROUP\t" 1996 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); 1997 init->offset += 7; 1998 1999 for (i = 0; i < num; i++) { 2000 trace("\tR[0x%06x] = {\n", addr); 2001 for (j = 0; j < count; j++) { 2002 u32 data = nvbios_rd32(bios, init->offset); 2003 2004 if (j == index) { 2005 trace("\t\t0x%08x *\n", data); 2006 init_wr32(init, addr, data); 2007 } else { 2008 trace("\t\t0x%08x\n", data); 2009 } 2010 2011 init->offset += 4; 2012 } 2013 trace("\t}\n"); 2014 addr += incr; 2015 } 2016 } 2017 2018 /** 2019 * INIT_COPY_ZM_REG - opcode 0x90 2020 * 2021 */ 2022 static void 2023 init_copy_zm_reg(struct nvbios_init *init) 2024 { 2025 struct nvkm_bios *bios = init->subdev->device->bios; 2026 u32 sreg = nvbios_rd32(bios, init->offset + 1); 2027 u32 dreg = nvbios_rd32(bios, init->offset + 5); 2028 2029 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); 2030 init->offset += 9; 2031 2032 init_wr32(init, dreg, init_rd32(init, sreg)); 2033 } 2034 2035 /** 2036 * INIT_ZM_REG_GROUP - opcode 0x91 2037 * 2038 */ 2039 static void 2040 init_zm_reg_group(struct nvbios_init *init) 2041 { 2042 struct nvkm_bios *bios = init->subdev->device->bios; 2043 u32 addr = nvbios_rd32(bios, init->offset + 1); 2044 u8 count = nvbios_rd08(bios, init->offset + 5); 2045 2046 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); 2047 init->offset += 6; 2048 2049 while (count--) { 2050 u32 data = nvbios_rd32(bios, init->offset); 2051 trace("\t0x%08x\n", data); 2052 init_wr32(init, addr, data); 2053 init->offset += 4; 2054 } 2055 } 2056 2057 /** 2058 * INIT_XLAT - opcode 0x96 2059 * 2060 */ 2061 static void 2062 init_xlat(struct nvbios_init *init) 2063 { 2064 struct nvkm_bios *bios = init->subdev->device->bios; 2065 u32 saddr = nvbios_rd32(bios, init->offset + 1); 2066 u8 sshift = nvbios_rd08(bios, init->offset + 5); 2067 u8 smask = nvbios_rd08(bios, init->offset + 6); 2068 u8 index = nvbios_rd08(bios, init->offset + 7); 2069 u32 daddr = nvbios_rd32(bios, init->offset + 8); 2070 u32 dmask = nvbios_rd32(bios, init->offset + 12); 2071 u8 shift = nvbios_rd08(bios, init->offset + 16); 2072 u32 data; 2073 2074 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " 2075 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", 2076 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", 2077 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); 2078 init->offset += 17; 2079 2080 data = init_shift(init_rd32(init, saddr), sshift) & smask; 2081 data = init_xlat_(init, index, data) << shift; 2082 init_mask(init, daddr, ~dmask, data); 2083 } 2084 2085 /** 2086 * INIT_ZM_MASK_ADD - opcode 0x97 2087 * 2088 */ 2089 static void 2090 init_zm_mask_add(struct nvbios_init *init) 2091 { 2092 struct nvkm_bios *bios = init->subdev->device->bios; 2093 u32 addr = nvbios_rd32(bios, init->offset + 1); 2094 u32 mask = nvbios_rd32(bios, init->offset + 5); 2095 u32 add = nvbios_rd32(bios, init->offset + 9); 2096 u32 data; 2097 2098 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); 2099 init->offset += 13; 2100 2101 data = init_rd32(init, addr); 2102 data = (data & mask) | ((data + add) & ~mask); 2103 init_wr32(init, addr, data); 2104 } 2105 2106 /** 2107 * INIT_AUXCH - opcode 0x98 2108 * 2109 */ 2110 static void 2111 init_auxch(struct nvbios_init *init) 2112 { 2113 struct nvkm_bios *bios = init->subdev->device->bios; 2114 u32 addr = nvbios_rd32(bios, init->offset + 1); 2115 u8 count = nvbios_rd08(bios, init->offset + 5); 2116 2117 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2118 init->offset += 6; 2119 2120 while (count--) { 2121 u8 mask = nvbios_rd08(bios, init->offset + 0); 2122 u8 data = nvbios_rd08(bios, init->offset + 1); 2123 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 2124 mask = init_rdauxr(init, addr) & mask; 2125 init_wrauxr(init, addr, mask | data); 2126 init->offset += 2; 2127 } 2128 } 2129 2130 /** 2131 * INIT_AUXCH - opcode 0x99 2132 * 2133 */ 2134 static void 2135 init_zm_auxch(struct nvbios_init *init) 2136 { 2137 struct nvkm_bios *bios = init->subdev->device->bios; 2138 u32 addr = nvbios_rd32(bios, init->offset + 1); 2139 u8 count = nvbios_rd08(bios, init->offset + 5); 2140 2141 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2142 init->offset += 6; 2143 2144 while (count--) { 2145 u8 data = nvbios_rd08(bios, init->offset + 0); 2146 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); 2147 init_wrauxr(init, addr, data); 2148 init->offset += 1; 2149 } 2150 } 2151 2152 /** 2153 * INIT_I2C_LONG_IF - opcode 0x9a 2154 * 2155 */ 2156 static void 2157 init_i2c_long_if(struct nvbios_init *init) 2158 { 2159 struct nvkm_bios *bios = init->subdev->device->bios; 2160 u8 index = nvbios_rd08(bios, init->offset + 1); 2161 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 2162 u8 reglo = nvbios_rd08(bios, init->offset + 3); 2163 u8 reghi = nvbios_rd08(bios, init->offset + 4); 2164 u8 mask = nvbios_rd08(bios, init->offset + 5); 2165 u8 data = nvbios_rd08(bios, init->offset + 6); 2166 struct i2c_adapter *adap; 2167 2168 trace("I2C_LONG_IF\t" 2169 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", 2170 index, addr, reglo, reghi, mask, data); 2171 init->offset += 7; 2172 2173 adap = init_i2c(init, index); 2174 if (adap) { 2175 u8 i[2] = { reghi, reglo }; 2176 u8 o[1] = {}; 2177 struct i2c_msg msg[] = { 2178 { .addr = addr, .flags = 0, .len = 2, .buf = i }, 2179 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } 2180 }; 2181 int ret; 2182 2183 ret = i2c_transfer(adap, msg, 2); 2184 if (ret == 2 && ((o[0] & mask) == data)) 2185 return; 2186 } 2187 2188 init_exec_set(init, false); 2189 } 2190 2191 /** 2192 * INIT_GPIO_NE - opcode 0xa9 2193 * 2194 */ 2195 static void 2196 init_gpio_ne(struct nvbios_init *init) 2197 { 2198 struct nvkm_bios *bios = init->subdev->device->bios; 2199 struct nvkm_gpio *gpio = bios->subdev.device->gpio; 2200 struct dcb_gpio_func func; 2201 u8 count = nvbios_rd08(bios, init->offset + 1); 2202 u8 idx = 0, ver, len; 2203 u16 data, i; 2204 2205 trace("GPIO_NE\t"); 2206 init->offset += 2; 2207 2208 for (i = init->offset; i < init->offset + count; i++) 2209 cont("0x%02x ", nvbios_rd08(bios, i)); 2210 cont("\n"); 2211 2212 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { 2213 if (func.func != DCB_GPIO_UNUSED) { 2214 for (i = init->offset; i < init->offset + count; i++) { 2215 if (func.func == nvbios_rd08(bios, i)) 2216 break; 2217 } 2218 2219 trace("\tFUNC[0x%02x]", func.func); 2220 if (i == (init->offset + count)) { 2221 cont(" *"); 2222 if (init_exec(init)) 2223 nvkm_gpio_reset(gpio, func.func); 2224 } 2225 cont("\n"); 2226 } 2227 } 2228 2229 init->offset += count; 2230 } 2231 2232 static struct nvbios_init_opcode { 2233 void (*exec)(struct nvbios_init *); 2234 } init_opcode[] = { 2235 [0x32] = { init_io_restrict_prog }, 2236 [0x33] = { init_repeat }, 2237 [0x34] = { init_io_restrict_pll }, 2238 [0x36] = { init_end_repeat }, 2239 [0x37] = { init_copy }, 2240 [0x38] = { init_not }, 2241 [0x39] = { init_io_flag_condition }, 2242 [0x3a] = { init_generic_condition }, 2243 [0x3b] = { init_io_mask_or }, 2244 [0x3c] = { init_io_or }, 2245 [0x47] = { init_andn_reg }, 2246 [0x48] = { init_or_reg }, 2247 [0x49] = { init_idx_addr_latched }, 2248 [0x4a] = { init_io_restrict_pll2 }, 2249 [0x4b] = { init_pll2 }, 2250 [0x4c] = { init_i2c_byte }, 2251 [0x4d] = { init_zm_i2c_byte }, 2252 [0x4e] = { init_zm_i2c }, 2253 [0x4f] = { init_tmds }, 2254 [0x50] = { init_zm_tmds_group }, 2255 [0x51] = { init_cr_idx_adr_latch }, 2256 [0x52] = { init_cr }, 2257 [0x53] = { init_zm_cr }, 2258 [0x54] = { init_zm_cr_group }, 2259 [0x56] = { init_condition_time }, 2260 [0x57] = { init_ltime }, 2261 [0x58] = { init_zm_reg_sequence }, 2262 [0x59] = { init_pll_indirect }, 2263 [0x5a] = { init_zm_reg_indirect }, 2264 [0x5b] = { init_sub_direct }, 2265 [0x5c] = { init_jump }, 2266 [0x5e] = { init_i2c_if }, 2267 [0x5f] = { init_copy_nv_reg }, 2268 [0x62] = { init_zm_index_io }, 2269 [0x63] = { init_compute_mem }, 2270 [0x65] = { init_reset }, 2271 [0x66] = { init_configure_mem }, 2272 [0x67] = { init_configure_clk }, 2273 [0x68] = { init_configure_preinit }, 2274 [0x69] = { init_io }, 2275 [0x6b] = { init_sub }, 2276 [0x6d] = { init_ram_condition }, 2277 [0x6e] = { init_nv_reg }, 2278 [0x6f] = { init_macro }, 2279 [0x71] = { init_done }, 2280 [0x72] = { init_resume }, 2281 [0x73] = { init_strap_condition }, 2282 [0x74] = { init_time }, 2283 [0x75] = { init_condition }, 2284 [0x76] = { init_io_condition }, 2285 [0x77] = { init_zm_reg16 }, 2286 [0x78] = { init_index_io }, 2287 [0x79] = { init_pll }, 2288 [0x7a] = { init_zm_reg }, 2289 [0x87] = { init_ram_restrict_pll }, 2290 [0x8c] = { init_reset_begun }, 2291 [0x8d] = { init_reset_end }, 2292 [0x8e] = { init_gpio }, 2293 [0x8f] = { init_ram_restrict_zm_reg_group }, 2294 [0x90] = { init_copy_zm_reg }, 2295 [0x91] = { init_zm_reg_group }, 2296 [0x92] = { init_reserved }, 2297 [0x96] = { init_xlat }, 2298 [0x97] = { init_zm_mask_add }, 2299 [0x98] = { init_auxch }, 2300 [0x99] = { init_zm_auxch }, 2301 [0x9a] = { init_i2c_long_if }, 2302 [0xa9] = { init_gpio_ne }, 2303 [0xaa] = { init_reserved }, 2304 }; 2305 2306 int 2307 nvbios_exec(struct nvbios_init *init) 2308 { 2309 struct nvkm_bios *bios = init->subdev->device->bios; 2310 2311 init->nested++; 2312 while (init->offset) { 2313 u8 opcode = nvbios_rd08(bios, init->offset); 2314 if (opcode >= ARRAY_SIZE(init_opcode) || 2315 !init_opcode[opcode].exec) { 2316 error("unknown opcode 0x%02x\n", opcode); 2317 return -EINVAL; 2318 } 2319 2320 init_opcode[opcode].exec(init); 2321 } 2322 init->nested--; 2323 return 0; 2324 } 2325 2326 int 2327 nvbios_post(struct nvkm_subdev *subdev, bool execute) 2328 { 2329 struct nvkm_bios *bios = subdev->device->bios; 2330 int ret = 0; 2331 int i = -1; 2332 u16 data; 2333 2334 if (execute) 2335 nvkm_debug(subdev, "running init tables\n"); 2336 while (!ret && (data = (init_script(bios, ++i)))) { 2337 ret = nvbios_init(subdev, data, 2338 init.execute = execute ? 1 : 0; 2339 ); 2340 } 2341 2342 /* the vbios parser will run this right after the normal init 2343 * tables, whereas the binary driver appears to run it later. 2344 */ 2345 if (!ret && (data = init_unknown_script(bios))) { 2346 ret = nvbios_init(subdev, data, 2347 init.execute = execute ? 1 : 0; 2348 ); 2349 } 2350 2351 return ret; 2352 } 2353
Indexes created Sat Sep 20 22:09:52 GMT 2025