1 /* $NetBSD: nouveau_nvkm_engine_device_base.c,v 1.13 2024/04/16 14:34:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_device_base.c,v 1.13 2024/04/16 14:34:02 riastradh Exp $"); 28 29 #include "priv.h" 30 #include "acpi.h" 31 32 #include <core/notify.h> 33 #include <core/option.h> 34 35 #include <subdev/bios.h> 36 #include <subdev/therm.h> 37 38 #ifdef __NetBSD__ 39 #include <linux/nbsd-namespace.h> 40 static struct mutex nv_devices_mutex; 41 static struct list_head nv_devices = LIST_HEAD_INIT(nv_devices); 42 43 void 44 nvkm_devices_init(void) 45 { 46 47 linux_mutex_init(&nv_devices_mutex); 48 } 49 50 void 51 nvkm_devices_fini(void) 52 { 53 54 linux_mutex_destroy(&nv_devices_mutex); 55 } 56 #else 57 static DEFINE_MUTEX(nv_devices_mutex); 58 static LIST_HEAD(nv_devices); 59 #endif 60 61 static struct nvkm_device * 62 nvkm_device_find_locked(u64 handle) 63 { 64 struct nvkm_device *device; 65 list_for_each_entry(device, &nv_devices, head) { 66 if (device->handle == handle) 67 return device; 68 } 69 return NULL; 70 } 71 72 struct nvkm_device * 73 nvkm_device_find(u64 handle) 74 { 75 struct nvkm_device *device; 76 mutex_lock(&nv_devices_mutex); 77 device = nvkm_device_find_locked(handle); 78 mutex_unlock(&nv_devices_mutex); 79 return device; 80 } 81 82 int 83 nvkm_device_list(u64 *name, int size) 84 { 85 struct nvkm_device *device; 86 int nr = 0; 87 mutex_lock(&nv_devices_mutex); 88 list_for_each_entry(device, &nv_devices, head) { 89 if (nr++ < size) 90 name[nr - 1] = device->handle; 91 } 92 mutex_unlock(&nv_devices_mutex); 93 return nr; 94 } 95 96 static const struct nvkm_device_chip 97 null_chipset = { 98 .name = "NULL", 99 .bios = nvkm_bios_new, 100 }; 101 102 static const struct nvkm_device_chip 103 nv4_chipset = { 104 .name = "NV04", 105 .bios = nvkm_bios_new, 106 .bus = nv04_bus_new, 107 .clk = nv04_clk_new, 108 .devinit = nv04_devinit_new, 109 .fb = nv04_fb_new, 110 .i2c = nv04_i2c_new, 111 .imem = nv04_instmem_new, 112 .mc = nv04_mc_new, 113 .mmu = nv04_mmu_new, 114 .pci = nv04_pci_new, 115 .timer = nv04_timer_new, 116 .disp = nv04_disp_new, 117 .dma = nv04_dma_new, 118 .fifo = nv04_fifo_new, 119 .gr = nv04_gr_new, 120 .sw = nv04_sw_new, 121 }; 122 123 static const struct nvkm_device_chip 124 nv5_chipset = { 125 .name = "NV05", 126 .bios = nvkm_bios_new, 127 .bus = nv04_bus_new, 128 .clk = nv04_clk_new, 129 .devinit = nv05_devinit_new, 130 .fb = nv04_fb_new, 131 .i2c = nv04_i2c_new, 132 .imem = nv04_instmem_new, 133 .mc = nv04_mc_new, 134 .mmu = nv04_mmu_new, 135 .pci = nv04_pci_new, 136 .timer = nv04_timer_new, 137 .disp = nv04_disp_new, 138 .dma = nv04_dma_new, 139 .fifo = nv04_fifo_new, 140 .gr = nv04_gr_new, 141 .sw = nv04_sw_new, 142 }; 143 144 static const struct nvkm_device_chip 145 nv10_chipset = { 146 .name = "NV10", 147 .bios = nvkm_bios_new, 148 .bus = nv04_bus_new, 149 .clk = nv04_clk_new, 150 .devinit = nv10_devinit_new, 151 .fb = nv10_fb_new, 152 .gpio = nv10_gpio_new, 153 .i2c = nv04_i2c_new, 154 .imem = nv04_instmem_new, 155 .mc = nv04_mc_new, 156 .mmu = nv04_mmu_new, 157 .pci = nv04_pci_new, 158 .timer = nv04_timer_new, 159 .disp = nv04_disp_new, 160 .dma = nv04_dma_new, 161 .gr = nv10_gr_new, 162 }; 163 164 static const struct nvkm_device_chip 165 nv11_chipset = { 166 .name = "NV11", 167 .bios = nvkm_bios_new, 168 .bus = nv04_bus_new, 169 .clk = nv04_clk_new, 170 .devinit = nv10_devinit_new, 171 .fb = nv10_fb_new, 172 .gpio = nv10_gpio_new, 173 .i2c = nv04_i2c_new, 174 .imem = nv04_instmem_new, 175 .mc = nv11_mc_new, 176 .mmu = nv04_mmu_new, 177 .pci = nv04_pci_new, 178 .timer = nv04_timer_new, 179 .disp = nv04_disp_new, 180 .dma = nv04_dma_new, 181 .fifo = nv10_fifo_new, 182 .gr = nv15_gr_new, 183 .sw = nv10_sw_new, 184 }; 185 186 static const struct nvkm_device_chip 187 nv15_chipset = { 188 .name = "NV15", 189 .bios = nvkm_bios_new, 190 .bus = nv04_bus_new, 191 .clk = nv04_clk_new, 192 .devinit = nv10_devinit_new, 193 .fb = nv10_fb_new, 194 .gpio = nv10_gpio_new, 195 .i2c = nv04_i2c_new, 196 .imem = nv04_instmem_new, 197 .mc = nv04_mc_new, 198 .mmu = nv04_mmu_new, 199 .pci = nv04_pci_new, 200 .timer = nv04_timer_new, 201 .disp = nv04_disp_new, 202 .dma = nv04_dma_new, 203 .fifo = nv10_fifo_new, 204 .gr = nv15_gr_new, 205 .sw = nv10_sw_new, 206 }; 207 208 static const struct nvkm_device_chip 209 nv17_chipset = { 210 .name = "NV17", 211 .bios = nvkm_bios_new, 212 .bus = nv04_bus_new, 213 .clk = nv04_clk_new, 214 .devinit = nv10_devinit_new, 215 .fb = nv10_fb_new, 216 .gpio = nv10_gpio_new, 217 .i2c = nv04_i2c_new, 218 .imem = nv04_instmem_new, 219 .mc = nv17_mc_new, 220 .mmu = nv04_mmu_new, 221 .pci = nv04_pci_new, 222 .timer = nv04_timer_new, 223 .disp = nv04_disp_new, 224 .dma = nv04_dma_new, 225 .fifo = nv17_fifo_new, 226 .gr = nv17_gr_new, 227 .sw = nv10_sw_new, 228 }; 229 230 static const struct nvkm_device_chip 231 nv18_chipset = { 232 .name = "NV18", 233 .bios = nvkm_bios_new, 234 .bus = nv04_bus_new, 235 .clk = nv04_clk_new, 236 .devinit = nv10_devinit_new, 237 .fb = nv10_fb_new, 238 .gpio = nv10_gpio_new, 239 .i2c = nv04_i2c_new, 240 .imem = nv04_instmem_new, 241 .mc = nv17_mc_new, 242 .mmu = nv04_mmu_new, 243 .pci = nv04_pci_new, 244 .timer = nv04_timer_new, 245 .disp = nv04_disp_new, 246 .dma = nv04_dma_new, 247 .fifo = nv17_fifo_new, 248 .gr = nv17_gr_new, 249 .sw = nv10_sw_new, 250 }; 251 252 static const struct nvkm_device_chip 253 nv1a_chipset = { 254 .name = "nForce", 255 .bios = nvkm_bios_new, 256 .bus = nv04_bus_new, 257 .clk = nv04_clk_new, 258 .devinit = nv1a_devinit_new, 259 .fb = nv1a_fb_new, 260 .gpio = nv10_gpio_new, 261 .i2c = nv04_i2c_new, 262 .imem = nv04_instmem_new, 263 .mc = nv04_mc_new, 264 .mmu = nv04_mmu_new, 265 .pci = nv04_pci_new, 266 .timer = nv04_timer_new, 267 .disp = nv04_disp_new, 268 .dma = nv04_dma_new, 269 .fifo = nv10_fifo_new, 270 .gr = nv15_gr_new, 271 .sw = nv10_sw_new, 272 }; 273 274 static const struct nvkm_device_chip 275 nv1f_chipset = { 276 .name = "nForce2", 277 .bios = nvkm_bios_new, 278 .bus = nv04_bus_new, 279 .clk = nv04_clk_new, 280 .devinit = nv1a_devinit_new, 281 .fb = nv1a_fb_new, 282 .gpio = nv10_gpio_new, 283 .i2c = nv04_i2c_new, 284 .imem = nv04_instmem_new, 285 .mc = nv17_mc_new, 286 .mmu = nv04_mmu_new, 287 .pci = nv04_pci_new, 288 .timer = nv04_timer_new, 289 .disp = nv04_disp_new, 290 .dma = nv04_dma_new, 291 .fifo = nv17_fifo_new, 292 .gr = nv17_gr_new, 293 .sw = nv10_sw_new, 294 }; 295 296 static const struct nvkm_device_chip 297 nv20_chipset = { 298 .name = "NV20", 299 .bios = nvkm_bios_new, 300 .bus = nv04_bus_new, 301 .clk = nv04_clk_new, 302 .devinit = nv20_devinit_new, 303 .fb = nv20_fb_new, 304 .gpio = nv10_gpio_new, 305 .i2c = nv04_i2c_new, 306 .imem = nv04_instmem_new, 307 .mc = nv17_mc_new, 308 .mmu = nv04_mmu_new, 309 .pci = nv04_pci_new, 310 .timer = nv04_timer_new, 311 .disp = nv04_disp_new, 312 .dma = nv04_dma_new, 313 .fifo = nv17_fifo_new, 314 .gr = nv20_gr_new, 315 .sw = nv10_sw_new, 316 }; 317 318 static const struct nvkm_device_chip 319 nv25_chipset = { 320 .name = "NV25", 321 .bios = nvkm_bios_new, 322 .bus = nv04_bus_new, 323 .clk = nv04_clk_new, 324 .devinit = nv20_devinit_new, 325 .fb = nv25_fb_new, 326 .gpio = nv10_gpio_new, 327 .i2c = nv04_i2c_new, 328 .imem = nv04_instmem_new, 329 .mc = nv17_mc_new, 330 .mmu = nv04_mmu_new, 331 .pci = nv04_pci_new, 332 .timer = nv04_timer_new, 333 .disp = nv04_disp_new, 334 .dma = nv04_dma_new, 335 .fifo = nv17_fifo_new, 336 .gr = nv25_gr_new, 337 .sw = nv10_sw_new, 338 }; 339 340 static const struct nvkm_device_chip 341 nv28_chipset = { 342 .name = "NV28", 343 .bios = nvkm_bios_new, 344 .bus = nv04_bus_new, 345 .clk = nv04_clk_new, 346 .devinit = nv20_devinit_new, 347 .fb = nv25_fb_new, 348 .gpio = nv10_gpio_new, 349 .i2c = nv04_i2c_new, 350 .imem = nv04_instmem_new, 351 .mc = nv17_mc_new, 352 .mmu = nv04_mmu_new, 353 .pci = nv04_pci_new, 354 .timer = nv04_timer_new, 355 .disp = nv04_disp_new, 356 .dma = nv04_dma_new, 357 .fifo = nv17_fifo_new, 358 .gr = nv25_gr_new, 359 .sw = nv10_sw_new, 360 }; 361 362 static const struct nvkm_device_chip 363 nv2a_chipset = { 364 .name = "NV2A", 365 .bios = nvkm_bios_new, 366 .bus = nv04_bus_new, 367 .clk = nv04_clk_new, 368 .devinit = nv20_devinit_new, 369 .fb = nv25_fb_new, 370 .gpio = nv10_gpio_new, 371 .i2c = nv04_i2c_new, 372 .imem = nv04_instmem_new, 373 .mc = nv17_mc_new, 374 .mmu = nv04_mmu_new, 375 .pci = nv04_pci_new, 376 .timer = nv04_timer_new, 377 .disp = nv04_disp_new, 378 .dma = nv04_dma_new, 379 .fifo = nv17_fifo_new, 380 .gr = nv2a_gr_new, 381 .sw = nv10_sw_new, 382 }; 383 384 static const struct nvkm_device_chip 385 nv30_chipset = { 386 .name = "NV30", 387 .bios = nvkm_bios_new, 388 .bus = nv04_bus_new, 389 .clk = nv04_clk_new, 390 .devinit = nv20_devinit_new, 391 .fb = nv30_fb_new, 392 .gpio = nv10_gpio_new, 393 .i2c = nv04_i2c_new, 394 .imem = nv04_instmem_new, 395 .mc = nv17_mc_new, 396 .mmu = nv04_mmu_new, 397 .pci = nv04_pci_new, 398 .timer = nv04_timer_new, 399 .disp = nv04_disp_new, 400 .dma = nv04_dma_new, 401 .fifo = nv17_fifo_new, 402 .gr = nv30_gr_new, 403 .sw = nv10_sw_new, 404 }; 405 406 static const struct nvkm_device_chip 407 nv31_chipset = { 408 .name = "NV31", 409 .bios = nvkm_bios_new, 410 .bus = nv31_bus_new, 411 .clk = nv04_clk_new, 412 .devinit = nv20_devinit_new, 413 .fb = nv30_fb_new, 414 .gpio = nv10_gpio_new, 415 .i2c = nv04_i2c_new, 416 .imem = nv04_instmem_new, 417 .mc = nv17_mc_new, 418 .mmu = nv04_mmu_new, 419 .pci = nv04_pci_new, 420 .timer = nv04_timer_new, 421 .disp = nv04_disp_new, 422 .dma = nv04_dma_new, 423 .fifo = nv17_fifo_new, 424 .gr = nv30_gr_new, 425 .mpeg = nv31_mpeg_new, 426 .sw = nv10_sw_new, 427 }; 428 429 static const struct nvkm_device_chip 430 nv34_chipset = { 431 .name = "NV34", 432 .bios = nvkm_bios_new, 433 .bus = nv31_bus_new, 434 .clk = nv04_clk_new, 435 .devinit = nv10_devinit_new, 436 .fb = nv10_fb_new, 437 .gpio = nv10_gpio_new, 438 .i2c = nv04_i2c_new, 439 .imem = nv04_instmem_new, 440 .mc = nv17_mc_new, 441 .mmu = nv04_mmu_new, 442 .pci = nv04_pci_new, 443 .timer = nv04_timer_new, 444 .disp = nv04_disp_new, 445 .dma = nv04_dma_new, 446 .fifo = nv17_fifo_new, 447 .gr = nv34_gr_new, 448 .mpeg = nv31_mpeg_new, 449 .sw = nv10_sw_new, 450 }; 451 452 static const struct nvkm_device_chip 453 nv35_chipset = { 454 .name = "NV35", 455 .bios = nvkm_bios_new, 456 .bus = nv04_bus_new, 457 .clk = nv04_clk_new, 458 .devinit = nv20_devinit_new, 459 .fb = nv35_fb_new, 460 .gpio = nv10_gpio_new, 461 .i2c = nv04_i2c_new, 462 .imem = nv04_instmem_new, 463 .mc = nv17_mc_new, 464 .mmu = nv04_mmu_new, 465 .pci = nv04_pci_new, 466 .timer = nv04_timer_new, 467 .disp = nv04_disp_new, 468 .dma = nv04_dma_new, 469 .fifo = nv17_fifo_new, 470 .gr = nv35_gr_new, 471 .sw = nv10_sw_new, 472 }; 473 474 static const struct nvkm_device_chip 475 nv36_chipset = { 476 .name = "NV36", 477 .bios = nvkm_bios_new, 478 .bus = nv31_bus_new, 479 .clk = nv04_clk_new, 480 .devinit = nv20_devinit_new, 481 .fb = nv36_fb_new, 482 .gpio = nv10_gpio_new, 483 .i2c = nv04_i2c_new, 484 .imem = nv04_instmem_new, 485 .mc = nv17_mc_new, 486 .mmu = nv04_mmu_new, 487 .pci = nv04_pci_new, 488 .timer = nv04_timer_new, 489 .disp = nv04_disp_new, 490 .dma = nv04_dma_new, 491 .fifo = nv17_fifo_new, 492 .gr = nv35_gr_new, 493 .mpeg = nv31_mpeg_new, 494 .sw = nv10_sw_new, 495 }; 496 497 static const struct nvkm_device_chip 498 nv40_chipset = { 499 .name = "NV40", 500 .bios = nvkm_bios_new, 501 .bus = nv31_bus_new, 502 .clk = nv40_clk_new, 503 .devinit = nv1a_devinit_new, 504 .fb = nv40_fb_new, 505 .gpio = nv10_gpio_new, 506 .i2c = nv04_i2c_new, 507 .imem = nv40_instmem_new, 508 .mc = nv17_mc_new, 509 .mmu = nv04_mmu_new, 510 .pci = nv40_pci_new, 511 .therm = nv40_therm_new, 512 .timer = nv40_timer_new, 513 .volt = nv40_volt_new, 514 .disp = nv04_disp_new, 515 .dma = nv04_dma_new, 516 .fifo = nv40_fifo_new, 517 .gr = nv40_gr_new, 518 .mpeg = nv40_mpeg_new, 519 .pm = nv40_pm_new, 520 .sw = nv10_sw_new, 521 }; 522 523 static const struct nvkm_device_chip 524 nv41_chipset = { 525 .name = "NV41", 526 .bios = nvkm_bios_new, 527 .bus = nv31_bus_new, 528 .clk = nv40_clk_new, 529 .devinit = nv1a_devinit_new, 530 .fb = nv41_fb_new, 531 .gpio = nv10_gpio_new, 532 .i2c = nv04_i2c_new, 533 .imem = nv40_instmem_new, 534 .mc = nv17_mc_new, 535 .mmu = nv41_mmu_new, 536 .pci = nv40_pci_new, 537 .therm = nv40_therm_new, 538 .timer = nv41_timer_new, 539 .volt = nv40_volt_new, 540 .disp = nv04_disp_new, 541 .dma = nv04_dma_new, 542 .fifo = nv40_fifo_new, 543 .gr = nv40_gr_new, 544 .mpeg = nv40_mpeg_new, 545 .pm = nv40_pm_new, 546 .sw = nv10_sw_new, 547 }; 548 549 static const struct nvkm_device_chip 550 nv42_chipset = { 551 .name = "NV42", 552 .bios = nvkm_bios_new, 553 .bus = nv31_bus_new, 554 .clk = nv40_clk_new, 555 .devinit = nv1a_devinit_new, 556 .fb = nv41_fb_new, 557 .gpio = nv10_gpio_new, 558 .i2c = nv04_i2c_new, 559 .imem = nv40_instmem_new, 560 .mc = nv17_mc_new, 561 .mmu = nv41_mmu_new, 562 .pci = nv40_pci_new, 563 .therm = nv40_therm_new, 564 .timer = nv41_timer_new, 565 .volt = nv40_volt_new, 566 .disp = nv04_disp_new, 567 .dma = nv04_dma_new, 568 .fifo = nv40_fifo_new, 569 .gr = nv40_gr_new, 570 .mpeg = nv40_mpeg_new, 571 .pm = nv40_pm_new, 572 .sw = nv10_sw_new, 573 }; 574 575 static const struct nvkm_device_chip 576 nv43_chipset = { 577 .name = "NV43", 578 .bios = nvkm_bios_new, 579 .bus = nv31_bus_new, 580 .clk = nv40_clk_new, 581 .devinit = nv1a_devinit_new, 582 .fb = nv41_fb_new, 583 .gpio = nv10_gpio_new, 584 .i2c = nv04_i2c_new, 585 .imem = nv40_instmem_new, 586 .mc = nv17_mc_new, 587 .mmu = nv41_mmu_new, 588 .pci = nv40_pci_new, 589 .therm = nv40_therm_new, 590 .timer = nv41_timer_new, 591 .volt = nv40_volt_new, 592 .disp = nv04_disp_new, 593 .dma = nv04_dma_new, 594 .fifo = nv40_fifo_new, 595 .gr = nv40_gr_new, 596 .mpeg = nv40_mpeg_new, 597 .pm = nv40_pm_new, 598 .sw = nv10_sw_new, 599 }; 600 601 static const struct nvkm_device_chip 602 nv44_chipset = { 603 .name = "NV44", 604 .bios = nvkm_bios_new, 605 .bus = nv31_bus_new, 606 .clk = nv40_clk_new, 607 .devinit = nv1a_devinit_new, 608 .fb = nv44_fb_new, 609 .gpio = nv10_gpio_new, 610 .i2c = nv04_i2c_new, 611 .imem = nv40_instmem_new, 612 .mc = nv44_mc_new, 613 .mmu = nv44_mmu_new, 614 .pci = nv40_pci_new, 615 .therm = nv40_therm_new, 616 .timer = nv41_timer_new, 617 .volt = nv40_volt_new, 618 .disp = nv04_disp_new, 619 .dma = nv04_dma_new, 620 .fifo = nv40_fifo_new, 621 .gr = nv44_gr_new, 622 .mpeg = nv44_mpeg_new, 623 .pm = nv40_pm_new, 624 .sw = nv10_sw_new, 625 }; 626 627 static const struct nvkm_device_chip 628 nv45_chipset = { 629 .name = "NV45", 630 .bios = nvkm_bios_new, 631 .bus = nv31_bus_new, 632 .clk = nv40_clk_new, 633 .devinit = nv1a_devinit_new, 634 .fb = nv40_fb_new, 635 .gpio = nv10_gpio_new, 636 .i2c = nv04_i2c_new, 637 .imem = nv40_instmem_new, 638 .mc = nv17_mc_new, 639 .mmu = nv04_mmu_new, 640 .pci = nv40_pci_new, 641 .therm = nv40_therm_new, 642 .timer = nv41_timer_new, 643 .volt = nv40_volt_new, 644 .disp = nv04_disp_new, 645 .dma = nv04_dma_new, 646 .fifo = nv40_fifo_new, 647 .gr = nv40_gr_new, 648 .mpeg = nv44_mpeg_new, 649 .pm = nv40_pm_new, 650 .sw = nv10_sw_new, 651 }; 652 653 static const struct nvkm_device_chip 654 nv46_chipset = { 655 .name = "G72", 656 .bios = nvkm_bios_new, 657 .bus = nv31_bus_new, 658 .clk = nv40_clk_new, 659 .devinit = nv1a_devinit_new, 660 .fb = nv46_fb_new, 661 .gpio = nv10_gpio_new, 662 .i2c = nv04_i2c_new, 663 .imem = nv40_instmem_new, 664 .mc = nv44_mc_new, 665 .mmu = nv44_mmu_new, 666 .pci = nv46_pci_new, 667 .therm = nv40_therm_new, 668 .timer = nv41_timer_new, 669 .volt = nv40_volt_new, 670 .disp = nv04_disp_new, 671 .dma = nv04_dma_new, 672 .fifo = nv40_fifo_new, 673 .gr = nv44_gr_new, 674 .mpeg = nv44_mpeg_new, 675 .pm = nv40_pm_new, 676 .sw = nv10_sw_new, 677 }; 678 679 static const struct nvkm_device_chip 680 nv47_chipset = { 681 .name = "G70", 682 .bios = nvkm_bios_new, 683 .bus = nv31_bus_new, 684 .clk = nv40_clk_new, 685 .devinit = nv1a_devinit_new, 686 .fb = nv47_fb_new, 687 .gpio = nv10_gpio_new, 688 .i2c = nv04_i2c_new, 689 .imem = nv40_instmem_new, 690 .mc = nv17_mc_new, 691 .mmu = nv41_mmu_new, 692 .pci = nv40_pci_new, 693 .therm = nv40_therm_new, 694 .timer = nv41_timer_new, 695 .volt = nv40_volt_new, 696 .disp = nv04_disp_new, 697 .dma = nv04_dma_new, 698 .fifo = nv40_fifo_new, 699 .gr = nv40_gr_new, 700 .mpeg = nv44_mpeg_new, 701 .pm = nv40_pm_new, 702 .sw = nv10_sw_new, 703 }; 704 705 static const struct nvkm_device_chip 706 nv49_chipset = { 707 .name = "G71", 708 .bios = nvkm_bios_new, 709 .bus = nv31_bus_new, 710 .clk = nv40_clk_new, 711 .devinit = nv1a_devinit_new, 712 .fb = nv49_fb_new, 713 .gpio = nv10_gpio_new, 714 .i2c = nv04_i2c_new, 715 .imem = nv40_instmem_new, 716 .mc = nv17_mc_new, 717 .mmu = nv41_mmu_new, 718 .pci = nv40_pci_new, 719 .therm = nv40_therm_new, 720 .timer = nv41_timer_new, 721 .volt = nv40_volt_new, 722 .disp = nv04_disp_new, 723 .dma = nv04_dma_new, 724 .fifo = nv40_fifo_new, 725 .gr = nv40_gr_new, 726 .mpeg = nv44_mpeg_new, 727 .pm = nv40_pm_new, 728 .sw = nv10_sw_new, 729 }; 730 731 static const struct nvkm_device_chip 732 nv4a_chipset = { 733 .name = "NV44A", 734 .bios = nvkm_bios_new, 735 .bus = nv31_bus_new, 736 .clk = nv40_clk_new, 737 .devinit = nv1a_devinit_new, 738 .fb = nv44_fb_new, 739 .gpio = nv10_gpio_new, 740 .i2c = nv04_i2c_new, 741 .imem = nv40_instmem_new, 742 .mc = nv44_mc_new, 743 .mmu = nv04_mmu_new, 744 .pci = nv40_pci_new, 745 .therm = nv40_therm_new, 746 .timer = nv41_timer_new, 747 .volt = nv40_volt_new, 748 .disp = nv04_disp_new, 749 .dma = nv04_dma_new, 750 .fifo = nv40_fifo_new, 751 .gr = nv44_gr_new, 752 .mpeg = nv44_mpeg_new, 753 .pm = nv40_pm_new, 754 .sw = nv10_sw_new, 755 }; 756 757 static const struct nvkm_device_chip 758 nv4b_chipset = { 759 .name = "G73", 760 .bios = nvkm_bios_new, 761 .bus = nv31_bus_new, 762 .clk = nv40_clk_new, 763 .devinit = nv1a_devinit_new, 764 .fb = nv49_fb_new, 765 .gpio = nv10_gpio_new, 766 .i2c = nv04_i2c_new, 767 .imem = nv40_instmem_new, 768 .mc = nv17_mc_new, 769 .mmu = nv41_mmu_new, 770 .pci = nv40_pci_new, 771 .therm = nv40_therm_new, 772 .timer = nv41_timer_new, 773 .volt = nv40_volt_new, 774 .disp = nv04_disp_new, 775 .dma = nv04_dma_new, 776 .fifo = nv40_fifo_new, 777 .gr = nv40_gr_new, 778 .mpeg = nv44_mpeg_new, 779 .pm = nv40_pm_new, 780 .sw = nv10_sw_new, 781 }; 782 783 static const struct nvkm_device_chip 784 nv4c_chipset = { 785 .name = "C61", 786 .bios = nvkm_bios_new, 787 .bus = nv31_bus_new, 788 .clk = nv40_clk_new, 789 .devinit = nv1a_devinit_new, 790 .fb = nv46_fb_new, 791 .gpio = nv10_gpio_new, 792 .i2c = nv04_i2c_new, 793 .imem = nv40_instmem_new, 794 .mc = nv44_mc_new, 795 .mmu = nv44_mmu_new, 796 .pci = nv4c_pci_new, 797 .therm = nv40_therm_new, 798 .timer = nv41_timer_new, 799 .volt = nv40_volt_new, 800 .disp = nv04_disp_new, 801 .dma = nv04_dma_new, 802 .fifo = nv40_fifo_new, 803 .gr = nv44_gr_new, 804 .mpeg = nv44_mpeg_new, 805 .pm = nv40_pm_new, 806 .sw = nv10_sw_new, 807 }; 808 809 static const struct nvkm_device_chip 810 nv4e_chipset = { 811 .name = "C51", 812 .bios = nvkm_bios_new, 813 .bus = nv31_bus_new, 814 .clk = nv40_clk_new, 815 .devinit = nv1a_devinit_new, 816 .fb = nv4e_fb_new, 817 .gpio = nv10_gpio_new, 818 .i2c = nv4e_i2c_new, 819 .imem = nv40_instmem_new, 820 .mc = nv44_mc_new, 821 .mmu = nv44_mmu_new, 822 .pci = nv4c_pci_new, 823 .therm = nv40_therm_new, 824 .timer = nv41_timer_new, 825 .volt = nv40_volt_new, 826 .disp = nv04_disp_new, 827 .dma = nv04_dma_new, 828 .fifo = nv40_fifo_new, 829 .gr = nv44_gr_new, 830 .mpeg = nv44_mpeg_new, 831 .pm = nv40_pm_new, 832 .sw = nv10_sw_new, 833 }; 834 835 static const struct nvkm_device_chip 836 nv50_chipset = { 837 .name = "G80", 838 .bar = nv50_bar_new, 839 .bios = nvkm_bios_new, 840 .bus = nv50_bus_new, 841 .clk = nv50_clk_new, 842 .devinit = nv50_devinit_new, 843 .fb = nv50_fb_new, 844 .fuse = nv50_fuse_new, 845 .gpio = nv50_gpio_new, 846 .i2c = nv50_i2c_new, 847 .imem = nv50_instmem_new, 848 .mc = nv50_mc_new, 849 .mmu = nv50_mmu_new, 850 .mxm = nv50_mxm_new, 851 .pci = nv46_pci_new, 852 .therm = nv50_therm_new, 853 .timer = nv41_timer_new, 854 .volt = nv40_volt_new, 855 .disp = nv50_disp_new, 856 .dma = nv50_dma_new, 857 .fifo = nv50_fifo_new, 858 .gr = nv50_gr_new, 859 .mpeg = nv50_mpeg_new, 860 .pm = nv50_pm_new, 861 .sw = nv50_sw_new, 862 }; 863 864 static const struct nvkm_device_chip 865 nv63_chipset = { 866 .name = "C73", 867 .bios = nvkm_bios_new, 868 .bus = nv31_bus_new, 869 .clk = nv40_clk_new, 870 .devinit = nv1a_devinit_new, 871 .fb = nv46_fb_new, 872 .gpio = nv10_gpio_new, 873 .i2c = nv04_i2c_new, 874 .imem = nv40_instmem_new, 875 .mc = nv44_mc_new, 876 .mmu = nv44_mmu_new, 877 .pci = nv4c_pci_new, 878 .therm = nv40_therm_new, 879 .timer = nv41_timer_new, 880 .volt = nv40_volt_new, 881 .disp = nv04_disp_new, 882 .dma = nv04_dma_new, 883 .fifo = nv40_fifo_new, 884 .gr = nv44_gr_new, 885 .mpeg = nv44_mpeg_new, 886 .pm = nv40_pm_new, 887 .sw = nv10_sw_new, 888 }; 889 890 static const struct nvkm_device_chip 891 nv67_chipset = { 892 .name = "C67", 893 .bios = nvkm_bios_new, 894 .bus = nv31_bus_new, 895 .clk = nv40_clk_new, 896 .devinit = nv1a_devinit_new, 897 .fb = nv46_fb_new, 898 .gpio = nv10_gpio_new, 899 .i2c = nv04_i2c_new, 900 .imem = nv40_instmem_new, 901 .mc = nv44_mc_new, 902 .mmu = nv44_mmu_new, 903 .pci = nv4c_pci_new, 904 .therm = nv40_therm_new, 905 .timer = nv41_timer_new, 906 .volt = nv40_volt_new, 907 .disp = nv04_disp_new, 908 .dma = nv04_dma_new, 909 .fifo = nv40_fifo_new, 910 .gr = nv44_gr_new, 911 .mpeg = nv44_mpeg_new, 912 .pm = nv40_pm_new, 913 .sw = nv10_sw_new, 914 }; 915 916 static const struct nvkm_device_chip 917 nv68_chipset = { 918 .name = "C68", 919 .bios = nvkm_bios_new, 920 .bus = nv31_bus_new, 921 .clk = nv40_clk_new, 922 .devinit = nv1a_devinit_new, 923 .fb = nv46_fb_new, 924 .gpio = nv10_gpio_new, 925 .i2c = nv04_i2c_new, 926 .imem = nv40_instmem_new, 927 .mc = nv44_mc_new, 928 .mmu = nv44_mmu_new, 929 .pci = nv4c_pci_new, 930 .therm = nv40_therm_new, 931 .timer = nv41_timer_new, 932 .volt = nv40_volt_new, 933 .disp = nv04_disp_new, 934 .dma = nv04_dma_new, 935 .fifo = nv40_fifo_new, 936 .gr = nv44_gr_new, 937 .mpeg = nv44_mpeg_new, 938 .pm = nv40_pm_new, 939 .sw = nv10_sw_new, 940 }; 941 942 static const struct nvkm_device_chip 943 nv84_chipset = { 944 .name = "G84", 945 .bar = g84_bar_new, 946 .bios = nvkm_bios_new, 947 .bus = nv50_bus_new, 948 .clk = g84_clk_new, 949 .devinit = g84_devinit_new, 950 .fb = g84_fb_new, 951 .fuse = nv50_fuse_new, 952 .gpio = nv50_gpio_new, 953 .i2c = nv50_i2c_new, 954 .imem = nv50_instmem_new, 955 .mc = g84_mc_new, 956 .mmu = g84_mmu_new, 957 .mxm = nv50_mxm_new, 958 .pci = g84_pci_new, 959 .therm = g84_therm_new, 960 .timer = nv41_timer_new, 961 .volt = nv40_volt_new, 962 .bsp = g84_bsp_new, 963 .cipher = g84_cipher_new, 964 .disp = g84_disp_new, 965 .dma = nv50_dma_new, 966 .fifo = g84_fifo_new, 967 .gr = g84_gr_new, 968 .mpeg = g84_mpeg_new, 969 .pm = g84_pm_new, 970 .sw = nv50_sw_new, 971 .vp = g84_vp_new, 972 }; 973 974 static const struct nvkm_device_chip 975 nv86_chipset = { 976 .name = "G86", 977 .bar = g84_bar_new, 978 .bios = nvkm_bios_new, 979 .bus = nv50_bus_new, 980 .clk = g84_clk_new, 981 .devinit = g84_devinit_new, 982 .fb = g84_fb_new, 983 .fuse = nv50_fuse_new, 984 .gpio = nv50_gpio_new, 985 .i2c = nv50_i2c_new, 986 .imem = nv50_instmem_new, 987 .mc = g84_mc_new, 988 .mmu = g84_mmu_new, 989 .mxm = nv50_mxm_new, 990 .pci = g84_pci_new, 991 .therm = g84_therm_new, 992 .timer = nv41_timer_new, 993 .volt = nv40_volt_new, 994 .bsp = g84_bsp_new, 995 .cipher = g84_cipher_new, 996 .disp = g84_disp_new, 997 .dma = nv50_dma_new, 998 .fifo = g84_fifo_new, 999 .gr = g84_gr_new, 1000 .mpeg = g84_mpeg_new, 1001 .pm = g84_pm_new, 1002 .sw = nv50_sw_new, 1003 .vp = g84_vp_new, 1004 }; 1005 1006 static const struct nvkm_device_chip 1007 nv92_chipset = { 1008 .name = "G92", 1009 .bar = g84_bar_new, 1010 .bios = nvkm_bios_new, 1011 .bus = nv50_bus_new, 1012 .clk = g84_clk_new, 1013 .devinit = g84_devinit_new, 1014 .fb = g84_fb_new, 1015 .fuse = nv50_fuse_new, 1016 .gpio = nv50_gpio_new, 1017 .i2c = nv50_i2c_new, 1018 .imem = nv50_instmem_new, 1019 .mc = g84_mc_new, 1020 .mmu = g84_mmu_new, 1021 .mxm = nv50_mxm_new, 1022 .pci = g92_pci_new, 1023 .therm = g84_therm_new, 1024 .timer = nv41_timer_new, 1025 .volt = nv40_volt_new, 1026 .bsp = g84_bsp_new, 1027 .cipher = g84_cipher_new, 1028 .disp = g84_disp_new, 1029 .dma = nv50_dma_new, 1030 .fifo = g84_fifo_new, 1031 .gr = g84_gr_new, 1032 .mpeg = g84_mpeg_new, 1033 .pm = g84_pm_new, 1034 .sw = nv50_sw_new, 1035 .vp = g84_vp_new, 1036 }; 1037 1038 static const struct nvkm_device_chip 1039 nv94_chipset = { 1040 .name = "G94", 1041 .bar = g84_bar_new, 1042 .bios = nvkm_bios_new, 1043 .bus = g94_bus_new, 1044 .clk = g84_clk_new, 1045 .devinit = g84_devinit_new, 1046 .fb = g84_fb_new, 1047 .fuse = nv50_fuse_new, 1048 .gpio = g94_gpio_new, 1049 .i2c = g94_i2c_new, 1050 .imem = nv50_instmem_new, 1051 .mc = g84_mc_new, 1052 .mmu = g84_mmu_new, 1053 .mxm = nv50_mxm_new, 1054 .pci = g94_pci_new, 1055 .therm = g84_therm_new, 1056 .timer = nv41_timer_new, 1057 .volt = nv40_volt_new, 1058 .bsp = g84_bsp_new, 1059 .cipher = g84_cipher_new, 1060 .disp = g94_disp_new, 1061 .dma = nv50_dma_new, 1062 .fifo = g84_fifo_new, 1063 .gr = g84_gr_new, 1064 .mpeg = g84_mpeg_new, 1065 .pm = g84_pm_new, 1066 .sw = nv50_sw_new, 1067 .vp = g84_vp_new, 1068 }; 1069 1070 static const struct nvkm_device_chip 1071 nv96_chipset = { 1072 .name = "G96", 1073 .bar = g84_bar_new, 1074 .bios = nvkm_bios_new, 1075 .bus = g94_bus_new, 1076 .clk = g84_clk_new, 1077 .devinit = g84_devinit_new, 1078 .fb = g84_fb_new, 1079 .fuse = nv50_fuse_new, 1080 .gpio = g94_gpio_new, 1081 .i2c = g94_i2c_new, 1082 .imem = nv50_instmem_new, 1083 .mc = g84_mc_new, 1084 .mmu = g84_mmu_new, 1085 .mxm = nv50_mxm_new, 1086 .pci = g94_pci_new, 1087 .therm = g84_therm_new, 1088 .timer = nv41_timer_new, 1089 .volt = nv40_volt_new, 1090 .bsp = g84_bsp_new, 1091 .cipher = g84_cipher_new, 1092 .disp = g94_disp_new, 1093 .dma = nv50_dma_new, 1094 .fifo = g84_fifo_new, 1095 .gr = g84_gr_new, 1096 .mpeg = g84_mpeg_new, 1097 .pm = g84_pm_new, 1098 .sw = nv50_sw_new, 1099 .vp = g84_vp_new, 1100 }; 1101 1102 static const struct nvkm_device_chip 1103 nv98_chipset = { 1104 .name = "G98", 1105 .bar = g84_bar_new, 1106 .bios = nvkm_bios_new, 1107 .bus = g94_bus_new, 1108 .clk = g84_clk_new, 1109 .devinit = g98_devinit_new, 1110 .fb = g84_fb_new, 1111 .fuse = nv50_fuse_new, 1112 .gpio = g94_gpio_new, 1113 .i2c = g94_i2c_new, 1114 .imem = nv50_instmem_new, 1115 .mc = g98_mc_new, 1116 .mmu = g84_mmu_new, 1117 .mxm = nv50_mxm_new, 1118 .pci = g94_pci_new, 1119 .therm = g84_therm_new, 1120 .timer = nv41_timer_new, 1121 .volt = nv40_volt_new, 1122 .disp = g94_disp_new, 1123 .dma = nv50_dma_new, 1124 .fifo = g84_fifo_new, 1125 .gr = g84_gr_new, 1126 .mspdec = g98_mspdec_new, 1127 .msppp = g98_msppp_new, 1128 .msvld = g98_msvld_new, 1129 .pm = g84_pm_new, 1130 .sec = g98_sec_new, 1131 .sw = nv50_sw_new, 1132 }; 1133 1134 static const struct nvkm_device_chip 1135 nva0_chipset = { 1136 .name = "GT200", 1137 .bar = g84_bar_new, 1138 .bios = nvkm_bios_new, 1139 .bus = g94_bus_new, 1140 .clk = g84_clk_new, 1141 .devinit = g84_devinit_new, 1142 .fb = g84_fb_new, 1143 .fuse = nv50_fuse_new, 1144 .gpio = g94_gpio_new, 1145 .i2c = nv50_i2c_new, 1146 .imem = nv50_instmem_new, 1147 .mc = g84_mc_new, 1148 .mmu = g84_mmu_new, 1149 .mxm = nv50_mxm_new, 1150 .pci = g94_pci_new, 1151 .therm = g84_therm_new, 1152 .timer = nv41_timer_new, 1153 .volt = nv40_volt_new, 1154 .bsp = g84_bsp_new, 1155 .cipher = g84_cipher_new, 1156 .disp = gt200_disp_new, 1157 .dma = nv50_dma_new, 1158 .fifo = g84_fifo_new, 1159 .gr = gt200_gr_new, 1160 .mpeg = g84_mpeg_new, 1161 .pm = gt200_pm_new, 1162 .sw = nv50_sw_new, 1163 .vp = g84_vp_new, 1164 }; 1165 1166 static const struct nvkm_device_chip 1167 nva3_chipset = { 1168 .name = "GT215", 1169 .bar = g84_bar_new, 1170 .bios = nvkm_bios_new, 1171 .bus = g94_bus_new, 1172 .clk = gt215_clk_new, 1173 .devinit = gt215_devinit_new, 1174 .fb = gt215_fb_new, 1175 .fuse = nv50_fuse_new, 1176 .gpio = g94_gpio_new, 1177 .i2c = g94_i2c_new, 1178 .imem = nv50_instmem_new, 1179 .mc = gt215_mc_new, 1180 .mmu = g84_mmu_new, 1181 .mxm = nv50_mxm_new, 1182 .pci = g94_pci_new, 1183 .pmu = gt215_pmu_new, 1184 .therm = gt215_therm_new, 1185 .timer = nv41_timer_new, 1186 .volt = nv40_volt_new, 1187 .ce[0] = gt215_ce_new, 1188 .disp = gt215_disp_new, 1189 .dma = nv50_dma_new, 1190 .fifo = g84_fifo_new, 1191 .gr = gt215_gr_new, 1192 .mpeg = g84_mpeg_new, 1193 .mspdec = gt215_mspdec_new, 1194 .msppp = gt215_msppp_new, 1195 .msvld = gt215_msvld_new, 1196 .pm = gt215_pm_new, 1197 .sw = nv50_sw_new, 1198 }; 1199 1200 static const struct nvkm_device_chip 1201 nva5_chipset = { 1202 .name = "GT216", 1203 .bar = g84_bar_new, 1204 .bios = nvkm_bios_new, 1205 .bus = g94_bus_new, 1206 .clk = gt215_clk_new, 1207 .devinit = gt215_devinit_new, 1208 .fb = gt215_fb_new, 1209 .fuse = nv50_fuse_new, 1210 .gpio = g94_gpio_new, 1211 .i2c = g94_i2c_new, 1212 .imem = nv50_instmem_new, 1213 .mc = gt215_mc_new, 1214 .mmu = g84_mmu_new, 1215 .mxm = nv50_mxm_new, 1216 .pci = g94_pci_new, 1217 .pmu = gt215_pmu_new, 1218 .therm = gt215_therm_new, 1219 .timer = nv41_timer_new, 1220 .volt = nv40_volt_new, 1221 .ce[0] = gt215_ce_new, 1222 .disp = gt215_disp_new, 1223 .dma = nv50_dma_new, 1224 .fifo = g84_fifo_new, 1225 .gr = gt215_gr_new, 1226 .mspdec = gt215_mspdec_new, 1227 .msppp = gt215_msppp_new, 1228 .msvld = gt215_msvld_new, 1229 .pm = gt215_pm_new, 1230 .sw = nv50_sw_new, 1231 }; 1232 1233 static const struct nvkm_device_chip 1234 nva8_chipset = { 1235 .name = "GT218", 1236 .bar = g84_bar_new, 1237 .bios = nvkm_bios_new, 1238 .bus = g94_bus_new, 1239 .clk = gt215_clk_new, 1240 .devinit = gt215_devinit_new, 1241 .fb = gt215_fb_new, 1242 .fuse = nv50_fuse_new, 1243 .gpio = g94_gpio_new, 1244 .i2c = g94_i2c_new, 1245 .imem = nv50_instmem_new, 1246 .mc = gt215_mc_new, 1247 .mmu = g84_mmu_new, 1248 .mxm = nv50_mxm_new, 1249 .pci = g94_pci_new, 1250 .pmu = gt215_pmu_new, 1251 .therm = gt215_therm_new, 1252 .timer = nv41_timer_new, 1253 .volt = nv40_volt_new, 1254 .ce[0] = gt215_ce_new, 1255 .disp = gt215_disp_new, 1256 .dma = nv50_dma_new, 1257 .fifo = g84_fifo_new, 1258 .gr = gt215_gr_new, 1259 .mspdec = gt215_mspdec_new, 1260 .msppp = gt215_msppp_new, 1261 .msvld = gt215_msvld_new, 1262 .pm = gt215_pm_new, 1263 .sw = nv50_sw_new, 1264 }; 1265 1266 static const struct nvkm_device_chip 1267 nvaa_chipset = { 1268 .name = "MCP77/MCP78", 1269 .bar = g84_bar_new, 1270 .bios = nvkm_bios_new, 1271 .bus = g94_bus_new, 1272 .clk = mcp77_clk_new, 1273 .devinit = g98_devinit_new, 1274 .fb = mcp77_fb_new, 1275 .fuse = nv50_fuse_new, 1276 .gpio = g94_gpio_new, 1277 .i2c = g94_i2c_new, 1278 .imem = nv50_instmem_new, 1279 .mc = g98_mc_new, 1280 .mmu = mcp77_mmu_new, 1281 .mxm = nv50_mxm_new, 1282 .pci = g94_pci_new, 1283 .therm = g84_therm_new, 1284 .timer = nv41_timer_new, 1285 .volt = nv40_volt_new, 1286 .disp = mcp77_disp_new, 1287 .dma = nv50_dma_new, 1288 .fifo = g84_fifo_new, 1289 .gr = gt200_gr_new, 1290 .mspdec = g98_mspdec_new, 1291 .msppp = g98_msppp_new, 1292 .msvld = g98_msvld_new, 1293 .pm = g84_pm_new, 1294 .sec = g98_sec_new, 1295 .sw = nv50_sw_new, 1296 }; 1297 1298 static const struct nvkm_device_chip 1299 nvac_chipset = { 1300 .name = "MCP79/MCP7A", 1301 .bar = g84_bar_new, 1302 .bios = nvkm_bios_new, 1303 .bus = g94_bus_new, 1304 .clk = mcp77_clk_new, 1305 .devinit = g98_devinit_new, 1306 .fb = mcp77_fb_new, 1307 .fuse = nv50_fuse_new, 1308 .gpio = g94_gpio_new, 1309 .i2c = g94_i2c_new, 1310 .imem = nv50_instmem_new, 1311 .mc = g98_mc_new, 1312 .mmu = mcp77_mmu_new, 1313 .mxm = nv50_mxm_new, 1314 .pci = g94_pci_new, 1315 .therm = g84_therm_new, 1316 .timer = nv41_timer_new, 1317 .volt = nv40_volt_new, 1318 .disp = mcp77_disp_new, 1319 .dma = nv50_dma_new, 1320 .fifo = g84_fifo_new, 1321 .gr = mcp79_gr_new, 1322 .mspdec = g98_mspdec_new, 1323 .msppp = g98_msppp_new, 1324 .msvld = g98_msvld_new, 1325 .pm = g84_pm_new, 1326 .sec = g98_sec_new, 1327 .sw = nv50_sw_new, 1328 }; 1329 1330 static const struct nvkm_device_chip 1331 nvaf_chipset = { 1332 .name = "MCP89", 1333 .bar = g84_bar_new, 1334 .bios = nvkm_bios_new, 1335 .bus = g94_bus_new, 1336 .clk = gt215_clk_new, 1337 .devinit = mcp89_devinit_new, 1338 .fb = mcp89_fb_new, 1339 .fuse = nv50_fuse_new, 1340 .gpio = g94_gpio_new, 1341 .i2c = g94_i2c_new, 1342 .imem = nv50_instmem_new, 1343 .mc = gt215_mc_new, 1344 .mmu = mcp77_mmu_new, 1345 .mxm = nv50_mxm_new, 1346 .pci = g94_pci_new, 1347 .pmu = gt215_pmu_new, 1348 .therm = gt215_therm_new, 1349 .timer = nv41_timer_new, 1350 .volt = nv40_volt_new, 1351 .ce[0] = gt215_ce_new, 1352 .disp = mcp89_disp_new, 1353 .dma = nv50_dma_new, 1354 .fifo = g84_fifo_new, 1355 .gr = mcp89_gr_new, 1356 .mspdec = gt215_mspdec_new, 1357 .msppp = gt215_msppp_new, 1358 .msvld = mcp89_msvld_new, 1359 .pm = gt215_pm_new, 1360 .sw = nv50_sw_new, 1361 }; 1362 1363 static const struct nvkm_device_chip 1364 nvc0_chipset = { 1365 .name = "GF100", 1366 .bar = gf100_bar_new, 1367 .bios = nvkm_bios_new, 1368 .bus = gf100_bus_new, 1369 .clk = gf100_clk_new, 1370 .devinit = gf100_devinit_new, 1371 .fb = gf100_fb_new, 1372 .fuse = gf100_fuse_new, 1373 .gpio = g94_gpio_new, 1374 .i2c = g94_i2c_new, 1375 .ibus = gf100_ibus_new, 1376 .iccsense = gf100_iccsense_new, 1377 .imem = nv50_instmem_new, 1378 .ltc = gf100_ltc_new, 1379 .mc = gf100_mc_new, 1380 .mmu = gf100_mmu_new, 1381 .mxm = nv50_mxm_new, 1382 .pci = gf100_pci_new, 1383 .pmu = gf100_pmu_new, 1384 .therm = gt215_therm_new, 1385 .timer = nv41_timer_new, 1386 .volt = gf100_volt_new, 1387 .ce[0] = gf100_ce_new, 1388 .ce[1] = gf100_ce_new, 1389 .disp = gt215_disp_new, 1390 .dma = gf100_dma_new, 1391 .fifo = gf100_fifo_new, 1392 .gr = gf100_gr_new, 1393 .mspdec = gf100_mspdec_new, 1394 .msppp = gf100_msppp_new, 1395 .msvld = gf100_msvld_new, 1396 .pm = gf100_pm_new, 1397 .sw = gf100_sw_new, 1398 }; 1399 1400 static const struct nvkm_device_chip 1401 nvc1_chipset = { 1402 .name = "GF108", 1403 .bar = gf100_bar_new, 1404 .bios = nvkm_bios_new, 1405 .bus = gf100_bus_new, 1406 .clk = gf100_clk_new, 1407 .devinit = gf100_devinit_new, 1408 .fb = gf108_fb_new, 1409 .fuse = gf100_fuse_new, 1410 .gpio = g94_gpio_new, 1411 .i2c = g94_i2c_new, 1412 .ibus = gf100_ibus_new, 1413 .iccsense = gf100_iccsense_new, 1414 .imem = nv50_instmem_new, 1415 .ltc = gf100_ltc_new, 1416 .mc = gf100_mc_new, 1417 .mmu = gf100_mmu_new, 1418 .mxm = nv50_mxm_new, 1419 .pci = gf106_pci_new, 1420 .pmu = gf100_pmu_new, 1421 .therm = gt215_therm_new, 1422 .timer = nv41_timer_new, 1423 .volt = gf100_volt_new, 1424 .ce[0] = gf100_ce_new, 1425 .disp = gt215_disp_new, 1426 .dma = gf100_dma_new, 1427 .fifo = gf100_fifo_new, 1428 .gr = gf108_gr_new, 1429 .mspdec = gf100_mspdec_new, 1430 .msppp = gf100_msppp_new, 1431 .msvld = gf100_msvld_new, 1432 .pm = gf108_pm_new, 1433 .sw = gf100_sw_new, 1434 }; 1435 1436 static const struct nvkm_device_chip 1437 nvc3_chipset = { 1438 .name = "GF106", 1439 .bar = gf100_bar_new, 1440 .bios = nvkm_bios_new, 1441 .bus = gf100_bus_new, 1442 .clk = gf100_clk_new, 1443 .devinit = gf100_devinit_new, 1444 .fb = gf100_fb_new, 1445 .fuse = gf100_fuse_new, 1446 .gpio = g94_gpio_new, 1447 .i2c = g94_i2c_new, 1448 .ibus = gf100_ibus_new, 1449 .iccsense = gf100_iccsense_new, 1450 .imem = nv50_instmem_new, 1451 .ltc = gf100_ltc_new, 1452 .mc = gf100_mc_new, 1453 .mmu = gf100_mmu_new, 1454 .mxm = nv50_mxm_new, 1455 .pci = gf106_pci_new, 1456 .pmu = gf100_pmu_new, 1457 .therm = gt215_therm_new, 1458 .timer = nv41_timer_new, 1459 .volt = gf100_volt_new, 1460 .ce[0] = gf100_ce_new, 1461 .disp = gt215_disp_new, 1462 .dma = gf100_dma_new, 1463 .fifo = gf100_fifo_new, 1464 .gr = gf104_gr_new, 1465 .mspdec = gf100_mspdec_new, 1466 .msppp = gf100_msppp_new, 1467 .msvld = gf100_msvld_new, 1468 .pm = gf100_pm_new, 1469 .sw = gf100_sw_new, 1470 }; 1471 1472 static const struct nvkm_device_chip 1473 nvc4_chipset = { 1474 .name = "GF104", 1475 .bar = gf100_bar_new, 1476 .bios = nvkm_bios_new, 1477 .bus = gf100_bus_new, 1478 .clk = gf100_clk_new, 1479 .devinit = gf100_devinit_new, 1480 .fb = gf100_fb_new, 1481 .fuse = gf100_fuse_new, 1482 .gpio = g94_gpio_new, 1483 .i2c = g94_i2c_new, 1484 .ibus = gf100_ibus_new, 1485 .iccsense = gf100_iccsense_new, 1486 .imem = nv50_instmem_new, 1487 .ltc = gf100_ltc_new, 1488 .mc = gf100_mc_new, 1489 .mmu = gf100_mmu_new, 1490 .mxm = nv50_mxm_new, 1491 .pci = gf100_pci_new, 1492 .pmu = gf100_pmu_new, 1493 .therm = gt215_therm_new, 1494 .timer = nv41_timer_new, 1495 .volt = gf100_volt_new, 1496 .ce[0] = gf100_ce_new, 1497 .ce[1] = gf100_ce_new, 1498 .disp = gt215_disp_new, 1499 .dma = gf100_dma_new, 1500 .fifo = gf100_fifo_new, 1501 .gr = gf104_gr_new, 1502 .mspdec = gf100_mspdec_new, 1503 .msppp = gf100_msppp_new, 1504 .msvld = gf100_msvld_new, 1505 .pm = gf100_pm_new, 1506 .sw = gf100_sw_new, 1507 }; 1508 1509 static const struct nvkm_device_chip 1510 nvc8_chipset = { 1511 .name = "GF110", 1512 .bar = gf100_bar_new, 1513 .bios = nvkm_bios_new, 1514 .bus = gf100_bus_new, 1515 .clk = gf100_clk_new, 1516 .devinit = gf100_devinit_new, 1517 .fb = gf100_fb_new, 1518 .fuse = gf100_fuse_new, 1519 .gpio = g94_gpio_new, 1520 .i2c = g94_i2c_new, 1521 .ibus = gf100_ibus_new, 1522 .iccsense = gf100_iccsense_new, 1523 .imem = nv50_instmem_new, 1524 .ltc = gf100_ltc_new, 1525 .mc = gf100_mc_new, 1526 .mmu = gf100_mmu_new, 1527 .mxm = nv50_mxm_new, 1528 .pci = gf100_pci_new, 1529 .pmu = gf100_pmu_new, 1530 .therm = gt215_therm_new, 1531 .timer = nv41_timer_new, 1532 .volt = gf100_volt_new, 1533 .ce[0] = gf100_ce_new, 1534 .ce[1] = gf100_ce_new, 1535 .disp = gt215_disp_new, 1536 .dma = gf100_dma_new, 1537 .fifo = gf100_fifo_new, 1538 .gr = gf110_gr_new, 1539 .mspdec = gf100_mspdec_new, 1540 .msppp = gf100_msppp_new, 1541 .msvld = gf100_msvld_new, 1542 .pm = gf100_pm_new, 1543 .sw = gf100_sw_new, 1544 }; 1545 1546 static const struct nvkm_device_chip 1547 nvce_chipset = { 1548 .name = "GF114", 1549 .bar = gf100_bar_new, 1550 .bios = nvkm_bios_new, 1551 .bus = gf100_bus_new, 1552 .clk = gf100_clk_new, 1553 .devinit = gf100_devinit_new, 1554 .fb = gf100_fb_new, 1555 .fuse = gf100_fuse_new, 1556 .gpio = g94_gpio_new, 1557 .i2c = g94_i2c_new, 1558 .ibus = gf100_ibus_new, 1559 .iccsense = gf100_iccsense_new, 1560 .imem = nv50_instmem_new, 1561 .ltc = gf100_ltc_new, 1562 .mc = gf100_mc_new, 1563 .mmu = gf100_mmu_new, 1564 .mxm = nv50_mxm_new, 1565 .pci = gf100_pci_new, 1566 .pmu = gf100_pmu_new, 1567 .therm = gt215_therm_new, 1568 .timer = nv41_timer_new, 1569 .volt = gf100_volt_new, 1570 .ce[0] = gf100_ce_new, 1571 .ce[1] = gf100_ce_new, 1572 .disp = gt215_disp_new, 1573 .dma = gf100_dma_new, 1574 .fifo = gf100_fifo_new, 1575 .gr = gf104_gr_new, 1576 .mspdec = gf100_mspdec_new, 1577 .msppp = gf100_msppp_new, 1578 .msvld = gf100_msvld_new, 1579 .pm = gf100_pm_new, 1580 .sw = gf100_sw_new, 1581 }; 1582 1583 static const struct nvkm_device_chip 1584 nvcf_chipset = { 1585 .name = "GF116", 1586 .bar = gf100_bar_new, 1587 .bios = nvkm_bios_new, 1588 .bus = gf100_bus_new, 1589 .clk = gf100_clk_new, 1590 .devinit = gf100_devinit_new, 1591 .fb = gf100_fb_new, 1592 .fuse = gf100_fuse_new, 1593 .gpio = g94_gpio_new, 1594 .i2c = g94_i2c_new, 1595 .ibus = gf100_ibus_new, 1596 .iccsense = gf100_iccsense_new, 1597 .imem = nv50_instmem_new, 1598 .ltc = gf100_ltc_new, 1599 .mc = gf100_mc_new, 1600 .mmu = gf100_mmu_new, 1601 .mxm = nv50_mxm_new, 1602 .pci = gf106_pci_new, 1603 .pmu = gf100_pmu_new, 1604 .therm = gt215_therm_new, 1605 .timer = nv41_timer_new, 1606 .volt = gf100_volt_new, 1607 .ce[0] = gf100_ce_new, 1608 .disp = gt215_disp_new, 1609 .dma = gf100_dma_new, 1610 .fifo = gf100_fifo_new, 1611 .gr = gf104_gr_new, 1612 .mspdec = gf100_mspdec_new, 1613 .msppp = gf100_msppp_new, 1614 .msvld = gf100_msvld_new, 1615 .pm = gf100_pm_new, 1616 .sw = gf100_sw_new, 1617 }; 1618 1619 static const struct nvkm_device_chip 1620 nvd7_chipset = { 1621 .name = "GF117", 1622 .bar = gf100_bar_new, 1623 .bios = nvkm_bios_new, 1624 .bus = gf100_bus_new, 1625 .clk = gf100_clk_new, 1626 .devinit = gf100_devinit_new, 1627 .fb = gf100_fb_new, 1628 .fuse = gf100_fuse_new, 1629 .gpio = gf119_gpio_new, 1630 .i2c = gf117_i2c_new, 1631 .ibus = gf117_ibus_new, 1632 .iccsense = gf100_iccsense_new, 1633 .imem = nv50_instmem_new, 1634 .ltc = gf100_ltc_new, 1635 .mc = gf100_mc_new, 1636 .mmu = gf100_mmu_new, 1637 .mxm = nv50_mxm_new, 1638 .pci = gf106_pci_new, 1639 .therm = gf119_therm_new, 1640 .timer = nv41_timer_new, 1641 .volt = gf117_volt_new, 1642 .ce[0] = gf100_ce_new, 1643 .disp = gf119_disp_new, 1644 .dma = gf119_dma_new, 1645 .fifo = gf100_fifo_new, 1646 .gr = gf117_gr_new, 1647 .mspdec = gf100_mspdec_new, 1648 .msppp = gf100_msppp_new, 1649 .msvld = gf100_msvld_new, 1650 .pm = gf117_pm_new, 1651 .sw = gf100_sw_new, 1652 }; 1653 1654 static const struct nvkm_device_chip 1655 nvd9_chipset = { 1656 .name = "GF119", 1657 .bar = gf100_bar_new, 1658 .bios = nvkm_bios_new, 1659 .bus = gf100_bus_new, 1660 .clk = gf100_clk_new, 1661 .devinit = gf100_devinit_new, 1662 .fb = gf100_fb_new, 1663 .fuse = gf100_fuse_new, 1664 .gpio = gf119_gpio_new, 1665 .i2c = gf119_i2c_new, 1666 .ibus = gf117_ibus_new, 1667 .iccsense = gf100_iccsense_new, 1668 .imem = nv50_instmem_new, 1669 .ltc = gf100_ltc_new, 1670 .mc = gf100_mc_new, 1671 .mmu = gf100_mmu_new, 1672 .mxm = nv50_mxm_new, 1673 .pci = gf106_pci_new, 1674 .pmu = gf119_pmu_new, 1675 .therm = gf119_therm_new, 1676 .timer = nv41_timer_new, 1677 .volt = gf100_volt_new, 1678 .ce[0] = gf100_ce_new, 1679 .disp = gf119_disp_new, 1680 .dma = gf119_dma_new, 1681 .fifo = gf100_fifo_new, 1682 .gr = gf119_gr_new, 1683 .mspdec = gf100_mspdec_new, 1684 .msppp = gf100_msppp_new, 1685 .msvld = gf100_msvld_new, 1686 .pm = gf117_pm_new, 1687 .sw = gf100_sw_new, 1688 }; 1689 1690 static const struct nvkm_device_chip 1691 nve4_chipset = { 1692 .name = "GK104", 1693 .bar = gf100_bar_new, 1694 .bios = nvkm_bios_new, 1695 .bus = gf100_bus_new, 1696 .clk = gk104_clk_new, 1697 .devinit = gf100_devinit_new, 1698 .fb = gk104_fb_new, 1699 .fuse = gf100_fuse_new, 1700 .gpio = gk104_gpio_new, 1701 .i2c = gk104_i2c_new, 1702 .ibus = gk104_ibus_new, 1703 .iccsense = gf100_iccsense_new, 1704 .imem = nv50_instmem_new, 1705 .ltc = gk104_ltc_new, 1706 .mc = gk104_mc_new, 1707 .mmu = gk104_mmu_new, 1708 .mxm = nv50_mxm_new, 1709 .pci = gk104_pci_new, 1710 .pmu = gk104_pmu_new, 1711 .therm = gk104_therm_new, 1712 .timer = nv41_timer_new, 1713 .top = gk104_top_new, 1714 .volt = gk104_volt_new, 1715 .ce[0] = gk104_ce_new, 1716 .ce[1] = gk104_ce_new, 1717 .ce[2] = gk104_ce_new, 1718 .disp = gk104_disp_new, 1719 .dma = gf119_dma_new, 1720 .fifo = gk104_fifo_new, 1721 .gr = gk104_gr_new, 1722 .mspdec = gk104_mspdec_new, 1723 .msppp = gf100_msppp_new, 1724 .msvld = gk104_msvld_new, 1725 .pm = gk104_pm_new, 1726 .sw = gf100_sw_new, 1727 }; 1728 1729 static const struct nvkm_device_chip 1730 nve6_chipset = { 1731 .name = "GK106", 1732 .bar = gf100_bar_new, 1733 .bios = nvkm_bios_new, 1734 .bus = gf100_bus_new, 1735 .clk = gk104_clk_new, 1736 .devinit = gf100_devinit_new, 1737 .fb = gk104_fb_new, 1738 .fuse = gf100_fuse_new, 1739 .gpio = gk104_gpio_new, 1740 .i2c = gk104_i2c_new, 1741 .ibus = gk104_ibus_new, 1742 .iccsense = gf100_iccsense_new, 1743 .imem = nv50_instmem_new, 1744 .ltc = gk104_ltc_new, 1745 .mc = gk104_mc_new, 1746 .mmu = gk104_mmu_new, 1747 .mxm = nv50_mxm_new, 1748 .pci = gk104_pci_new, 1749 .pmu = gk104_pmu_new, 1750 .therm = gk104_therm_new, 1751 .timer = nv41_timer_new, 1752 .top = gk104_top_new, 1753 .volt = gk104_volt_new, 1754 .ce[0] = gk104_ce_new, 1755 .ce[1] = gk104_ce_new, 1756 .ce[2] = gk104_ce_new, 1757 .disp = gk104_disp_new, 1758 .dma = gf119_dma_new, 1759 .fifo = gk104_fifo_new, 1760 .gr = gk104_gr_new, 1761 .mspdec = gk104_mspdec_new, 1762 .msppp = gf100_msppp_new, 1763 .msvld = gk104_msvld_new, 1764 .pm = gk104_pm_new, 1765 .sw = gf100_sw_new, 1766 }; 1767 1768 static const struct nvkm_device_chip 1769 nve7_chipset = { 1770 .name = "GK107", 1771 .bar = gf100_bar_new, 1772 .bios = nvkm_bios_new, 1773 .bus = gf100_bus_new, 1774 .clk = gk104_clk_new, 1775 .devinit = gf100_devinit_new, 1776 .fb = gk104_fb_new, 1777 .fuse = gf100_fuse_new, 1778 .gpio = gk104_gpio_new, 1779 .i2c = gk104_i2c_new, 1780 .ibus = gk104_ibus_new, 1781 .iccsense = gf100_iccsense_new, 1782 .imem = nv50_instmem_new, 1783 .ltc = gk104_ltc_new, 1784 .mc = gk104_mc_new, 1785 .mmu = gk104_mmu_new, 1786 .mxm = nv50_mxm_new, 1787 .pci = gk104_pci_new, 1788 .pmu = gk104_pmu_new, 1789 .therm = gk104_therm_new, 1790 .timer = nv41_timer_new, 1791 .top = gk104_top_new, 1792 .volt = gk104_volt_new, 1793 .ce[0] = gk104_ce_new, 1794 .ce[1] = gk104_ce_new, 1795 .ce[2] = gk104_ce_new, 1796 .disp = gk104_disp_new, 1797 .dma = gf119_dma_new, 1798 .fifo = gk104_fifo_new, 1799 .gr = gk104_gr_new, 1800 .mspdec = gk104_mspdec_new, 1801 .msppp = gf100_msppp_new, 1802 .msvld = gk104_msvld_new, 1803 .pm = gk104_pm_new, 1804 .sw = gf100_sw_new, 1805 }; 1806 1807 static const struct nvkm_device_chip 1808 nvea_chipset = { 1809 .name = "GK20A", 1810 .bar = gk20a_bar_new, 1811 .bus = gf100_bus_new, 1812 .clk = gk20a_clk_new, 1813 .fb = gk20a_fb_new, 1814 .fuse = gf100_fuse_new, 1815 .ibus = gk20a_ibus_new, 1816 .imem = gk20a_instmem_new, 1817 .ltc = gk104_ltc_new, 1818 .mc = gk20a_mc_new, 1819 .mmu = gk20a_mmu_new, 1820 .pmu = gk20a_pmu_new, 1821 .timer = gk20a_timer_new, 1822 .top = gk104_top_new, 1823 .volt = gk20a_volt_new, 1824 .ce[2] = gk104_ce_new, 1825 .dma = gf119_dma_new, 1826 .fifo = gk20a_fifo_new, 1827 .gr = gk20a_gr_new, 1828 .pm = gk104_pm_new, 1829 .sw = gf100_sw_new, 1830 }; 1831 1832 static const struct nvkm_device_chip 1833 nvf0_chipset = { 1834 .name = "GK110", 1835 .bar = gf100_bar_new, 1836 .bios = nvkm_bios_new, 1837 .bus = gf100_bus_new, 1838 .clk = gk104_clk_new, 1839 .devinit = gf100_devinit_new, 1840 .fb = gk110_fb_new, 1841 .fuse = gf100_fuse_new, 1842 .gpio = gk104_gpio_new, 1843 .i2c = gk104_i2c_new, 1844 .ibus = gk104_ibus_new, 1845 .iccsense = gf100_iccsense_new, 1846 .imem = nv50_instmem_new, 1847 .ltc = gk104_ltc_new, 1848 .mc = gk104_mc_new, 1849 .mmu = gk104_mmu_new, 1850 .mxm = nv50_mxm_new, 1851 .pci = gk104_pci_new, 1852 .pmu = gk110_pmu_new, 1853 .therm = gk104_therm_new, 1854 .timer = nv41_timer_new, 1855 .top = gk104_top_new, 1856 .volt = gk104_volt_new, 1857 .ce[0] = gk104_ce_new, 1858 .ce[1] = gk104_ce_new, 1859 .ce[2] = gk104_ce_new, 1860 .disp = gk110_disp_new, 1861 .dma = gf119_dma_new, 1862 .fifo = gk110_fifo_new, 1863 .gr = gk110_gr_new, 1864 .mspdec = gk104_mspdec_new, 1865 .msppp = gf100_msppp_new, 1866 .msvld = gk104_msvld_new, 1867 .sw = gf100_sw_new, 1868 }; 1869 1870 static const struct nvkm_device_chip 1871 nvf1_chipset = { 1872 .name = "GK110B", 1873 .bar = gf100_bar_new, 1874 .bios = nvkm_bios_new, 1875 .bus = gf100_bus_new, 1876 .clk = gk104_clk_new, 1877 .devinit = gf100_devinit_new, 1878 .fb = gk110_fb_new, 1879 .fuse = gf100_fuse_new, 1880 .gpio = gk104_gpio_new, 1881 .i2c = gk104_i2c_new, 1882 .ibus = gk104_ibus_new, 1883 .iccsense = gf100_iccsense_new, 1884 .imem = nv50_instmem_new, 1885 .ltc = gk104_ltc_new, 1886 .mc = gk104_mc_new, 1887 .mmu = gk104_mmu_new, 1888 .mxm = nv50_mxm_new, 1889 .pci = gk104_pci_new, 1890 .pmu = gk110_pmu_new, 1891 .therm = gk104_therm_new, 1892 .timer = nv41_timer_new, 1893 .top = gk104_top_new, 1894 .volt = gk104_volt_new, 1895 .ce[0] = gk104_ce_new, 1896 .ce[1] = gk104_ce_new, 1897 .ce[2] = gk104_ce_new, 1898 .disp = gk110_disp_new, 1899 .dma = gf119_dma_new, 1900 .fifo = gk110_fifo_new, 1901 .gr = gk110b_gr_new, 1902 .mspdec = gk104_mspdec_new, 1903 .msppp = gf100_msppp_new, 1904 .msvld = gk104_msvld_new, 1905 .sw = gf100_sw_new, 1906 }; 1907 1908 static const struct nvkm_device_chip 1909 nv106_chipset = { 1910 .name = "GK208B", 1911 .bar = gf100_bar_new, 1912 .bios = nvkm_bios_new, 1913 .bus = gf100_bus_new, 1914 .clk = gk104_clk_new, 1915 .devinit = gf100_devinit_new, 1916 .fb = gk110_fb_new, 1917 .fuse = gf100_fuse_new, 1918 .gpio = gk104_gpio_new, 1919 .i2c = gk104_i2c_new, 1920 .ibus = gk104_ibus_new, 1921 .iccsense = gf100_iccsense_new, 1922 .imem = nv50_instmem_new, 1923 .ltc = gk104_ltc_new, 1924 .mc = gk20a_mc_new, 1925 .mmu = gk104_mmu_new, 1926 .mxm = nv50_mxm_new, 1927 .pci = gk104_pci_new, 1928 .pmu = gk208_pmu_new, 1929 .therm = gk104_therm_new, 1930 .timer = nv41_timer_new, 1931 .top = gk104_top_new, 1932 .volt = gk104_volt_new, 1933 .ce[0] = gk104_ce_new, 1934 .ce[1] = gk104_ce_new, 1935 .ce[2] = gk104_ce_new, 1936 .disp = gk110_disp_new, 1937 .dma = gf119_dma_new, 1938 .fifo = gk208_fifo_new, 1939 .gr = gk208_gr_new, 1940 .mspdec = gk104_mspdec_new, 1941 .msppp = gf100_msppp_new, 1942 .msvld = gk104_msvld_new, 1943 .sw = gf100_sw_new, 1944 }; 1945 1946 static const struct nvkm_device_chip 1947 nv108_chipset = { 1948 .name = "GK208", 1949 .bar = gf100_bar_new, 1950 .bios = nvkm_bios_new, 1951 .bus = gf100_bus_new, 1952 .clk = gk104_clk_new, 1953 .devinit = gf100_devinit_new, 1954 .fb = gk110_fb_new, 1955 .fuse = gf100_fuse_new, 1956 .gpio = gk104_gpio_new, 1957 .i2c = gk104_i2c_new, 1958 .ibus = gk104_ibus_new, 1959 .iccsense = gf100_iccsense_new, 1960 .imem = nv50_instmem_new, 1961 .ltc = gk104_ltc_new, 1962 .mc = gk20a_mc_new, 1963 .mmu = gk104_mmu_new, 1964 .mxm = nv50_mxm_new, 1965 .pci = gk104_pci_new, 1966 .pmu = gk208_pmu_new, 1967 .therm = gk104_therm_new, 1968 .timer = nv41_timer_new, 1969 .top = gk104_top_new, 1970 .volt = gk104_volt_new, 1971 .ce[0] = gk104_ce_new, 1972 .ce[1] = gk104_ce_new, 1973 .ce[2] = gk104_ce_new, 1974 .disp = gk110_disp_new, 1975 .dma = gf119_dma_new, 1976 .fifo = gk208_fifo_new, 1977 .gr = gk208_gr_new, 1978 .mspdec = gk104_mspdec_new, 1979 .msppp = gf100_msppp_new, 1980 .msvld = gk104_msvld_new, 1981 .sw = gf100_sw_new, 1982 }; 1983 1984 static const struct nvkm_device_chip 1985 nv117_chipset = { 1986 .name = "GM107", 1987 .bar = gm107_bar_new, 1988 .bios = nvkm_bios_new, 1989 .bus = gf100_bus_new, 1990 .clk = gk104_clk_new, 1991 .devinit = gm107_devinit_new, 1992 .fb = gm107_fb_new, 1993 .fuse = gm107_fuse_new, 1994 .gpio = gk104_gpio_new, 1995 .i2c = gk104_i2c_new, 1996 .ibus = gk104_ibus_new, 1997 .iccsense = gf100_iccsense_new, 1998 .imem = nv50_instmem_new, 1999 .ltc = gm107_ltc_new, 2000 .mc = gk20a_mc_new, 2001 .mmu = gk104_mmu_new, 2002 .mxm = nv50_mxm_new, 2003 .pci = gk104_pci_new, 2004 .pmu = gm107_pmu_new, 2005 .therm = gm107_therm_new, 2006 .timer = gk20a_timer_new, 2007 .top = gk104_top_new, 2008 .volt = gk104_volt_new, 2009 .ce[0] = gm107_ce_new, 2010 .ce[2] = gm107_ce_new, 2011 .disp = gm107_disp_new, 2012 .dma = gf119_dma_new, 2013 .fifo = gm107_fifo_new, 2014 .gr = gm107_gr_new, 2015 .nvdec[0] = gm107_nvdec_new, 2016 .nvenc[0] = gm107_nvenc_new, 2017 .sw = gf100_sw_new, 2018 }; 2019 2020 static const struct nvkm_device_chip 2021 nv118_chipset = { 2022 .name = "GM108", 2023 .bar = gm107_bar_new, 2024 .bios = nvkm_bios_new, 2025 .bus = gf100_bus_new, 2026 .clk = gk104_clk_new, 2027 .devinit = gm107_devinit_new, 2028 .fb = gm107_fb_new, 2029 .fuse = gm107_fuse_new, 2030 .gpio = gk104_gpio_new, 2031 .i2c = gk104_i2c_new, 2032 .ibus = gk104_ibus_new, 2033 .iccsense = gf100_iccsense_new, 2034 .imem = nv50_instmem_new, 2035 .ltc = gm107_ltc_new, 2036 .mc = gk20a_mc_new, 2037 .mmu = gk104_mmu_new, 2038 .mxm = nv50_mxm_new, 2039 .pci = gk104_pci_new, 2040 .pmu = gm107_pmu_new, 2041 .therm = gm107_therm_new, 2042 .timer = gk20a_timer_new, 2043 .top = gk104_top_new, 2044 .volt = gk104_volt_new, 2045 .ce[0] = gm107_ce_new, 2046 .ce[2] = gm107_ce_new, 2047 .disp = gm107_disp_new, 2048 .dma = gf119_dma_new, 2049 .fifo = gm107_fifo_new, 2050 .gr = gm107_gr_new, 2051 .sw = gf100_sw_new, 2052 }; 2053 2054 static const struct nvkm_device_chip 2055 nv120_chipset = { 2056 .name = "GM200", 2057 .acr = gm200_acr_new, 2058 .bar = gm107_bar_new, 2059 .bios = nvkm_bios_new, 2060 .bus = gf100_bus_new, 2061 .devinit = gm200_devinit_new, 2062 .fb = gm200_fb_new, 2063 .fuse = gm107_fuse_new, 2064 .gpio = gk104_gpio_new, 2065 .i2c = gm200_i2c_new, 2066 .ibus = gm200_ibus_new, 2067 .iccsense = gf100_iccsense_new, 2068 .imem = nv50_instmem_new, 2069 .ltc = gm200_ltc_new, 2070 .mc = gk20a_mc_new, 2071 .mmu = gm200_mmu_new, 2072 .mxm = nv50_mxm_new, 2073 .pci = gk104_pci_new, 2074 .pmu = gm107_pmu_new, 2075 .therm = gm200_therm_new, 2076 .timer = gk20a_timer_new, 2077 .top = gk104_top_new, 2078 .volt = gk104_volt_new, 2079 .ce[0] = gm200_ce_new, 2080 .ce[1] = gm200_ce_new, 2081 .ce[2] = gm200_ce_new, 2082 .disp = gm200_disp_new, 2083 .dma = gf119_dma_new, 2084 .fifo = gm200_fifo_new, 2085 .gr = gm200_gr_new, 2086 .nvdec[0] = gm107_nvdec_new, 2087 .nvenc[0] = gm107_nvenc_new, 2088 .nvenc[1] = gm107_nvenc_new, 2089 .sw = gf100_sw_new, 2090 }; 2091 2092 static const struct nvkm_device_chip 2093 nv124_chipset = { 2094 .name = "GM204", 2095 .acr = gm200_acr_new, 2096 .bar = gm107_bar_new, 2097 .bios = nvkm_bios_new, 2098 .bus = gf100_bus_new, 2099 .devinit = gm200_devinit_new, 2100 .fb = gm200_fb_new, 2101 .fuse = gm107_fuse_new, 2102 .gpio = gk104_gpio_new, 2103 .i2c = gm200_i2c_new, 2104 .ibus = gm200_ibus_new, 2105 .iccsense = gf100_iccsense_new, 2106 .imem = nv50_instmem_new, 2107 .ltc = gm200_ltc_new, 2108 .mc = gk20a_mc_new, 2109 .mmu = gm200_mmu_new, 2110 .mxm = nv50_mxm_new, 2111 .pci = gk104_pci_new, 2112 .pmu = gm107_pmu_new, 2113 .therm = gm200_therm_new, 2114 .timer = gk20a_timer_new, 2115 .top = gk104_top_new, 2116 .volt = gk104_volt_new, 2117 .ce[0] = gm200_ce_new, 2118 .ce[1] = gm200_ce_new, 2119 .ce[2] = gm200_ce_new, 2120 .disp = gm200_disp_new, 2121 .dma = gf119_dma_new, 2122 .fifo = gm200_fifo_new, 2123 .gr = gm200_gr_new, 2124 .nvdec[0] = gm107_nvdec_new, 2125 .nvenc[0] = gm107_nvenc_new, 2126 .nvenc[1] = gm107_nvenc_new, 2127 .sw = gf100_sw_new, 2128 }; 2129 2130 static const struct nvkm_device_chip 2131 nv126_chipset = { 2132 .name = "GM206", 2133 .acr = gm200_acr_new, 2134 .bar = gm107_bar_new, 2135 .bios = nvkm_bios_new, 2136 .bus = gf100_bus_new, 2137 .devinit = gm200_devinit_new, 2138 .fb = gm200_fb_new, 2139 .fuse = gm107_fuse_new, 2140 .gpio = gk104_gpio_new, 2141 .i2c = gm200_i2c_new, 2142 .ibus = gm200_ibus_new, 2143 .iccsense = gf100_iccsense_new, 2144 .imem = nv50_instmem_new, 2145 .ltc = gm200_ltc_new, 2146 .mc = gk20a_mc_new, 2147 .mmu = gm200_mmu_new, 2148 .mxm = nv50_mxm_new, 2149 .pci = gk104_pci_new, 2150 .pmu = gm107_pmu_new, 2151 .therm = gm200_therm_new, 2152 .timer = gk20a_timer_new, 2153 .top = gk104_top_new, 2154 .volt = gk104_volt_new, 2155 .ce[0] = gm200_ce_new, 2156 .ce[1] = gm200_ce_new, 2157 .ce[2] = gm200_ce_new, 2158 .disp = gm200_disp_new, 2159 .dma = gf119_dma_new, 2160 .fifo = gm200_fifo_new, 2161 .gr = gm200_gr_new, 2162 .nvdec[0] = gm107_nvdec_new, 2163 .nvenc[0] = gm107_nvenc_new, 2164 .sw = gf100_sw_new, 2165 }; 2166 2167 static const struct nvkm_device_chip 2168 nv12b_chipset = { 2169 .name = "GM20B", 2170 .acr = gm20b_acr_new, 2171 .bar = gm20b_bar_new, 2172 .bus = gf100_bus_new, 2173 .clk = gm20b_clk_new, 2174 .fb = gm20b_fb_new, 2175 .fuse = gm107_fuse_new, 2176 .ibus = gk20a_ibus_new, 2177 .imem = gk20a_instmem_new, 2178 .ltc = gm200_ltc_new, 2179 .mc = gk20a_mc_new, 2180 .mmu = gm20b_mmu_new, 2181 .pmu = gm20b_pmu_new, 2182 .timer = gk20a_timer_new, 2183 .top = gk104_top_new, 2184 .ce[2] = gm200_ce_new, 2185 .volt = gm20b_volt_new, 2186 .dma = gf119_dma_new, 2187 .fifo = gm20b_fifo_new, 2188 .gr = gm20b_gr_new, 2189 .sw = gf100_sw_new, 2190 }; 2191 2192 static const struct nvkm_device_chip 2193 nv130_chipset = { 2194 .name = "GP100", 2195 .acr = gm200_acr_new, 2196 .bar = gm107_bar_new, 2197 .bios = nvkm_bios_new, 2198 .bus = gf100_bus_new, 2199 .devinit = gm200_devinit_new, 2200 .fault = gp100_fault_new, 2201 .fb = gp100_fb_new, 2202 .fuse = gm107_fuse_new, 2203 .gpio = gk104_gpio_new, 2204 .i2c = gm200_i2c_new, 2205 .ibus = gm200_ibus_new, 2206 .imem = nv50_instmem_new, 2207 .ltc = gp100_ltc_new, 2208 .mc = gp100_mc_new, 2209 .mmu = gp100_mmu_new, 2210 .therm = gp100_therm_new, 2211 .pci = gp100_pci_new, 2212 .pmu = gp100_pmu_new, 2213 .timer = gk20a_timer_new, 2214 .top = gk104_top_new, 2215 .ce[0] = gp100_ce_new, 2216 .ce[1] = gp100_ce_new, 2217 .ce[2] = gp100_ce_new, 2218 .ce[3] = gp100_ce_new, 2219 .ce[4] = gp100_ce_new, 2220 .ce[5] = gp100_ce_new, 2221 .dma = gf119_dma_new, 2222 .disp = gp100_disp_new, 2223 .fifo = gp100_fifo_new, 2224 .gr = gp100_gr_new, 2225 .nvdec[0] = gm107_nvdec_new, 2226 .nvenc[0] = gm107_nvenc_new, 2227 .nvenc[1] = gm107_nvenc_new, 2228 .nvenc[2] = gm107_nvenc_new, 2229 .sw = gf100_sw_new, 2230 }; 2231 2232 static const struct nvkm_device_chip 2233 nv132_chipset = { 2234 .name = "GP102", 2235 .acr = gp102_acr_new, 2236 .bar = gm107_bar_new, 2237 .bios = nvkm_bios_new, 2238 .bus = gf100_bus_new, 2239 .devinit = gm200_devinit_new, 2240 .fault = gp100_fault_new, 2241 .fb = gp102_fb_new, 2242 .fuse = gm107_fuse_new, 2243 .gpio = gk104_gpio_new, 2244 .i2c = gm200_i2c_new, 2245 .ibus = gm200_ibus_new, 2246 .imem = nv50_instmem_new, 2247 .ltc = gp102_ltc_new, 2248 .mc = gp100_mc_new, 2249 .mmu = gp100_mmu_new, 2250 .therm = gp100_therm_new, 2251 .pci = gp100_pci_new, 2252 .pmu = gp102_pmu_new, 2253 .timer = gk20a_timer_new, 2254 .top = gk104_top_new, 2255 .ce[0] = gp102_ce_new, 2256 .ce[1] = gp102_ce_new, 2257 .ce[2] = gp102_ce_new, 2258 .ce[3] = gp102_ce_new, 2259 .disp = gp102_disp_new, 2260 .dma = gf119_dma_new, 2261 .fifo = gp100_fifo_new, 2262 .gr = gp102_gr_new, 2263 .nvdec[0] = gm107_nvdec_new, 2264 .nvenc[0] = gm107_nvenc_new, 2265 .nvenc[1] = gm107_nvenc_new, 2266 .sec2 = gp102_sec2_new, 2267 .sw = gf100_sw_new, 2268 }; 2269 2270 static const struct nvkm_device_chip 2271 nv134_chipset = { 2272 .name = "GP104", 2273 .acr = gp102_acr_new, 2274 .bar = gm107_bar_new, 2275 .bios = nvkm_bios_new, 2276 .bus = gf100_bus_new, 2277 .devinit = gm200_devinit_new, 2278 .fault = gp100_fault_new, 2279 .fb = gp102_fb_new, 2280 .fuse = gm107_fuse_new, 2281 .gpio = gk104_gpio_new, 2282 .i2c = gm200_i2c_new, 2283 .ibus = gm200_ibus_new, 2284 .imem = nv50_instmem_new, 2285 .ltc = gp102_ltc_new, 2286 .mc = gp100_mc_new, 2287 .mmu = gp100_mmu_new, 2288 .therm = gp100_therm_new, 2289 .pci = gp100_pci_new, 2290 .pmu = gp102_pmu_new, 2291 .timer = gk20a_timer_new, 2292 .top = gk104_top_new, 2293 .ce[0] = gp102_ce_new, 2294 .ce[1] = gp102_ce_new, 2295 .ce[2] = gp102_ce_new, 2296 .ce[3] = gp102_ce_new, 2297 .disp = gp102_disp_new, 2298 .dma = gf119_dma_new, 2299 .fifo = gp100_fifo_new, 2300 .gr = gp104_gr_new, 2301 .nvdec[0] = gm107_nvdec_new, 2302 .nvenc[0] = gm107_nvenc_new, 2303 .nvenc[1] = gm107_nvenc_new, 2304 .sec2 = gp102_sec2_new, 2305 .sw = gf100_sw_new, 2306 }; 2307 2308 static const struct nvkm_device_chip 2309 nv136_chipset = { 2310 .name = "GP106", 2311 .acr = gp102_acr_new, 2312 .bar = gm107_bar_new, 2313 .bios = nvkm_bios_new, 2314 .bus = gf100_bus_new, 2315 .devinit = gm200_devinit_new, 2316 .fault = gp100_fault_new, 2317 .fb = gp102_fb_new, 2318 .fuse = gm107_fuse_new, 2319 .gpio = gk104_gpio_new, 2320 .i2c = gm200_i2c_new, 2321 .ibus = gm200_ibus_new, 2322 .imem = nv50_instmem_new, 2323 .ltc = gp102_ltc_new, 2324 .mc = gp100_mc_new, 2325 .mmu = gp100_mmu_new, 2326 .therm = gp100_therm_new, 2327 .pci = gp100_pci_new, 2328 .pmu = gp102_pmu_new, 2329 .timer = gk20a_timer_new, 2330 .top = gk104_top_new, 2331 .ce[0] = gp102_ce_new, 2332 .ce[1] = gp102_ce_new, 2333 .ce[2] = gp102_ce_new, 2334 .ce[3] = gp102_ce_new, 2335 .disp = gp102_disp_new, 2336 .dma = gf119_dma_new, 2337 .fifo = gp100_fifo_new, 2338 .gr = gp104_gr_new, 2339 .nvdec[0] = gm107_nvdec_new, 2340 .nvenc[0] = gm107_nvenc_new, 2341 .sec2 = gp102_sec2_new, 2342 .sw = gf100_sw_new, 2343 }; 2344 2345 static const struct nvkm_device_chip 2346 nv137_chipset = { 2347 .name = "GP107", 2348 .acr = gp102_acr_new, 2349 .bar = gm107_bar_new, 2350 .bios = nvkm_bios_new, 2351 .bus = gf100_bus_new, 2352 .devinit = gm200_devinit_new, 2353 .fault = gp100_fault_new, 2354 .fb = gp102_fb_new, 2355 .fuse = gm107_fuse_new, 2356 .gpio = gk104_gpio_new, 2357 .i2c = gm200_i2c_new, 2358 .ibus = gm200_ibus_new, 2359 .imem = nv50_instmem_new, 2360 .ltc = gp102_ltc_new, 2361 .mc = gp100_mc_new, 2362 .mmu = gp100_mmu_new, 2363 .therm = gp100_therm_new, 2364 .pci = gp100_pci_new, 2365 .pmu = gp102_pmu_new, 2366 .timer = gk20a_timer_new, 2367 .top = gk104_top_new, 2368 .ce[0] = gp102_ce_new, 2369 .ce[1] = gp102_ce_new, 2370 .ce[2] = gp102_ce_new, 2371 .ce[3] = gp102_ce_new, 2372 .disp = gp102_disp_new, 2373 .dma = gf119_dma_new, 2374 .fifo = gp100_fifo_new, 2375 .gr = gp107_gr_new, 2376 .nvdec[0] = gm107_nvdec_new, 2377 .nvenc[0] = gm107_nvenc_new, 2378 .nvenc[1] = gm107_nvenc_new, 2379 .sec2 = gp102_sec2_new, 2380 .sw = gf100_sw_new, 2381 }; 2382 2383 static const struct nvkm_device_chip 2384 nv138_chipset = { 2385 .name = "GP108", 2386 .acr = gp108_acr_new, 2387 .bar = gm107_bar_new, 2388 .bios = nvkm_bios_new, 2389 .bus = gf100_bus_new, 2390 .devinit = gm200_devinit_new, 2391 .fault = gp100_fault_new, 2392 .fb = gp102_fb_new, 2393 .fuse = gm107_fuse_new, 2394 .gpio = gk104_gpio_new, 2395 .i2c = gm200_i2c_new, 2396 .ibus = gm200_ibus_new, 2397 .imem = nv50_instmem_new, 2398 .ltc = gp102_ltc_new, 2399 .mc = gp100_mc_new, 2400 .mmu = gp100_mmu_new, 2401 .therm = gp100_therm_new, 2402 .pci = gp100_pci_new, 2403 .pmu = gp102_pmu_new, 2404 .timer = gk20a_timer_new, 2405 .top = gk104_top_new, 2406 .ce[0] = gp102_ce_new, 2407 .ce[1] = gp102_ce_new, 2408 .ce[2] = gp102_ce_new, 2409 .ce[3] = gp102_ce_new, 2410 .disp = gp102_disp_new, 2411 .dma = gf119_dma_new, 2412 .fifo = gp100_fifo_new, 2413 .gr = gp108_gr_new, 2414 .nvdec[0] = gm107_nvdec_new, 2415 .sec2 = gp108_sec2_new, 2416 .sw = gf100_sw_new, 2417 }; 2418 2419 static const struct nvkm_device_chip 2420 nv13b_chipset = { 2421 .name = "GP10B", 2422 .acr = gp10b_acr_new, 2423 .bar = gm20b_bar_new, 2424 .bus = gf100_bus_new, 2425 .fault = gp10b_fault_new, 2426 .fb = gp10b_fb_new, 2427 .fuse = gm107_fuse_new, 2428 .ibus = gp10b_ibus_new, 2429 .imem = gk20a_instmem_new, 2430 .ltc = gp10b_ltc_new, 2431 .mc = gp10b_mc_new, 2432 .mmu = gp10b_mmu_new, 2433 .pmu = gp10b_pmu_new, 2434 .timer = gk20a_timer_new, 2435 .top = gk104_top_new, 2436 .ce[0] = gp100_ce_new, 2437 .dma = gf119_dma_new, 2438 .fifo = gp10b_fifo_new, 2439 .gr = gp10b_gr_new, 2440 .sw = gf100_sw_new, 2441 }; 2442 2443 static const struct nvkm_device_chip 2444 nv140_chipset = { 2445 .name = "GV100", 2446 .acr = gp108_acr_new, 2447 .bar = gm107_bar_new, 2448 .bios = nvkm_bios_new, 2449 .bus = gf100_bus_new, 2450 .devinit = gv100_devinit_new, 2451 .fault = gv100_fault_new, 2452 .fb = gv100_fb_new, 2453 .fuse = gm107_fuse_new, 2454 .gpio = gk104_gpio_new, 2455 .gsp = gv100_gsp_new, 2456 .i2c = gm200_i2c_new, 2457 .ibus = gm200_ibus_new, 2458 .imem = nv50_instmem_new, 2459 .ltc = gp102_ltc_new, 2460 .mc = gp100_mc_new, 2461 .mmu = gv100_mmu_new, 2462 .pci = gp100_pci_new, 2463 .pmu = gp102_pmu_new, 2464 .therm = gp100_therm_new, 2465 .timer = gk20a_timer_new, 2466 .top = gk104_top_new, 2467 .disp = gv100_disp_new, 2468 .ce[0] = gv100_ce_new, 2469 .ce[1] = gv100_ce_new, 2470 .ce[2] = gv100_ce_new, 2471 .ce[3] = gv100_ce_new, 2472 .ce[4] = gv100_ce_new, 2473 .ce[5] = gv100_ce_new, 2474 .ce[6] = gv100_ce_new, 2475 .ce[7] = gv100_ce_new, 2476 .ce[8] = gv100_ce_new, 2477 .dma = gv100_dma_new, 2478 .fifo = gv100_fifo_new, 2479 .gr = gv100_gr_new, 2480 .nvdec[0] = gm107_nvdec_new, 2481 .nvenc[0] = gm107_nvenc_new, 2482 .nvenc[1] = gm107_nvenc_new, 2483 .nvenc[2] = gm107_nvenc_new, 2484 .sec2 = gp108_sec2_new, 2485 }; 2486 2487 static const struct nvkm_device_chip 2488 nv162_chipset = { 2489 .name = "TU102", 2490 .acr = tu102_acr_new, 2491 .bar = tu102_bar_new, 2492 .bios = nvkm_bios_new, 2493 .bus = gf100_bus_new, 2494 .devinit = tu102_devinit_new, 2495 .fault = tu102_fault_new, 2496 .fb = gv100_fb_new, 2497 .fuse = gm107_fuse_new, 2498 .gpio = gk104_gpio_new, 2499 .gsp = gv100_gsp_new, 2500 .i2c = gm200_i2c_new, 2501 .ibus = gm200_ibus_new, 2502 .imem = nv50_instmem_new, 2503 .ltc = gp102_ltc_new, 2504 .mc = tu102_mc_new, 2505 .mmu = tu102_mmu_new, 2506 .pci = gp100_pci_new, 2507 .pmu = gp102_pmu_new, 2508 .therm = gp100_therm_new, 2509 .timer = gk20a_timer_new, 2510 .top = gk104_top_new, 2511 .ce[0] = tu102_ce_new, 2512 .ce[1] = tu102_ce_new, 2513 .ce[2] = tu102_ce_new, 2514 .ce[3] = tu102_ce_new, 2515 .ce[4] = tu102_ce_new, 2516 .disp = tu102_disp_new, 2517 .dma = gv100_dma_new, 2518 .fifo = tu102_fifo_new, 2519 .gr = tu102_gr_new, 2520 .nvdec[0] = gm107_nvdec_new, 2521 .nvenc[0] = gm107_nvenc_new, 2522 .sec2 = tu102_sec2_new, 2523 }; 2524 2525 static const struct nvkm_device_chip 2526 nv164_chipset = { 2527 .name = "TU104", 2528 .acr = tu102_acr_new, 2529 .bar = tu102_bar_new, 2530 .bios = nvkm_bios_new, 2531 .bus = gf100_bus_new, 2532 .devinit = tu102_devinit_new, 2533 .fault = tu102_fault_new, 2534 .fb = gv100_fb_new, 2535 .fuse = gm107_fuse_new, 2536 .gpio = gk104_gpio_new, 2537 .gsp = gv100_gsp_new, 2538 .i2c = gm200_i2c_new, 2539 .ibus = gm200_ibus_new, 2540 .imem = nv50_instmem_new, 2541 .ltc = gp102_ltc_new, 2542 .mc = tu102_mc_new, 2543 .mmu = tu102_mmu_new, 2544 .pci = gp100_pci_new, 2545 .pmu = gp102_pmu_new, 2546 .therm = gp100_therm_new, 2547 .timer = gk20a_timer_new, 2548 .top = gk104_top_new, 2549 .ce[0] = tu102_ce_new, 2550 .ce[1] = tu102_ce_new, 2551 .ce[2] = tu102_ce_new, 2552 .ce[3] = tu102_ce_new, 2553 .ce[4] = tu102_ce_new, 2554 .disp = tu102_disp_new, 2555 .dma = gv100_dma_new, 2556 .fifo = tu102_fifo_new, 2557 .gr = tu102_gr_new, 2558 .nvdec[0] = gm107_nvdec_new, 2559 .nvdec[1] = gm107_nvdec_new, 2560 .nvenc[0] = gm107_nvenc_new, 2561 .sec2 = tu102_sec2_new, 2562 }; 2563 2564 static const struct nvkm_device_chip 2565 nv166_chipset = { 2566 .name = "TU106", 2567 .acr = tu102_acr_new, 2568 .bar = tu102_bar_new, 2569 .bios = nvkm_bios_new, 2570 .bus = gf100_bus_new, 2571 .devinit = tu102_devinit_new, 2572 .fault = tu102_fault_new, 2573 .fb = gv100_fb_new, 2574 .fuse = gm107_fuse_new, 2575 .gpio = gk104_gpio_new, 2576 .gsp = gv100_gsp_new, 2577 .i2c = gm200_i2c_new, 2578 .ibus = gm200_ibus_new, 2579 .imem = nv50_instmem_new, 2580 .ltc = gp102_ltc_new, 2581 .mc = tu102_mc_new, 2582 .mmu = tu102_mmu_new, 2583 .pci = gp100_pci_new, 2584 .pmu = gp102_pmu_new, 2585 .therm = gp100_therm_new, 2586 .timer = gk20a_timer_new, 2587 .top = gk104_top_new, 2588 .ce[0] = tu102_ce_new, 2589 .ce[1] = tu102_ce_new, 2590 .ce[2] = tu102_ce_new, 2591 .ce[3] = tu102_ce_new, 2592 .ce[4] = tu102_ce_new, 2593 .disp = tu102_disp_new, 2594 .dma = gv100_dma_new, 2595 .fifo = tu102_fifo_new, 2596 .gr = tu102_gr_new, 2597 .nvdec[0] = gm107_nvdec_new, 2598 .nvdec[1] = gm107_nvdec_new, 2599 .nvdec[2] = gm107_nvdec_new, 2600 .nvenc[0] = gm107_nvenc_new, 2601 .sec2 = tu102_sec2_new, 2602 }; 2603 2604 static const struct nvkm_device_chip 2605 nv167_chipset = { 2606 .name = "TU117", 2607 .acr = tu102_acr_new, 2608 .bar = tu102_bar_new, 2609 .bios = nvkm_bios_new, 2610 .bus = gf100_bus_new, 2611 .devinit = tu102_devinit_new, 2612 .fault = tu102_fault_new, 2613 .fb = gv100_fb_new, 2614 .fuse = gm107_fuse_new, 2615 .gpio = gk104_gpio_new, 2616 .gsp = gv100_gsp_new, 2617 .i2c = gm200_i2c_new, 2618 .ibus = gm200_ibus_new, 2619 .imem = nv50_instmem_new, 2620 .ltc = gp102_ltc_new, 2621 .mc = tu102_mc_new, 2622 .mmu = tu102_mmu_new, 2623 .pci = gp100_pci_new, 2624 .pmu = gp102_pmu_new, 2625 .therm = gp100_therm_new, 2626 .timer = gk20a_timer_new, 2627 .top = gk104_top_new, 2628 .ce[0] = tu102_ce_new, 2629 .ce[1] = tu102_ce_new, 2630 .ce[2] = tu102_ce_new, 2631 .ce[3] = tu102_ce_new, 2632 .ce[4] = tu102_ce_new, 2633 .disp = tu102_disp_new, 2634 .dma = gv100_dma_new, 2635 .fifo = tu102_fifo_new, 2636 .gr = tu102_gr_new, 2637 .nvdec[0] = gm107_nvdec_new, 2638 .nvenc[0] = gm107_nvenc_new, 2639 .sec2 = tu102_sec2_new, 2640 }; 2641 2642 static const struct nvkm_device_chip 2643 nv168_chipset = { 2644 .name = "TU116", 2645 .acr = tu102_acr_new, 2646 .bar = tu102_bar_new, 2647 .bios = nvkm_bios_new, 2648 .bus = gf100_bus_new, 2649 .devinit = tu102_devinit_new, 2650 .fault = tu102_fault_new, 2651 .fb = gv100_fb_new, 2652 .fuse = gm107_fuse_new, 2653 .gpio = gk104_gpio_new, 2654 .gsp = gv100_gsp_new, 2655 .i2c = gm200_i2c_new, 2656 .ibus = gm200_ibus_new, 2657 .imem = nv50_instmem_new, 2658 .ltc = gp102_ltc_new, 2659 .mc = tu102_mc_new, 2660 .mmu = tu102_mmu_new, 2661 .pci = gp100_pci_new, 2662 .pmu = gp102_pmu_new, 2663 .therm = gp100_therm_new, 2664 .timer = gk20a_timer_new, 2665 .top = gk104_top_new, 2666 .ce[0] = tu102_ce_new, 2667 .ce[1] = tu102_ce_new, 2668 .ce[2] = tu102_ce_new, 2669 .ce[3] = tu102_ce_new, 2670 .ce[4] = tu102_ce_new, 2671 .disp = tu102_disp_new, 2672 .dma = gv100_dma_new, 2673 .fifo = tu102_fifo_new, 2674 .gr = tu102_gr_new, 2675 .nvdec[0] = gm107_nvdec_new, 2676 .nvenc[0] = gm107_nvenc_new, 2677 .sec2 = tu102_sec2_new, 2678 }; 2679 2680 static int 2681 nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, 2682 struct nvkm_notify *notify) 2683 { 2684 if (!WARN_ON(size != 0)) { 2685 notify->size = 0; 2686 notify->types = 1; 2687 notify->index = 0; 2688 return 0; 2689 } 2690 return -EINVAL; 2691 } 2692 2693 static const struct nvkm_event_func 2694 nvkm_device_event_func = { 2695 .ctor = nvkm_device_event_ctor, 2696 }; 2697 2698 struct nvkm_subdev * 2699 nvkm_device_subdev(struct nvkm_device *device, int index) 2700 { 2701 struct nvkm_engine *engine; 2702 2703 if (device->disable_mask & (1ULL << index)) 2704 return NULL; 2705 2706 switch (index) { 2707 #define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break 2708 _(ACR , device->acr , &device->acr->subdev); 2709 _(BAR , device->bar , &device->bar->subdev); 2710 _(VBIOS , device->bios , &device->bios->subdev); 2711 _(BUS , device->bus , &device->bus->subdev); 2712 _(CLK , device->clk , &device->clk->subdev); 2713 _(DEVINIT , device->devinit , &device->devinit->subdev); 2714 _(FAULT , device->fault , &device->fault->subdev); 2715 _(FB , device->fb , &device->fb->subdev); 2716 _(FUSE , device->fuse , &device->fuse->subdev); 2717 _(GPIO , device->gpio , &device->gpio->subdev); 2718 _(GSP , device->gsp , &device->gsp->subdev); 2719 _(I2C , device->i2c , &device->i2c->subdev); 2720 _(IBUS , device->ibus , device->ibus); 2721 _(ICCSENSE, device->iccsense, &device->iccsense->subdev); 2722 _(INSTMEM , device->imem , &device->imem->subdev); 2723 _(LTC , device->ltc , &device->ltc->subdev); 2724 _(MC , device->mc , &device->mc->subdev); 2725 _(MMU , device->mmu , &device->mmu->subdev); 2726 _(MXM , device->mxm , device->mxm); 2727 _(PCI , device->pci , &device->pci->subdev); 2728 _(PMU , device->pmu , &device->pmu->subdev); 2729 _(THERM , device->therm , &device->therm->subdev); 2730 _(TIMER , device->timer , &device->timer->subdev); 2731 _(TOP , device->top , &device->top->subdev); 2732 _(VOLT , device->volt , &device->volt->subdev); 2733 #undef _ 2734 default: 2735 engine = nvkm_device_engine(device, index); 2736 if (engine) 2737 return &engine->subdev; 2738 break; 2739 } 2740 return NULL; 2741 } 2742 2743 struct nvkm_engine * 2744 nvkm_device_engine(struct nvkm_device *device, int index) 2745 { 2746 if (device->disable_mask & (1ULL << index)) 2747 return NULL; 2748 2749 switch (index) { 2750 #define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break 2751 _(BSP , device->bsp , device->bsp); 2752 _(CE0 , device->ce[0] , device->ce[0]); 2753 _(CE1 , device->ce[1] , device->ce[1]); 2754 _(CE2 , device->ce[2] , device->ce[2]); 2755 _(CE3 , device->ce[3] , device->ce[3]); 2756 _(CE4 , device->ce[4] , device->ce[4]); 2757 _(CE5 , device->ce[5] , device->ce[5]); 2758 _(CE6 , device->ce[6] , device->ce[6]); 2759 _(CE7 , device->ce[7] , device->ce[7]); 2760 _(CE8 , device->ce[8] , device->ce[8]); 2761 _(CIPHER , device->cipher , device->cipher); 2762 _(DISP , device->disp , &device->disp->engine); 2763 _(DMAOBJ , device->dma , &device->dma->engine); 2764 _(FIFO , device->fifo , &device->fifo->engine); 2765 _(GR , device->gr , &device->gr->engine); 2766 _(IFB , device->ifb , device->ifb); 2767 _(ME , device->me , device->me); 2768 _(MPEG , device->mpeg , device->mpeg); 2769 _(MSENC , device->msenc , device->msenc); 2770 _(MSPDEC , device->mspdec , device->mspdec); 2771 _(MSPPP , device->msppp , device->msppp); 2772 _(MSVLD , device->msvld , device->msvld); 2773 _(NVENC0 , device->nvenc[0], &device->nvenc[0]->engine); 2774 _(NVENC1 , device->nvenc[1], &device->nvenc[1]->engine); 2775 _(NVENC2 , device->nvenc[2], &device->nvenc[2]->engine); 2776 _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine); 2777 _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine); 2778 _(NVDEC2 , device->nvdec[2], &device->nvdec[2]->engine); 2779 _(PM , device->pm , &device->pm->engine); 2780 _(SEC , device->sec , device->sec); 2781 _(SEC2 , device->sec2 , &device->sec2->engine); 2782 _(SW , device->sw , &device->sw->engine); 2783 _(VIC , device->vic , device->vic); 2784 _(VP , device->vp , device->vp); 2785 #undef _ 2786 default: 2787 WARN_ON(1); 2788 break; 2789 } 2790 return NULL; 2791 } 2792 2793 int 2794 nvkm_device_fini(struct nvkm_device *device, bool suspend) 2795 { 2796 const char *action = suspend ? "suspend" : "fini"; 2797 struct nvkm_subdev *subdev; 2798 int ret, i; 2799 s64 time; 2800 2801 nvdev_trace(device, "%s running...\n", action); 2802 time = ktime_to_us(ktime_get()); 2803 2804 nvkm_acpi_fini(device); 2805 2806 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2807 if ((subdev = nvkm_device_subdev(device, i))) { 2808 ret = nvkm_subdev_fini(subdev, suspend); 2809 if (ret && suspend) 2810 goto fail; 2811 } 2812 } 2813 2814 nvkm_therm_clkgate_fini(device->therm, suspend); 2815 2816 if (device->func->fini) 2817 device->func->fini(device, suspend); 2818 2819 time = ktime_to_us(ktime_get()) - time; 2820 nvdev_trace(device, "%s completed in %"PRId64"us...\n", action, time); 2821 return 0; 2822 2823 fail: 2824 do { 2825 if ((subdev = nvkm_device_subdev(device, i))) { 2826 int rret = nvkm_subdev_init(subdev); 2827 if (rret) 2828 nvkm_fatal(subdev, "failed restart, %d\n", ret); 2829 } 2830 } while (++i < NVKM_SUBDEV_NR); 2831 2832 nvdev_trace(device, "%s failed with %d\n", action, ret); 2833 return ret; 2834 } 2835 2836 static int 2837 nvkm_device_preinit(struct nvkm_device *device) 2838 { 2839 struct nvkm_subdev *subdev; 2840 int ret, i; 2841 s64 time; 2842 2843 nvdev_trace(device, "preinit running...\n"); 2844 time = ktime_to_us(ktime_get()); 2845 2846 if (device->func->preinit) { 2847 ret = device->func->preinit(device); 2848 if (ret) 2849 goto fail; 2850 } 2851 2852 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2853 if ((subdev = nvkm_device_subdev(device, i))) { 2854 ret = nvkm_subdev_preinit(subdev); 2855 if (ret) 2856 goto fail; 2857 } 2858 } 2859 2860 ret = nvkm_devinit_post(device->devinit, &device->disable_mask); 2861 if (ret) 2862 goto fail; 2863 2864 time = ktime_to_us(ktime_get()) - time; 2865 nvdev_trace(device, "preinit completed in %"PRId64"us\n", time); 2866 return 0; 2867 2868 fail: 2869 nvdev_error(device, "preinit failed with %d\n", ret); 2870 return ret; 2871 } 2872 2873 int 2874 nvkm_device_init(struct nvkm_device *device) 2875 { 2876 struct nvkm_subdev *subdev; 2877 int ret, i; 2878 s64 time; 2879 2880 ret = nvkm_device_preinit(device); 2881 if (ret) 2882 return ret; 2883 2884 nvkm_device_fini(device, false); 2885 2886 nvdev_trace(device, "init running...\n"); 2887 time = ktime_to_us(ktime_get()); 2888 2889 if (device->func->init) { 2890 ret = device->func->init(device); 2891 if (ret) 2892 goto fail; 2893 } 2894 2895 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2896 if ((subdev = nvkm_device_subdev(device, i))) { 2897 ret = nvkm_subdev_init(subdev); 2898 if (ret) 2899 goto fail_subdev; 2900 } 2901 } 2902 2903 nvkm_acpi_init(device); 2904 nvkm_therm_clkgate_enable(device->therm); 2905 2906 time = ktime_to_us(ktime_get()) - time; 2907 nvdev_trace(device, "init completed in %"PRId64"us\n", time); 2908 return 0; 2909 2910 fail_subdev: 2911 do { 2912 if ((subdev = nvkm_device_subdev(device, i))) 2913 nvkm_subdev_fini(subdev, false); 2914 } while (--i >= 0); 2915 2916 fail: 2917 nvkm_device_fini(device, false); 2918 2919 nvdev_error(device, "init failed with %d\n", ret); 2920 return ret; 2921 } 2922 2923 void 2924 nvkm_device_del(struct nvkm_device **pdevice) 2925 { 2926 struct nvkm_device *device = *pdevice; 2927 int i; 2928 if (device) { 2929 mutex_lock(&nv_devices_mutex); 2930 device->disable_mask = 0; 2931 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2932 struct nvkm_subdev *subdev = 2933 nvkm_device_subdev(device, i); 2934 nvkm_subdev_del(&subdev); 2935 } 2936 2937 mutex_destroy(&device->mutex); 2938 2939 nvkm_event_fini(&device->event); 2940 2941 #ifdef __NetBSD__ 2942 if (device->mmiosz) 2943 bus_space_unmap(device->mmiot, device->mmioh, 2944 device->mmiosz); 2945 #else 2946 if (device->pri) 2947 iounmap(device->pri); 2948 #endif 2949 list_del(&device->head); 2950 2951 if (device->func->dtor) 2952 *pdevice = device->func->dtor(device); 2953 mutex_unlock(&nv_devices_mutex); 2954 2955 kfree(*pdevice); 2956 *pdevice = NULL; 2957 } 2958 } 2959 2960 int 2961 nvkm_device_ctor(const struct nvkm_device_func *func, 2962 const struct nvkm_device_quirk *quirk, 2963 struct device *dev, enum nvkm_device_type type, u64 handle, 2964 #ifdef __NetBSD__ /* XXX nouveau acpi */ 2965 struct acpi_devnode *acpidev, 2966 #endif 2967 const char *name, const char *cfg, const char *dbg, 2968 bool detect, bool mmio, u64 subdev_mask, 2969 struct nvkm_device *device) 2970 { 2971 struct nvkm_subdev *subdev; 2972 u64 mmio_base, mmio_size; 2973 u32 boot0, strap; 2974 #ifdef __NetBSD__ 2975 bus_space_tag_t mmiot; 2976 bus_space_handle_t mmioh; 2977 #else 2978 void __iomem *map; 2979 #endif 2980 int ret = -EEXIST, i; 2981 unsigned chipset; 2982 2983 mutex_lock(&nv_devices_mutex); 2984 if (nvkm_device_find_locked(handle)) 2985 goto done; 2986 2987 device->func = func; 2988 device->quirk = quirk; 2989 device->dev = dev; 2990 device->type = type; 2991 device->handle = handle; 2992 #ifdef __NetBSD__ /* XXX nouveau acpi */ 2993 device->acpidev = acpidev; 2994 #endif 2995 device->cfgopt = cfg; 2996 device->dbgopt = dbg; 2997 device->name = name; 2998 list_add_tail(&device->head, &nv_devices); 2999 device->debug = nvkm_dbgopt(device->dbgopt, "device"); 3000 3001 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); 3002 if (ret) 3003 goto done; 3004 3005 #ifdef __NetBSD__ 3006 mmiot = device->func->resource_tag(device, 0); 3007 #endif 3008 mmio_base = device->func->resource_addr(device, 0); 3009 mmio_size = device->func->resource_size(device, 0); 3010 3011 /* identify the chipset, and determine classes of subdev/engines */ 3012 if (detect) { 3013 #ifdef __NetBSD__ 3014 if (mmio_size < 0x102000) { 3015 ret = -ENOMEM; 3016 goto done; 3017 } 3018 /* XXX errno NetBSD->Linux */ 3019 ret = -bus_space_map(mmiot, mmio_base, 0x102000, 0, &mmioh); 3020 if (ret) 3021 goto done; 3022 #ifndef __BIG_ENDIAN 3023 if (bus_space_read_stream_4(mmiot, mmioh, 4) != 0) 3024 #else 3025 if (bus_space_read_stream_4(mmiot, mmioh, 4) == 0) 3026 #endif 3027 { 3028 bus_space_write_stream_4(mmiot, mmioh, 4, 0x01000001); 3029 bus_space_read_stream_4(mmiot, mmioh, 0); 3030 } 3031 3032 /* read boot0 and strapping information */ 3033 boot0 = bus_space_read_stream_4(mmiot, mmioh, 0x000000); 3034 strap = bus_space_read_stream_4(mmiot, mmioh, 0x101000); 3035 bus_space_unmap(mmiot, mmioh, 0x102000); 3036 #else 3037 map = ioremap(mmio_base, 0x102000); 3038 if (ret = -ENOMEM, map == NULL) 3039 goto done; 3040 3041 /* switch mmio to cpu's native endianness */ 3042 #ifndef __BIG_ENDIAN 3043 if (ioread32_native(map + 0x000004) != 0x00000000) { 3044 #else 3045 if (ioread32_native(map + 0x000004) == 0x00000000) { 3046 #endif 3047 iowrite32_native(0x01000001, map + 0x000004); 3048 ioread32_native(map); 3049 } 3050 3051 /* read boot0 and strapping information */ 3052 boot0 = ioread32_native(map + 0x000000); 3053 strap = ioread32_native(map + 0x101000); 3054 iounmap(map); 3055 #endif 3056 3057 /* chipset can be overridden for devel/testing purposes */ 3058 chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); 3059 if (chipset) { 3060 u32 override_boot0; 3061 3062 if (chipset >= 0x10) { 3063 override_boot0 = ((chipset & 0x1ff) << 20); 3064 override_boot0 |= 0x000000a1; 3065 } else { 3066 if (chipset != 0x04) 3067 override_boot0 = 0x20104000; 3068 else 3069 override_boot0 = 0x20004000; 3070 } 3071 3072 nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n", 3073 boot0, override_boot0); 3074 boot0 = override_boot0; 3075 } 3076 3077 /* determine chipset and derive architecture from it */ 3078 if ((boot0 & 0x1f000000) > 0) { 3079 device->chipset = (boot0 & 0x1ff00000) >> 20; 3080 device->chiprev = (boot0 & 0x000000ff); 3081 switch (device->chipset & 0x1f0) { 3082 case 0x010: { 3083 if (0x461 & (1 << (device->chipset & 0xf))) 3084 device->card_type = NV_10; 3085 else 3086 device->card_type = NV_11; 3087 device->chiprev = 0x00; 3088 break; 3089 } 3090 case 0x020: device->card_type = NV_20; break; 3091 case 0x030: device->card_type = NV_30; break; 3092 case 0x040: 3093 case 0x060: device->card_type = NV_40; break; 3094 case 0x050: 3095 case 0x080: 3096 case 0x090: 3097 case 0x0a0: device->card_type = NV_50; break; 3098 case 0x0c0: 3099 case 0x0d0: device->card_type = NV_C0; break; 3100 case 0x0e0: 3101 case 0x0f0: 3102 case 0x100: device->card_type = NV_E0; break; 3103 case 0x110: 3104 case 0x120: device->card_type = GM100; break; 3105 case 0x130: device->card_type = GP100; break; 3106 case 0x140: device->card_type = GV100; break; 3107 case 0x160: device->card_type = TU100; break; 3108 default: 3109 break; 3110 } 3111 } else 3112 if ((boot0 & 0xff00fff0) == 0x20004000) { 3113 if (boot0 & 0x00f00000) 3114 device->chipset = 0x05; 3115 else 3116 device->chipset = 0x04; 3117 device->card_type = NV_04; 3118 } 3119 3120 switch (device->chipset) { 3121 case 0x004: device->chip = &nv4_chipset; break; 3122 case 0x005: device->chip = &nv5_chipset; break; 3123 case 0x010: device->chip = &nv10_chipset; break; 3124 case 0x011: device->chip = &nv11_chipset; break; 3125 case 0x015: device->chip = &nv15_chipset; break; 3126 case 0x017: device->chip = &nv17_chipset; break; 3127 case 0x018: device->chip = &nv18_chipset; break; 3128 case 0x01a: device->chip = &nv1a_chipset; break; 3129 case 0x01f: device->chip = &nv1f_chipset; break; 3130 case 0x020: device->chip = &nv20_chipset; break; 3131 case 0x025: device->chip = &nv25_chipset; break; 3132 case 0x028: device->chip = &nv28_chipset; break; 3133 case 0x02a: device->chip = &nv2a_chipset; break; 3134 case 0x030: device->chip = &nv30_chipset; break; 3135 case 0x031: device->chip = &nv31_chipset; break; 3136 case 0x034: device->chip = &nv34_chipset; break; 3137 case 0x035: device->chip = &nv35_chipset; break; 3138 case 0x036: device->chip = &nv36_chipset; break; 3139 case 0x040: device->chip = &nv40_chipset; break; 3140 case 0x041: device->chip = &nv41_chipset; break; 3141 case 0x042: device->chip = &nv42_chipset; break; 3142 case 0x043: device->chip = &nv43_chipset; break; 3143 case 0x044: device->chip = &nv44_chipset; break; 3144 case 0x045: device->chip = &nv45_chipset; break; 3145 case 0x046: device->chip = &nv46_chipset; break; 3146 case 0x047: device->chip = &nv47_chipset; break; 3147 case 0x049: device->chip = &nv49_chipset; break; 3148 case 0x04a: device->chip = &nv4a_chipset; break; 3149 case 0x04b: device->chip = &nv4b_chipset; break; 3150 case 0x04c: device->chip = &nv4c_chipset; break; 3151 case 0x04e: device->chip = &nv4e_chipset; break; 3152 case 0x050: device->chip = &nv50_chipset; break; 3153 case 0x063: device->chip = &nv63_chipset; break; 3154 case 0x067: device->chip = &nv67_chipset; break; 3155 case 0x068: device->chip = &nv68_chipset; break; 3156 case 0x084: device->chip = &nv84_chipset; break; 3157 case 0x086: device->chip = &nv86_chipset; break; 3158 case 0x092: device->chip = &nv92_chipset; break; 3159 case 0x094: device->chip = &nv94_chipset; break; 3160 case 0x096: device->chip = &nv96_chipset; break; 3161 case 0x098: device->chip = &nv98_chipset; break; 3162 case 0x0a0: device->chip = &nva0_chipset; break; 3163 case 0x0a3: device->chip = &nva3_chipset; break; 3164 case 0x0a5: device->chip = &nva5_chipset; break; 3165 case 0x0a8: device->chip = &nva8_chipset; break; 3166 case 0x0aa: device->chip = &nvaa_chipset; break; 3167 case 0x0ac: device->chip = &nvac_chipset; break; 3168 case 0x0af: device->chip = &nvaf_chipset; break; 3169 case 0x0c0: device->chip = &nvc0_chipset; break; 3170 case 0x0c1: device->chip = &nvc1_chipset; break; 3171 case 0x0c3: device->chip = &nvc3_chipset; break; 3172 case 0x0c4: device->chip = &nvc4_chipset; break; 3173 case 0x0c8: device->chip = &nvc8_chipset; break; 3174 case 0x0ce: device->chip = &nvce_chipset; break; 3175 case 0x0cf: device->chip = &nvcf_chipset; break; 3176 case 0x0d7: device->chip = &nvd7_chipset; break; 3177 case 0x0d9: device->chip = &nvd9_chipset; break; 3178 case 0x0e4: device->chip = &nve4_chipset; break; 3179 case 0x0e6: device->chip = &nve6_chipset; break; 3180 case 0x0e7: device->chip = &nve7_chipset; break; 3181 case 0x0ea: device->chip = &nvea_chipset; break; 3182 case 0x0f0: device->chip = &nvf0_chipset; break; 3183 case 0x0f1: device->chip = &nvf1_chipset; break; 3184 case 0x106: device->chip = &nv106_chipset; break; 3185 case 0x108: device->chip = &nv108_chipset; break; 3186 case 0x117: device->chip = &nv117_chipset; break; 3187 case 0x118: device->chip = &nv118_chipset; break; 3188 case 0x120: device->chip = &nv120_chipset; break; 3189 case 0x124: device->chip = &nv124_chipset; break; 3190 case 0x126: device->chip = &nv126_chipset; break; 3191 case 0x12b: device->chip = &nv12b_chipset; break; 3192 case 0x130: device->chip = &nv130_chipset; break; 3193 case 0x132: device->chip = &nv132_chipset; break; 3194 case 0x134: device->chip = &nv134_chipset; break; 3195 case 0x136: device->chip = &nv136_chipset; break; 3196 case 0x137: device->chip = &nv137_chipset; break; 3197 case 0x138: device->chip = &nv138_chipset; break; 3198 case 0x13b: device->chip = &nv13b_chipset; break; 3199 case 0x140: device->chip = &nv140_chipset; break; 3200 case 0x162: device->chip = &nv162_chipset; break; 3201 case 0x164: device->chip = &nv164_chipset; break; 3202 case 0x166: device->chip = &nv166_chipset; break; 3203 case 0x167: device->chip = &nv167_chipset; break; 3204 case 0x168: device->chip = &nv168_chipset; break; 3205 default: 3206 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 3207 goto done; 3208 } 3209 3210 nvdev_info(device, "NVIDIA %s (%08x)\n", 3211 device->chip->name, boot0); 3212 3213 /* determine frequency of timing crystal */ 3214 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 3215 (device->chipset >= 0x20 && device->chipset < 0x25)) 3216 strap &= 0x00000040; 3217 else 3218 strap &= 0x00400040; 3219 3220 switch (strap) { 3221 case 0x00000000: device->crystal = 13500; break; 3222 case 0x00000040: device->crystal = 14318; break; 3223 case 0x00400000: device->crystal = 27000; break; 3224 case 0x00400040: device->crystal = 25000; break; 3225 } 3226 } else { 3227 device->chip = &null_chipset; 3228 } 3229 3230 if (!device->name) 3231 device->name = device->chip->name; 3232 3233 if (mmio) { 3234 #ifdef __NetBSD__ 3235 /* XXX errno NetBSD->Linux */ 3236 ret = -bus_space_map(mmiot, mmio_base, mmio_size, 3237 BUS_SPACE_MAP_LINEAR, &mmioh); 3238 if (ret) { 3239 nvdev_error(device, "unable to map device registers\n"); 3240 goto done; /* XXX Linux leaks mutex */ 3241 } 3242 device->mmiot = mmiot; 3243 device->mmioh = mmioh; 3244 device->mmioaddr = mmio_base; 3245 device->mmiosz = mmio_size; 3246 #else 3247 device->pri = ioremap(mmio_base, mmio_size); 3248 if (!device->pri) { 3249 nvdev_error(device, "unable to map PRI\n"); 3250 ret = -ENOMEM; 3251 goto done; 3252 } 3253 #endif 3254 } 3255 3256 mutex_init(&device->mutex); 3257 3258 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 3259 #define _(s,m) case s: \ 3260 if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ 3261 ret = device->chip->m(device, (s), &device->m); \ 3262 if (ret) { \ 3263 subdev = nvkm_device_subdev(device, (s)); \ 3264 nvkm_subdev_del(&subdev); \ 3265 device->m = NULL; \ 3266 if (ret != -ENODEV) { \ 3267 nvdev_error(device, "%s ctor failed, %d\n", \ 3268 nvkm_subdev_name[s], ret); \ 3269 goto done; \ 3270 } \ 3271 } \ 3272 } \ 3273 break 3274 switch (i) { 3275 _(NVKM_SUBDEV_ACR , acr); 3276 _(NVKM_SUBDEV_BAR , bar); 3277 _(NVKM_SUBDEV_VBIOS , bios); 3278 _(NVKM_SUBDEV_BUS , bus); 3279 _(NVKM_SUBDEV_CLK , clk); 3280 _(NVKM_SUBDEV_DEVINIT , devinit); 3281 _(NVKM_SUBDEV_FAULT , fault); 3282 _(NVKM_SUBDEV_FB , fb); 3283 _(NVKM_SUBDEV_FUSE , fuse); 3284 _(NVKM_SUBDEV_GPIO , gpio); 3285 _(NVKM_SUBDEV_GSP , gsp); 3286 _(NVKM_SUBDEV_I2C , i2c); 3287 _(NVKM_SUBDEV_IBUS , ibus); 3288 _(NVKM_SUBDEV_ICCSENSE, iccsense); 3289 _(NVKM_SUBDEV_INSTMEM , imem); 3290 _(NVKM_SUBDEV_LTC , ltc); 3291 _(NVKM_SUBDEV_MC , mc); 3292 _(NVKM_SUBDEV_MMU , mmu); 3293 _(NVKM_SUBDEV_MXM , mxm); 3294 _(NVKM_SUBDEV_PCI , pci); 3295 _(NVKM_SUBDEV_PMU , pmu); 3296 _(NVKM_SUBDEV_THERM , therm); 3297 _(NVKM_SUBDEV_TIMER , timer); 3298 _(NVKM_SUBDEV_TOP , top); 3299 _(NVKM_SUBDEV_VOLT , volt); 3300 _(NVKM_ENGINE_BSP , bsp); 3301 _(NVKM_ENGINE_CE0 , ce[0]); 3302 _(NVKM_ENGINE_CE1 , ce[1]); 3303 _(NVKM_ENGINE_CE2 , ce[2]); 3304 _(NVKM_ENGINE_CE3 , ce[3]); 3305 _(NVKM_ENGINE_CE4 , ce[4]); 3306 _(NVKM_ENGINE_CE5 , ce[5]); 3307 _(NVKM_ENGINE_CE6 , ce[6]); 3308 _(NVKM_ENGINE_CE7 , ce[7]); 3309 _(NVKM_ENGINE_CE8 , ce[8]); 3310 _(NVKM_ENGINE_CIPHER , cipher); 3311 _(NVKM_ENGINE_DISP , disp); 3312 _(NVKM_ENGINE_DMAOBJ , dma); 3313 _(NVKM_ENGINE_FIFO , fifo); 3314 _(NVKM_ENGINE_GR , gr); 3315 _(NVKM_ENGINE_IFB , ifb); 3316 _(NVKM_ENGINE_ME , me); 3317 _(NVKM_ENGINE_MPEG , mpeg); 3318 _(NVKM_ENGINE_MSENC , msenc); 3319 _(NVKM_ENGINE_MSPDEC , mspdec); 3320 _(NVKM_ENGINE_MSPPP , msppp); 3321 _(NVKM_ENGINE_MSVLD , msvld); 3322 _(NVKM_ENGINE_NVENC0 , nvenc[0]); 3323 _(NVKM_ENGINE_NVENC1 , nvenc[1]); 3324 _(NVKM_ENGINE_NVENC2 , nvenc[2]); 3325 _(NVKM_ENGINE_NVDEC0 , nvdec[0]); 3326 _(NVKM_ENGINE_NVDEC1 , nvdec[1]); 3327 _(NVKM_ENGINE_NVDEC2 , nvdec[2]); 3328 _(NVKM_ENGINE_PM , pm); 3329 _(NVKM_ENGINE_SEC , sec); 3330 _(NVKM_ENGINE_SEC2 , sec2); 3331 _(NVKM_ENGINE_SW , sw); 3332 _(NVKM_ENGINE_VIC , vic); 3333 _(NVKM_ENGINE_VP , vp); 3334 default: 3335 WARN_ON(1); 3336 continue; 3337 } 3338 #undef _ 3339 } 3340 3341 ret = 0; 3342 done: 3343 mutex_unlock(&nv_devices_mutex); 3344 return ret; 3345 } 3346
Indexes created Sat Sep 20 22:09:52 GMT 2025