1 /* $NetBSD: obio.c,v 1.16 2023/07/14 12:57:10 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003, 2005 Genetec corp. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corp. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corp. may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/kernel.h> 37 #include <sys/reboot.h> 38 #include <sys/bitops.h> 39 40 #include <machine/cpu.h> 41 #include <sys/bus.h> 42 #include <machine/intr.h> 43 #include <arm/cpufunc.h> 44 45 #include <arm/mainbus/mainbus.h> 46 #include <arm/xscale/pxa2x0cpu.h> 47 #include <arm/xscale/pxa2x0reg.h> 48 #include <arm/xscale/pxa2x0var.h> 49 #include <arm/xscale/pxa2x0_gpio.h> 50 #include <arm/sa11x0/sa11x0_var.h> 51 #include <evbarm/g42xxeb/g42xxeb_reg.h> 52 #include <evbarm/g42xxeb/g42xxeb_var.h> 53 54 #include "locators.h" 55 56 /* prototypes */ 57 static int obio_match(device_t, cfdata_t, void *); 58 static void obio_attach(device_t, device_t, void *); 59 static int obio_search(device_t, cfdata_t, const int *, void *); 60 static int obio_print(void *, const char *); 61 62 /* attach structures */ 63 CFATTACH_DECL_NEW(obio, sizeof(struct obio_softc), obio_match, obio_attach, 64 NULL, NULL); 65 66 static int 67 obio_spurious(void *arg) 68 { 69 int irqno = (int)arg; 70 71 printf("Spurious interrupt %d on On-board peripheral", irqno); 72 return 1; 73 } 74 75 76 /* 77 * interrupt handler for GPIO0 (on-board peripherals) 78 * 79 * On G4250ebx, 10 interrupts are ORed through on-board logic, 80 * and routed to GPIO0 of PXA250 processor. 81 */ 82 static int 83 obio_intr(void *arg) 84 { 85 int irqno, pending; 86 struct obio_softc *sc = (struct obio_softc *)arg; 87 int n=0; 88 89 #define get_pending(sc) \ 90 (bus_space_read_2( sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTSTS1) \ 91 & ~(sc->sc_intr_pending|sc->sc_intr_mask)) 92 93 #ifdef DEBUG 94 printf("obio_intr: pend=%x, mask=%x, pend=%x, mask=%x\n", 95 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTSTS1), 96 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTMASK), 97 sc->sc_intr_pending, 98 sc->sc_intr_mask); 99 #endif 100 101 for (pending = get_pending(sc); 102 (irqno = fls32(pending) - 1) >= 0; 103 pending = get_pending(sc)) { 104 105 /* reset pending bit */ 106 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 107 G42XXEB_INTSTS1, ~(1<<irqno)); 108 109 #if 0 110 if (sc->sc_handler[irqno].level > saved_spl_level) { 111 int spl_save = _splraise(sc->sc_handler[irqno].level); 112 (* sc->sc_handler[irqno].func)( 113 sc->sc_handler[irqno].arg); 114 splx(spl_save); 115 } 116 else 117 #endif 118 { 119 int psw = disable_interrupts(I32_bit); /* XXX */ 120 121 /* mask this interrupt until software 122 interrupt is handled. */ 123 sc->sc_intr_pending |= (1U<<irqno); 124 obio_update_intrmask(sc); 125 126 restore_interrupts(psw); 127 ++n; 128 } 129 #ifdef DIAGNOSTIC 130 if (n > 1000) 131 panic("obio_intr: stayed too long"); 132 #endif 133 } 134 135 if (n > 0) { 136 /* handle it later */ 137 softint_schedule(sc->sc_si); 138 } 139 140 /* GPIO interrupt is edge triggered. make a pulse 141 to let Cotulla notice when other interrupts are 142 still pending */ 143 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 144 G42XXEB_INTMASK, 0xffff); 145 obio_update_intrmask(sc); 146 147 return 1; 148 } 149 150 static void 151 obio_softint(void *arg) 152 { 153 struct obio_softc *sc = (struct obio_softc *)arg; 154 int irqno; 155 int spl_save = curcpl(); 156 int psw; 157 158 psw = disable_interrupts(I32_bit); 159 while ((irqno = fls32(sc->sc_intr_pending) - 1) >= 0) { 160 sc->sc_intr_pending &= ~(1U<<irqno); 161 162 restore_interrupts(psw); 163 164 _splraise(sc->sc_handler[irqno].level); 165 (* sc->sc_handler[irqno].func)( 166 sc->sc_handler[irqno].arg); 167 splx(spl_save); 168 169 psw = disable_interrupts(I32_bit); 170 } 171 172 /* assert(sc->sc_intr_pending==0) */ 173 174 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 175 G42XXEB_INTMASK, 0xffff); 176 obio_update_intrmask(sc); 177 178 restore_interrupts(psw); 179 } 180 181 /* 182 * int obio_print(void *aux, const char *name) 183 * print configuration info for children 184 */ 185 186 static int 187 obio_print(void *aux, const char *name) 188 { 189 struct obio_attach_args *oba = (struct obio_attach_args*)aux; 190 191 if (oba->oba_addr != OBIOCF_ADDR_DEFAULT) 192 aprint_normal(" addr 0x%lx", oba->oba_addr); 193 if (oba->oba_intr > 0) 194 aprint_normal(" intr %d", oba->oba_intr); 195 return (UNCONF); 196 } 197 198 int 199 obio_match(device_t parent, cfdata_t match, void *aux) 200 { 201 return 1; 202 } 203 204 void 205 obio_attach(device_t parent, device_t self, void *aux) 206 { 207 struct obio_softc *sc = device_private(self); 208 struct sa11x0_attach_args *sa = aux; 209 bus_space_tag_t iot = sa->sa_iot; 210 int i; 211 uint16_t reg; 212 213 sc->sc_dev = self; 214 215 /* tweak memory access timing for CS3. 216 the value set by redboot is too slow */ 217 if (bus_space_map(iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, 218 &sc->sc_memctl_ioh)) 219 goto fail; 220 bus_space_write_4(iot, sc->sc_memctl_ioh, MEMCTL_MSC1, 221 (0xffff & bus_space_read_4(iot, sc->sc_memctl_ioh, MEMCTL_MSC1)) 222 | (0x6888 << 16)); 223 224 /* Map on-board FPGA registers */ 225 sc->sc_iot = iot; 226 if (bus_space_map(iot, G42XXEB_PLDREG_BASE, G42XXEB_PLDREG_SIZE, 227 0, &(sc->sc_obioreg_ioh))) 228 goto fail; 229 230 /* 231 * Mask all interrupts. 232 * They are later unmasked at each device's attach routine. 233 */ 234 sc->sc_intr_mask = 0xffff; 235 bus_space_write_2(iot, sc->sc_obioreg_ioh, G42XXEB_INTMASK, 236 sc->sc_intr_mask ); 237 238 #if 0 239 sc->sc_intr = 8; /* GPIO0 */ 240 #endif 241 sc->sc_intr_pending = 0; 242 243 for (i=0; i < G42XXEB_N_INTS; ++i) { 244 sc->sc_handler[i].func = obio_spurious; 245 sc->sc_handler[i].arg = (void *)i; 246 } 247 248 obio_peripheral_reset(sc, 1, 0); 249 250 /* 251 * establish interrupt handler. 252 * level is very high to allow high priority sub-interrupts. 253 */ 254 sc->sc_ipl = IPL_AUDIO; 255 sc->sc_ih = pxa2x0_gpio_intr_establish(0, IST_EDGE_FALLING, sc->sc_ipl, 256 obio_intr, sc); 257 sc->sc_si = softint_establish(SOFTINT_NET, obio_softint, sc); 258 259 reg = bus_space_read_2(iot, sc->sc_obioreg_ioh, G42XXEB_PLDVER); 260 aprint_normal(": board %d version %x\n", reg>>8, reg & 0xff); 261 262 /* 263 * Attach each devices 264 */ 265 config_search(self, NULL, 266 CFARGS(.search = obio_search)); 267 return; 268 269 fail: 270 aprint_error_dev(self, "can't map FPGA registers\n"); 271 } 272 273 int 274 obio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 275 { 276 struct obio_softc *sc = device_private(parent); 277 struct obio_attach_args oba; 278 279 oba.oba_sc = sc; 280 oba.oba_iot = sc->sc_iot; 281 oba.oba_addr = cf->cf_loc[OBIOCF_ADDR]; 282 oba.oba_intr = cf->cf_loc[OBIOCF_INTR]; 283 284 if (config_probe(parent, cf, &oba)) 285 config_attach(parent, cf, &oba, obio_print, CFARGS_NONE); 286 287 return 0; 288 } 289 290 void * 291 obio_intr_establish(struct obio_softc *sc, int irq, int ipl, 292 int type, int (*func)(void *), void *arg) 293 { 294 int save; 295 int regidx, sft; 296 uint16_t reg; 297 static const uint8_t ist_code[] = { 298 0, 299 G42XXEB_INT_EDGE_FALLING, /* pulse */ 300 G42XXEB_INT_EDGE_FALLING, /* IST_EDGE */ 301 G42XXEB_INT_LEVEL_LOW, /* IST_LEVEL */ 302 G42XXEB_INT_LEVEL_HIGH, /* IST_LEVEL_HIGH */ 303 G42XXEB_INT_EDGE_RISING, /* IST_EDGE_RISING */ 304 G42XXEB_INT_EDGE_BOTH, /* IST_EDGE_BOTH */ 305 }; 306 307 if (irq < 0 || G42XXEB_N_INTS <= irq) 308 panic("Bad irq no. for obio (%d)", irq); 309 310 if (type < 0 || IST_EDGE_BOTH < type) 311 panic("Bad interrupt type for obio (%d)", type); 312 313 regidx = G42XXEB_INTCNTL; 314 sft = 3 * irq; 315 if (irq >= 5) { 316 regidx = G42XXEB_INTCNTH; 317 sft -= 3*5; 318 } 319 320 save = disable_interrupts(I32_bit); 321 322 sc->sc_handler[irq].func = func; 323 sc->sc_handler[irq].arg = arg; 324 sc->sc_handler[irq].level = ipl; 325 326 /* set interrupt type */ 327 reg = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, regidx); 328 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, regidx, 329 (reg & ~(7<<sft)) | (ist_code[type] << sft)); 330 331 #ifdef DEBUG 332 printf("INTCTL=%x,%x\n", 333 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTCNTL), 334 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTCNTH)); 335 #endif 336 337 sc->sc_intr_mask &= ~(1U << irq); 338 obio_update_intrmask(sc); 339 340 restore_interrupts(save); 341 342 #if 0 343 if (ipl > sc->sc_ipl) { 344 pxa2x0_update_intr_masks(sc->sc_intr, ipl); 345 sc->sc_ipl = ipl; 346 } 347 #endif 348 349 return &sc->sc_handler[irq]; 350 } 351 352 void 353 obio_intr_disestablish(struct obio_softc *sc, int irq, int (* func)(void *)) 354 { 355 int error = 0; 356 int save; 357 358 save = disable_interrupts(I32_bit); 359 360 if (sc->sc_handler[irq].func != func) 361 error = 1; 362 else { 363 sc->sc_handler[irq].func = obio_spurious; 364 sc->sc_handler[irq].level = IPL_NONE; 365 366 sc->sc_intr_pending &= ~(1U << irq); 367 sc->sc_intr_mask |= (1U << irq); 368 obio_update_intrmask(sc); 369 } 370 371 restore_interrupts(save); 372 373 if (error) 374 aprint_error_dev(sc->sc_dev, "bad intr_disestablish\n"); 375 } 376 377 void 378 obio_intr_mask(struct obio_softc *sc, struct obio_handler *ih) 379 { 380 int irqno; 381 int save; 382 383 irqno = ih - sc->sc_handler; 384 #ifdef DIAGNOSTIC 385 if (ih == NULL || ih->func==NULL || irqno < 0 || 386 irqno >= G42XXEB_N_INTS) 387 panic("Bad arg for obio_intr_mask"); 388 #endif 389 390 save = disable_interrupts(I32_bit); 391 sc->sc_intr_mask |= 1U<<irqno; 392 obio_update_intrmask(sc); 393 restore_interrupts(save); 394 } 395 396 void 397 obio_intr_unmask(struct obio_softc *sc, struct obio_handler *ih) 398 { 399 int irqno; 400 int save; 401 402 irqno = ih - sc->sc_handler; 403 #ifdef DIAGNOSTIC 404 if (ih == NULL || ih->func==NULL || irqno < 0 || 405 irqno >= G42XXEB_N_INTS) 406 panic("Bad arg for obio_intr_unmask"); 407 #endif 408 409 save = disable_interrupts(I32_bit); 410 sc->sc_intr_mask &= ~(1U<<irqno); 411 obio_update_intrmask(sc); 412 restore_interrupts(save); 413 } 414 415 void 416 obio_peripheral_reset(struct obio_softc *bsc, int no, int onoff) 417 { 418 uint16_t reg; 419 420 reg = bus_space_read_2(bsc->sc_iot, bsc->sc_obioreg_ioh, 421 G42XXEB_RST); 422 bus_space_write_2(bsc->sc_iot, bsc->sc_obioreg_ioh, G42XXEB_RST, 423 onoff ? (reg & ~RST_EXT(no)) : (reg | RST_EXT(no))); 424 } 425 426
Indexes created Sun Sep 21 16:09:51 GMT 2025