| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| dce110_compressor.h | 42 struct dce110_compressor_reg_offsets offsets; member in struct:dce110_compressor
|
| dce110_timing_generator.h | 100 struct dce110_timing_generator_offsets offsets; member in struct:dce110_timing_generator
126 const struct dce110_timing_generator_offsets *offsets);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| dce112_compressor.h | 42 struct dce112_compressor_reg_offsets offsets; member in struct:dce112_compressor
|
| /src/sys/kern/ |
| vnode_if.sh | 669 function offsets() { function
670 # Define offsets array
702 # vp offsets
786 offsets(); function
|
| /src/sys/arch/hpcmips/dev/ |
| mq200subr.c | 195 static int offsets[MQ200_I_MAX] = { local in function:mq200_setup_regctx
205 for (i = 0; i < sizeof(offsets)/sizeof(*offsets); i++) {
206 if (offsets[i] == 0)
212 sc->sc_regctxs[i].offset = offsets[i];
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_framebuffer.h | 154 * @offsets: Offset from buffer start to the actual pixel data in bytes,
163 * @offsets must at least be tile-size aligned, but hardware often has
166 * This should not be used to specifiy x/y pixel offsets into the buffer
170 unsigned int offsets[4]; member in struct:drm_framebuffer
|
| /src/sys/arch/pmax/stand/smallnet/setnetimage/ |
| setnetimage.c | 71 #define NLADDR(x) (mappedbfile + offsets[(x)])
80 size_t offsets[X_NSYMS]; local in function:main
122 if (findoff_elf32(mappedbfile, osb.st_size, nl[i].n_value, &offsets[i]) != 0)
125 printf("%s is at offset %#x in %s\n", nl[i].n_name, offsets[i], bootfile);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| i915_gem_coherency.c | 312 u32 *offsets, *values; local in function:igt_gem_coherency
324 offsets = kmalloc_array(ncachelines, 2*sizeof(u32), GFP_KERNEL);
325 if (!offsets)
328 offsets[count] = count * 64 + 4 * (count % 16);
330 values = offsets + ncachelines;
368 i915_random_reorder(offsets, ncachelines, &prng);
373 err = over->set(&ctx, offsets[n], ~values[n]);
382 err = write->set(&ctx, offsets[n], values[n]);
393 err = read->get(&ctx, offsets[n], &found);
405 ~values[n], offsets[n])
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_tvmodesnv17.c | 365 uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; local in function:tv_save_filter
369 regs[i][j] = nv_read_ptv(dev, offsets[i]+4*j);
377 uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; local in function:tv_load_filter
381 nv_write_ptv(dev, offsets[i]+4*j, regs[i][j]);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| mkregtable.c | 117 struct list_head offsets; member in struct:table
138 list_add_tail(&offset->list, &t->offsets);
143 INIT_LIST_HEAD(&t->offsets);
184 list_for_each_entry(offset, &t->offsets, list) {
|
| radeon_dp_mst.c | 22 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, local in function:radeon_atom_set_enc_offset
30 return offsets[id];
|
| /src/games/rogue/ |
| level.c | 540 static short offsets[4] = {-1, 1, 3, -3}; local in function:fill_it
546 t = offsets[srow];
547 offsets[srow] = offsets[scol];
548 offsets[scol] = t;
552 target_room = rn + offsets[i];
588 recursive_deadend(rn, offsets, srow, scol);
595 recursive_deadend(short rn, const short *offsets, short srow, short scol)
604 de = rn + offsets[i];
623 recursive_deadend(de, offsets, drow, dcol)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_client_modeset.c | 266 struct drm_client_offset *offsets,
345 struct drm_client_offset *offsets,
369 offsets[idx].x = hoffset;
370 offsets[idx].y = voffset;
378 struct drm_client_offset *offsets,
422 * find the tile offsets for this pass - need to find
425 drm_client_get_tile_offsets(connectors, connector_count, modes, offsets, i,
570 struct drm_client_offset *offsets,
774 struct drm_client_offset *offsets; local in function:drm_client_modeset_probe
809 offsets = kcalloc(connector_count, sizeof(*offsets), GFP_KERNEL)
[all...] |
| drm_ioc32.c | 884 u32 offsets[4]; member in struct:drm_mode_fb_cmd232
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_object_types.h | 144 spinlock_t lock; /* Protects access to mmo offsets */
146 struct i915_mmap_offset *offsets[I915_MMAP_NTYPES]; member in struct:drm_i915_gem_object::__anonbfddbbad0308
148 struct rb_root offsets; member in struct:drm_i915_gem_object::__anonbfddbbad0308
|
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_binding.c | 138 * @offsets: array[shader_slot] of offsets to the array[slot]
147 const size_t *offsets; member in struct:vmw_binding_info
192 .offsets = vmw_binding_shader_offsets,
196 .offsets = vmw_binding_rt_offsets,
200 .offsets = vmw_binding_tex_offsets,
204 .offsets = vmw_binding_cb_offsets,
208 .offsets = vmw_binding_shader_offsets,
212 .offsets = vmw_binding_rt_offsets,
216 .offsets = vmw_binding_sr_offsets
[all...] |
| vmwgfx_drv.h | 247 struct vmw_surface_offset *offsets; member in struct:vmw_surface
|
| /src/sys/dev/usb/ |
| if_bwfm_usb.c | 107 #define TRX_MAX_OFFSET 3 /* Max number of file offsets */
152 uint32_t offsets[TRX_MAX_OFFSET];/* Offsets of partitions from start of member in struct:trx_header
|
| uaudio.c | 192 uint16_t offsets[UAUDIO_NFRAMES_HI]; member in struct:chan::chanbuf
3947 cb->offsets[i] = total;
4012 memcpy(ch->cur, cb->buffer + cb->offsets[i], n);
4017 memcpy(ch->cur, cb->buffer + cb->offsets[i] + n,
|
| /src/sys/compat/netbsd32/ |
| netbsd32_drm.c | 877 uint32_t offsets[4]; member in struct:drm_mode_fb_cmd232
905 req64.offsets[i] = req32.offsets[i];
|
| /src/sys/dev/pci/ |
| viogpu.h | 421 __le32 offsets[4]; member in struct:virtio_gpu_set_scanout_blob
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| drm_mode.h | 500 * buffer objects with offsets and pitches per plane.
508 * So it would consist of Y as offsets[0] and UV as
509 * offsets[1]. Note that offsets[0] will generally
524 __u32 offsets[4]; /* offset of each plane */ member in struct:drm_mode_fb_cmd2
|
