1 /* $NetBSD: ohci.c,v 1.330 2025/03/31 14:46:42 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012, 2016, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna23.net), and Nick Hudson. 11 * 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.330 2025/03/31 14:46:42 riastradh Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usb_quirks.h> 70 71 #include <dev/usb/ohcireg.h> 72 #include <dev/usb/ohcivar.h> 73 #include <dev/usb/usbroothub.h> 74 #include <dev/usb/usbhist.h> 75 76 #ifdef USB_DEBUG 77 #ifndef OHCI_DEBUG 78 #define ohcidebug 0 79 #else 80 static int ohcidebug = 0; 81 82 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 83 { 84 int err; 85 const struct sysctlnode *rnode; 86 const struct sysctlnode *cnode; 87 88 err = sysctl_createv(clog, 0, NULL, &rnode, 89 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 90 SYSCTL_DESCR("ohci global controls"), 91 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 92 93 if (err) 94 goto fail; 95 96 /* control debugging printfs */ 97 err = sysctl_createv(clog, 0, &rnode, &cnode, 98 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 99 "debug", SYSCTL_DESCR("Enable debugging output"), 100 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 101 if (err) 102 goto fail; 103 104 return; 105 fail: 106 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 107 } 108 109 #endif /* OHCI_DEBUG */ 110 #endif /* USB_DEBUG */ 111 112 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 113 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 114 #define OHCIHIST_FUNC() USBHIST_FUNC() 115 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 116 117 #if BYTE_ORDER == BIG_ENDIAN 118 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 119 #else 120 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 121 #endif 122 123 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 124 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 125 #define HTOO16(val) O16TOH(val) 126 #define HTOO32(val) O32TOH(val) 127 128 struct ohci_pipe; 129 130 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 131 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 132 133 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 134 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 135 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 136 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 139 Static void ohci_free_sitd_locked(ohci_softc_t *, 140 ohci_soft_itd_t *); 141 142 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 143 int, int); 144 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 145 146 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 147 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 148 149 Static usbd_status ohci_open(struct usbd_pipe *); 150 Static void ohci_poll(struct usbd_bus *); 151 Static void ohci_softintr(void *); 152 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 153 Static void ohci_rhsc_softint(void *); 154 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 158 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 159 ohci_soft_ed_t *); 160 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 162 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 163 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 165 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 166 167 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 168 Static void ohci_device_isoc_enter(struct usbd_xfer *); 169 170 Static struct usbd_xfer * 171 ohci_allocx(struct usbd_bus *, unsigned int); 172 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 173 Static bool ohci_dying(struct usbd_bus *); 174 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 175 Static int ohci_roothub_ctrl(struct usbd_bus *, 176 usb_device_request_t *, void *, int); 177 178 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 179 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 180 Static void ohci_root_intr_abort(struct usbd_xfer *); 181 Static void ohci_root_intr_close(struct usbd_pipe *); 182 Static void ohci_root_intr_done(struct usbd_xfer *); 183 184 Static int ohci_device_ctrl_init(struct usbd_xfer *); 185 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 187 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 188 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 189 Static void ohci_device_ctrl_close(struct usbd_pipe *); 190 Static void ohci_device_ctrl_done(struct usbd_xfer *); 191 192 Static int ohci_device_bulk_init(struct usbd_xfer *); 193 Static void ohci_device_bulk_fini(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 195 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 196 Static void ohci_device_bulk_abort(struct usbd_xfer *); 197 Static void ohci_device_bulk_close(struct usbd_pipe *); 198 Static void ohci_device_bulk_done(struct usbd_xfer *); 199 200 Static int ohci_device_intr_init(struct usbd_xfer *); 201 Static void ohci_device_intr_fini(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 203 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 204 Static void ohci_device_intr_abort(struct usbd_xfer *); 205 Static void ohci_device_intr_close(struct usbd_pipe *); 206 Static void ohci_device_intr_done(struct usbd_xfer *); 207 208 Static int ohci_device_isoc_init(struct usbd_xfer *); 209 Static void ohci_device_isoc_fini(struct usbd_xfer *); 210 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 211 Static void ohci_device_isoc_abort(struct usbd_xfer *); 212 Static void ohci_device_isoc_close(struct usbd_pipe *); 213 Static void ohci_device_isoc_done(struct usbd_xfer *); 214 215 Static usbd_status ohci_device_setintr(ohci_softc_t *, 216 struct ohci_pipe *, int); 217 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abortx(struct usbd_xfer *); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_abortx = ohci_abortx, 291 .ubm_dying = ohci_dying, 292 .ubm_getlock = ohci_get_lock, 293 .ubm_rhctrl = ohci_roothub_ctrl, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 297 .upm_transfer = ohci_root_intr_transfer, 298 .upm_start = ohci_root_intr_start, 299 .upm_abort = ohci_root_intr_abort, 300 .upm_close = ohci_root_intr_close, 301 .upm_cleartoggle = ohci_noop, 302 .upm_done = ohci_root_intr_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 306 .upm_init = ohci_device_ctrl_init, 307 .upm_fini = ohci_device_ctrl_fini, 308 .upm_transfer = ohci_device_ctrl_transfer, 309 .upm_start = ohci_device_ctrl_start, 310 .upm_abort = ohci_device_ctrl_abort, 311 .upm_close = ohci_device_ctrl_close, 312 .upm_cleartoggle = ohci_noop, 313 .upm_done = ohci_device_ctrl_done, 314 }; 315 316 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 317 .upm_init = ohci_device_intr_init, 318 .upm_fini = ohci_device_intr_fini, 319 .upm_transfer = ohci_device_intr_transfer, 320 .upm_start = ohci_device_intr_start, 321 .upm_abort = ohci_device_intr_abort, 322 .upm_close = ohci_device_intr_close, 323 .upm_cleartoggle = ohci_device_clear_toggle, 324 .upm_done = ohci_device_intr_done, 325 }; 326 327 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 328 .upm_init = ohci_device_bulk_init, 329 .upm_fini = ohci_device_bulk_fini, 330 .upm_transfer = ohci_device_bulk_transfer, 331 .upm_start = ohci_device_bulk_start, 332 .upm_abort = ohci_device_bulk_abort, 333 .upm_close = ohci_device_bulk_close, 334 .upm_cleartoggle = ohci_device_clear_toggle, 335 .upm_done = ohci_device_bulk_done, 336 }; 337 338 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 339 .upm_init = ohci_device_isoc_init, 340 .upm_fini = ohci_device_isoc_fini, 341 .upm_transfer = ohci_device_isoc_transfer, 342 .upm_abort = ohci_device_isoc_abort, 343 .upm_close = ohci_device_isoc_close, 344 .upm_cleartoggle = ohci_noop, 345 .upm_done = ohci_device_isoc_done, 346 }; 347 348 int 349 ohci_activate(device_t self, enum devact act) 350 { 351 struct ohci_softc *sc = device_private(self); 352 353 switch (act) { 354 case DVACT_DEACTIVATE: 355 sc->sc_dying = 1; 356 return 0; 357 default: 358 return EOPNOTSUPP; 359 } 360 } 361 362 void 363 ohci_childdet(device_t self, device_t child) 364 { 365 struct ohci_softc *sc = device_private(self); 366 367 KASSERT(sc->sc_child == child); 368 sc->sc_child = NULL; 369 } 370 371 void 372 ohci_detach(struct ohci_softc *sc) 373 { 374 375 KASSERT(sc->sc_child == NULL); 376 377 if (!sc->sc_attached) 378 return; 379 380 softint_disestablish(sc->sc_rhsc_si); 381 382 callout_halt(&sc->sc_tmo_rhsc, NULL); 383 callout_destroy(&sc->sc_tmo_rhsc); 384 385 mutex_destroy(&sc->sc_lock); 386 mutex_destroy(&sc->sc_intr_lock); 387 388 if (sc->sc_hcca != NULL) 389 usb_freemem(&sc->sc_hccadma); 390 pool_cache_destroy(sc->sc_xferpool); 391 cv_destroy(&sc->sc_abort_cv); 392 } 393 394 ohci_soft_ed_t * 395 ohci_alloc_sed(ohci_softc_t *sc) 396 { 397 ohci_soft_ed_t *sed; 398 int i, offs; 399 usb_dma_t dma; 400 401 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 402 403 mutex_enter(&sc->sc_lock); 404 if (sc->sc_freeeds == NULL) { 405 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 406 mutex_exit(&sc->sc_lock); 407 408 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 409 OHCI_ED_SIZE * OHCI_ED_CHUNK, 410 OHCI_ED_ALIGN, 0, &dma); 411 if (err) 412 return NULL; 413 414 ohci_soft_ed_t *seds = 415 kmem_alloc(sizeof(*sed) * OHCI_ED_CHUNK, KM_SLEEP); 416 /* 417 * We can avoid USBMALLOC_COHERENT as the EDs are each on a 418 * cacheline. 419 */ 420 mutex_enter(&sc->sc_lock); 421 for (i = 0; i < OHCI_ED_CHUNK; i++) { 422 offs = i * OHCI_ED_SIZE; 423 424 sed = &seds[i]; 425 sed->ed = KERNADDR(&dma, offs); 426 sed->physaddr = DMAADDR(&dma, offs); 427 sed->dma = dma; 428 sed->offs = offs; 429 sed->next = sc->sc_freeeds; 430 431 sc->sc_freeeds = sed; 432 } 433 } 434 sed = sc->sc_freeeds; 435 sc->sc_freeeds = sed->next; 436 mutex_exit(&sc->sc_lock); 437 438 memset(sed->ed, 0, sizeof(*sed->ed)); 439 sed->next = 0; 440 return sed; 441 } 442 443 static inline void 444 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 445 { 446 447 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 448 449 sed->next = sc->sc_freeeds; 450 sc->sc_freeeds = sed; 451 } 452 453 void 454 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 455 { 456 457 mutex_enter(&sc->sc_lock); 458 ohci_free_sed_locked(sc, sed); 459 mutex_exit(&sc->sc_lock); 460 } 461 462 ohci_soft_td_t * 463 ohci_alloc_std(ohci_softc_t *sc) 464 { 465 ohci_soft_td_t *std; 466 int i, offs; 467 usb_dma_t dma; 468 469 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 470 471 mutex_enter(&sc->sc_lock); 472 if (sc->sc_freetds == NULL) { 473 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 474 mutex_exit(&sc->sc_lock); 475 476 ohci_soft_td_t *stds = 477 kmem_alloc(sizeof(*std) * OHCI_TD_CHUNK, KM_SLEEP); 478 /* 479 * We can avoid USBMALLOC_COHERENT as the TDs are each on a 480 * cacheline. 481 */ 482 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 483 OHCI_TD_SIZE * OHCI_TD_CHUNK, 484 OHCI_TD_ALIGN, 0, &dma); 485 if (err) 486 return NULL; 487 488 mutex_enter(&sc->sc_lock); 489 for (i = 0; i < OHCI_TD_CHUNK; i++) { 490 offs = i * OHCI_TD_SIZE; 491 492 std = &stds[i]; 493 std->td = KERNADDR(&dma, offs); 494 std->physaddr = DMAADDR(&dma, offs); 495 std->dma = dma; 496 std->offs = offs; 497 std->nexttd = sc->sc_freetds; 498 499 sc->sc_freetds = std; 500 } 501 } 502 503 std = sc->sc_freetds; 504 sc->sc_freetds = std->nexttd; 505 mutex_exit(&sc->sc_lock); 506 507 memset(std->td, 0, sizeof(*std->td)); 508 std->nexttd = NULL; 509 std->xfer = NULL; 510 std->held = NULL; 511 512 return std; 513 } 514 515 void 516 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 517 { 518 519 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 520 521 std->nexttd = sc->sc_freetds; 522 sc->sc_freetds = std; 523 } 524 525 void 526 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 527 { 528 529 mutex_enter(&sc->sc_lock); 530 ohci_free_std_locked(sc, std); 531 mutex_exit(&sc->sc_lock); 532 } 533 534 Static int 535 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 536 { 537 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 538 uint16_t flags = xfer->ux_flags; 539 540 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 541 542 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 543 xfer->ux_pipe->up_dev->ud_addr, 544 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 545 length, xfer->ux_pipe->up_dev->ud_speed); 546 547 ASSERT_SLEEPABLE(); 548 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 549 550 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 551 nstd += howmany(length, OHCI_PAGE_SIZE); 552 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 553 KM_SLEEP); 554 ox->ox_nstd = nstd; 555 556 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 557 558 for (size_t j = 0; j < ox->ox_nstd; j++) { 559 ohci_soft_td_t *cur = ohci_alloc_std(sc); 560 if (cur == NULL) 561 goto nomem; 562 563 ox->ox_stds[j] = cur; 564 cur->held = &ox->ox_stds[j]; 565 cur->xfer = xfer; 566 cur->flags = 0; 567 DPRINTFN(10, "xfer=%#jx new std=%#jx held at %#jx", (uintptr_t)ox, 568 (uintptr_t)cur, (uintptr_t)cur->held, 0); 569 } 570 571 return 0; 572 573 nomem: 574 ohci_free_stds(sc, ox); 575 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 576 577 return ENOMEM; 578 } 579 580 Static void 581 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 582 { 583 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 584 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 585 586 mutex_enter(&sc->sc_lock); 587 for (size_t i = 0; i < ox->ox_nstd; i++) { 588 ohci_soft_td_t *std = ox->ox_stds[i]; 589 if (std == NULL) 590 break; 591 ohci_free_std_locked(sc, std); 592 } 593 mutex_exit(&sc->sc_lock); 594 } 595 596 void 597 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 598 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 599 { 600 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 601 ohci_soft_td_t *next, *cur; 602 int len, curlen; 603 usb_dma_t *dma = &xfer->ux_dmabuf; 604 uint16_t flags = xfer->ux_flags; 605 606 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 607 DPRINTF("start len=%jd", alen, 0, 0, 0); 608 609 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 610 611 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 612 xfer->ux_pipe->up_dev->ud_addr, 613 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 614 alen, xfer->ux_pipe->up_dev->ud_speed); 615 616 KASSERT(sp); 617 618 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 619 620 /* 621 * Assign next for the len == 0 case where we don't go through the 622 * main loop. 623 */ 624 len = alen; 625 cur = next = sp; 626 627 usb_syncmem(dma, 0, len, 628 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 629 const uint32_t tdflags = HTOO32( 630 OHCI_TD_SET_DP(rd ? OHCI_TD_DP_IN : OHCI_TD_DP_OUT) | 631 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 632 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_CARRY) | 633 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 634 ); 635 636 size_t curoffs = 0; 637 for (size_t j = 1; len != 0;) { 638 if (j == ox->ox_nstd) 639 next = NULL; 640 else 641 next = ox->ox_stds[j++]; 642 KASSERT(next != cur); 643 644 curlen = len; 645 /* 646 * The OHCI hardware can handle at most one page crossing per 647 * TD. That is, 2 * OHCI_PAGE_SIZE as a maximum. Limit the 648 * length in this TD accordingly. 649 */ 650 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 651 652 int maxlen = (2 * OHCI_PAGE_SIZE) - OHCI_PAGE_OFFSET(sdataphys); 653 if (curlen > maxlen) { 654 curlen = maxlen; 655 656 /* 657 * the length must be a multiple of 658 * the max size 659 */ 660 curlen -= curlen % mps; 661 } 662 663 const int edataoffs = curoffs + curlen - 1; 664 const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs); 665 666 KASSERT(curlen != 0); 667 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 668 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 669 670 cur->td->td_flags = tdflags; 671 cur->td->td_cbp = HTOO32(sdataphys); 672 cur->td->td_be = HTOO32(edataphys); 673 cur->td->td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 674 cur->nexttd = next; 675 cur->len = curlen; 676 cur->flags = OHCI_ADD_LEN; 677 cur->xfer = xfer; 678 ohci_hash_add_td(sc, cur); 679 680 curoffs += curlen; 681 len -= curlen; 682 683 if (len != 0) { 684 KASSERT(next != NULL); 685 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 686 usb_syncmem(&cur->dma, cur->offs, sizeof(*cur->td), 687 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 688 689 cur = next; 690 } 691 } 692 cur->td->td_flags |= 693 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 694 695 if (!rd && 696 (flags & USBD_FORCE_SHORT_XFER) && 697 alen % mps == 0) { 698 /* We're adding a ZLP so sync the previous TD */ 699 usb_syncmem(&cur->dma, cur->offs, sizeof(*cur->td), 700 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 701 702 /* Force a 0 length transfer at the end. */ 703 704 KASSERT(next != NULL); 705 cur = next; 706 707 cur->td->td_flags = tdflags; 708 cur->td->td_cbp = 0; /* indicate 0 length packet */ 709 cur->td->td_nexttd = 0; 710 cur->td->td_be = ~0; 711 cur->nexttd = NULL; 712 cur->len = 0; 713 cur->flags = 0; 714 cur->xfer = xfer; 715 ohci_hash_add_td(sc, cur); 716 717 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 718 } 719 720 /* Last TD gets usb_syncmem'ed by caller */ 721 *ep = cur; 722 } 723 724 ohci_soft_itd_t * 725 ohci_alloc_sitd(ohci_softc_t *sc) 726 { 727 ohci_soft_itd_t *sitd; 728 int i, offs; 729 usb_dma_t dma; 730 731 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 732 733 mutex_enter(&sc->sc_lock); 734 if (sc->sc_freeitds == NULL) { 735 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 736 mutex_exit(&sc->sc_lock); 737 738 int err = usb_allocmem(sc->sc_bus.ub_dmatag, 739 OHCI_ITD_SIZE * OHCI_ITD_CHUNK, 740 OHCI_ITD_ALIGN, 0, &dma); 741 if (err) 742 return NULL; 743 744 ohci_soft_itd_t *sitds = 745 kmem_alloc(sizeof(*sitd) * OHCI_ITD_CHUNK, KM_SLEEP); 746 747 mutex_enter(&sc->sc_lock); 748 for (i = 0; i < OHCI_ITD_CHUNK; i++) { 749 offs = i * OHCI_ITD_SIZE; 750 751 sitd = &sitds[i]; 752 sitd->itd = KERNADDR(&dma, offs); 753 sitd->physaddr = DMAADDR(&dma, offs); 754 sitd->dma = dma; 755 sitd->offs = offs; 756 sitd->nextitd = sc->sc_freeitds; 757 758 sc->sc_freeitds = sitd; 759 } 760 } 761 762 sitd = sc->sc_freeitds; 763 sc->sc_freeitds = sitd->nextitd; 764 mutex_exit(&sc->sc_lock); 765 766 memset(sitd->itd, 0, sizeof(*sitd->itd)); 767 sitd->nextitd = NULL; 768 sitd->xfer = NULL; 769 770 #ifdef DIAGNOSTIC 771 sitd->isdone = true; 772 #endif 773 774 return sitd; 775 } 776 777 Static void 778 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 779 { 780 781 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 782 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 783 784 KASSERT(sitd->isdone); 785 #ifdef DIAGNOSTIC 786 /* Warn double free */ 787 sitd->isdone = false; 788 #endif 789 790 sitd->nextitd = sc->sc_freeitds; 791 sc->sc_freeitds = sitd; 792 } 793 794 void 795 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 796 { 797 798 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 799 800 mutex_enter(&sc->sc_lock); 801 ohci_free_sitd_locked(sc, sitd); 802 mutex_exit(&sc->sc_lock); 803 } 804 805 int 806 ohci_init(ohci_softc_t *sc) 807 { 808 ohci_soft_ed_t *sed, *psed; 809 usbd_status err; 810 int i; 811 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 812 813 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 814 815 aprint_normal_dev(sc->sc_dev, ""); 816 817 sc->sc_hcca = NULL; 818 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 819 820 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 821 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 822 823 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 824 ohci_rhsc_softint, sc); 825 826 for (i = 0; i < OHCI_HASH_SIZE; i++) 827 LIST_INIT(&sc->sc_hash_tds[i]); 828 for (i = 0; i < OHCI_HASH_SIZE; i++) 829 LIST_INIT(&sc->sc_hash_itds[i]); 830 831 TAILQ_INIT(&sc->sc_abortingxfers); 832 cv_init(&sc->sc_abort_cv, "ohciabt"); 833 834 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 835 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 836 837 rev = OREAD4(sc, OHCI_REVISION); 838 aprint_normal("OHCI version %" __PRIuBITS ".%" __PRIuBITS "%s\n", 839 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 840 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 841 842 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 843 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 844 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 845 return -1; 846 } 847 sc->sc_bus.ub_revision = USBREV_1_0; 848 sc->sc_bus.ub_usedma = true; 849 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 850 851 /* XXX determine alignment by R/W */ 852 /* Allocate the HCCA area. */ 853 err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_HCCA_SIZE, 854 OHCI_HCCA_ALIGN, USBMALLOC_COHERENT, &sc->sc_hccadma); 855 if (err) { 856 sc->sc_hcca = NULL; 857 return err; 858 } 859 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 860 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 861 862 sc->sc_eintrs = OHCI_NORMAL_INTRS; 863 864 /* Allocate dummy ED that starts the control list. */ 865 sc->sc_ctrl_head = ohci_alloc_sed(sc); 866 if (sc->sc_ctrl_head == NULL) { 867 err = ENOMEM; 868 goto bad1; 869 } 870 sc->sc_ctrl_head->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); 871 usb_syncmem(&sc->sc_ctrl_head->dma, sc->sc_ctrl_head->offs, 872 sizeof(*sc->sc_ctrl_head->ed), 873 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 874 875 /* Allocate dummy ED that starts the bulk list. */ 876 sc->sc_bulk_head = ohci_alloc_sed(sc); 877 if (sc->sc_bulk_head == NULL) { 878 err = ENOMEM; 879 goto bad2; 880 } 881 sc->sc_bulk_head->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); 882 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 883 sizeof(*sc->sc_bulk_head->ed), 884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 885 886 /* Allocate dummy ED that starts the isochronous list. */ 887 sc->sc_isoc_head = ohci_alloc_sed(sc); 888 if (sc->sc_isoc_head == NULL) { 889 err = ENOMEM; 890 goto bad3; 891 } 892 sc->sc_isoc_head->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); 893 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 894 sizeof(*sc->sc_isoc_head->ed), 895 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 896 897 /* Allocate all the dummy EDs that make up the interrupt tree. */ 898 for (i = 0; i < OHCI_NO_EDS; i++) { 899 sed = ohci_alloc_sed(sc); 900 if (sed == NULL) { 901 while (--i >= 0) 902 ohci_free_sed(sc, sc->sc_eds[i]); 903 err = ENOMEM; 904 goto bad4; 905 } 906 /* All ED fields are set to 0. */ 907 sc->sc_eds[i] = sed; 908 sed->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); 909 if (i != 0) 910 psed = sc->sc_eds[(i-1) / 2]; 911 else 912 psed= sc->sc_isoc_head; 913 sed->next = psed; 914 sed->ed->ed_nexted = HTOO32(psed->physaddr); 915 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 917 } 918 /* 919 * Fill HCCA interrupt table. The bit reversal is to get 920 * the tree set up properly to spread the interrupts. 921 */ 922 for (i = 0; i < OHCI_NO_INTRS; i++) 923 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 924 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 925 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 926 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 927 928 #ifdef OHCI_DEBUG 929 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 930 if (ohcidebug >= 15) { 931 for (i = 0; i < OHCI_NO_EDS; i++) { 932 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 933 ohci_dump_ed(sc, sc->sc_eds[i]); 934 } 935 DPRINTFN(15, "iso", 0, 0, 0 ,0); 936 ohci_dump_ed(sc, sc->sc_isoc_head); 937 } 938 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 939 #endif 940 941 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 942 ctl = OREAD4(sc, OHCI_CONTROL); 943 rwc = ctl & OHCI_RWC; 944 fm = OREAD4(sc, OHCI_FM_INTERVAL); 945 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 946 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 947 948 /* Determine in what context we are running. */ 949 if (ctl & OHCI_IR) { 950 /* SMM active, request change */ 951 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 952 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 953 (OHCI_OC | OHCI_MIE)) 954 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 955 s = OREAD4(sc, OHCI_COMMAND_STATUS); 956 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 957 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 958 usb_delay_ms(&sc->sc_bus, 1); 959 ctl = OREAD4(sc, OHCI_CONTROL); 960 } 961 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 962 if ((ctl & OHCI_IR) == 0) { 963 aprint_error_dev(sc->sc_dev, 964 "SMM does not respond, resetting\n"); 965 OWRITE4(sc, OHCI_CONTROL, 966 OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 967 goto reset; 968 } 969 #if 0 970 /* 971 * Don't bother trying to reuse the BIOS init, we'll reset it 972 * anyway. 973 */ 974 } else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) { 975 /* BIOS started controller. */ 976 DPRINTF("BIOS active", 0, 0, 0, 0); 977 if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) { 978 OWRITE4(sc, OHCI_CONTROL, 979 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc); 980 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 981 } 982 #endif 983 } else { 984 DPRINTF("cold started", 0 ,0 ,0 ,0); 985 reset: 986 /* Controller was cold started. */ 987 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 988 } 989 990 /* 991 * This reset should not be necessary according to the OHCI spec, but 992 * without it some controllers do not start. 993 */ 994 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 995 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 996 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 997 998 /* We now own the host controller and the bus has been reset. */ 999 1000 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1001 /* Nominal time for a reset is 10 us. */ 1002 for (i = 0; i < 10; i++) { 1003 delay(10); 1004 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1005 if (!hcr) 1006 break; 1007 } 1008 if (hcr) { 1009 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 1010 err = EIO; 1011 goto bad5; 1012 } 1013 #ifdef OHCI_DEBUG 1014 if (ohcidebug >= 15) 1015 ohci_dumpregs(sc); 1016 #endif 1017 1018 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1019 1020 /* Set up HC registers. */ 1021 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1022 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1023 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1024 /* disable all interrupts and then switch on all desired interrupts */ 1025 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1026 /* switch on desired functional features */ 1027 ctl = OREAD4(sc, OHCI_CONTROL); 1028 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1029 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1030 OHCI_CBSR_SET(OHCI_RATIO_1_4) | 1031 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc; 1032 /* And finally start it! */ 1033 OWRITE4(sc, OHCI_CONTROL, ctl); 1034 1035 /* 1036 * The controller is now OPERATIONAL. Set a some final 1037 * registers that should be set earlier, but that the 1038 * controller ignores when in the SUSPEND state. 1039 */ 1040 ival = OHCI_FM_GET_IVAL(fm); 1041 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FM_FIT) ^ OHCI_FM_FIT; 1042 fm |= OHCI_FSMPS(ival) | ival; 1043 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1044 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1045 OWRITE4(sc, OHCI_PERIODIC_START, per); 1046 1047 if (sc->sc_flags & OHCIF_SUPERIO) { 1048 /* no overcurrent protection */ 1049 desca |= OHCI_RHD_NOCP; 1050 /* 1051 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1052 * that 1053 * - ports are always power switched 1054 * - don't wait for powered root hub port 1055 */ 1056 desca &= ~(OHCI_RHD_POTPGT_MASK | OHCI_RHD_NPS); 1057 } 1058 1059 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1060 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_RHD_NOCP); 1061 OWRITE4(sc, OHCI_RH_STATUS, OHCI_RHS_LPSC); /* Enable port power */ 1062 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1063 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1064 1065 /* 1066 * The AMD756 requires a delay before re-reading the register, 1067 * otherwise it will occasionally report 0 ports. 1068 */ 1069 sc->sc_noport = 0; 1070 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1071 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1072 sc->sc_noport = 1073 OHCI_RHD_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1074 } 1075 1076 #ifdef OHCI_DEBUG 1077 if (ohcidebug >= 5) 1078 ohci_dumpregs(sc); 1079 #endif 1080 1081 /* Set up the bus struct. */ 1082 sc->sc_bus.ub_methods = &ohci_bus_methods; 1083 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1084 1085 sc->sc_control = sc->sc_intre = 0; 1086 1087 /* Finally, turn on interrupts. */ 1088 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1089 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1090 1091 sc->sc_attached = true; 1092 return 0; 1093 1094 bad5: 1095 for (i = 0; i < OHCI_NO_EDS; i++) 1096 ohci_free_sed(sc, sc->sc_eds[i]); 1097 bad4: 1098 ohci_free_sed(sc, sc->sc_isoc_head); 1099 bad3: 1100 ohci_free_sed(sc, sc->sc_bulk_head); 1101 bad2: 1102 ohci_free_sed(sc, sc->sc_ctrl_head); 1103 bad1: 1104 usb_freemem(&sc->sc_hccadma); 1105 sc->sc_hcca = NULL; 1106 return err; 1107 } 1108 1109 struct usbd_xfer * 1110 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1111 { 1112 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1113 struct usbd_xfer *xfer; 1114 1115 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1116 if (xfer != NULL) { 1117 memset(xfer, 0, sizeof(struct ohci_xfer)); 1118 1119 #ifdef DIAGNOSTIC 1120 xfer->ux_state = XFER_BUSY; 1121 #endif 1122 } 1123 return xfer; 1124 } 1125 1126 void 1127 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1128 { 1129 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1130 1131 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1132 xfer->ux_status == USBD_NOT_STARTED, 1133 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1134 #ifdef DIAGNOSTIC 1135 xfer->ux_state = XFER_FREE; 1136 #endif 1137 pool_cache_put(sc->sc_xferpool, xfer); 1138 } 1139 1140 Static bool 1141 ohci_dying(struct usbd_bus *bus) 1142 { 1143 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1144 1145 return sc->sc_dying; 1146 } 1147 1148 Static void 1149 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1150 { 1151 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1152 1153 *lock = &sc->sc_lock; 1154 } 1155 1156 /* 1157 * Shut down the controller when the system is going down. 1158 */ 1159 bool 1160 ohci_shutdown(device_t self, int flags) 1161 { 1162 ohci_softc_t *sc = device_private(self); 1163 1164 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1165 1166 if (!sc->sc_attached) 1167 return true; 1168 1169 DPRINTF("stopping the HC", 0, 0, 0, 0); 1170 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1171 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1172 return true; 1173 } 1174 1175 bool 1176 ohci_resume(device_t dv, const pmf_qual_t *qual) 1177 { 1178 ohci_softc_t *sc = device_private(dv); 1179 uint32_t ctl; 1180 1181 /* Some broken BIOSes do not recover these values */ 1182 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1183 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1184 sc->sc_ctrl_head->physaddr); 1185 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1186 sc->sc_bulk_head->physaddr); 1187 if (sc->sc_intre) 1188 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1189 (OHCI_ALL_INTRS | OHCI_MIE)); 1190 if (sc->sc_control) 1191 ctl = sc->sc_control; 1192 else 1193 ctl = OREAD4(sc, OHCI_CONTROL); 1194 ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME); 1195 OWRITE4(sc, OHCI_CONTROL, ctl); 1196 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1197 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL); 1198 OWRITE4(sc, OHCI_CONTROL, ctl); 1199 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1200 sc->sc_control = sc->sc_intre = 0; 1201 1202 return true; 1203 } 1204 1205 bool 1206 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1207 { 1208 ohci_softc_t *sc = device_private(dv); 1209 uint32_t ctl; 1210 1211 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1212 if (sc->sc_control == 0) { 1213 /* 1214 * Preserve register values, in case that BIOS 1215 * does not recover them. 1216 */ 1217 sc->sc_control = ctl; 1218 sc->sc_intre = OREAD4(sc, 1219 OHCI_INTERRUPT_ENABLE); 1220 } 1221 ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND); 1222 OWRITE4(sc, OHCI_CONTROL, ctl); 1223 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1224 1225 return true; 1226 } 1227 1228 #ifdef OHCI_DEBUG 1229 void 1230 ohci_dumpregs(ohci_softc_t *sc) 1231 { 1232 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1233 1234 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1235 OREAD4(sc, OHCI_REVISION), 1236 OREAD4(sc, OHCI_CONTROL), 1237 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1238 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1239 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1240 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1241 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1242 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1243 OREAD4(sc, OHCI_HCCA), 1244 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1245 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1246 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1247 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1248 OREAD4(sc, OHCI_BULK_HEAD_ED), 1249 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1250 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1251 OREAD4(sc, OHCI_DONE_HEAD), 1252 OREAD4(sc, OHCI_FM_INTERVAL), 1253 OREAD4(sc, OHCI_FM_REMAINING), 0); 1254 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1255 OREAD4(sc, OHCI_FM_NUMBER), 1256 OREAD4(sc, OHCI_PERIODIC_START), 1257 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1258 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1259 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1260 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1261 OREAD4(sc, OHCI_RH_STATUS), 0); 1262 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1263 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1264 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1265 usb_syncmem(&sc->sc_hccadma, 1266 offsetof(struct ohci_hcca, hcca_frame_number), 1267 sizeof(sc->sc_hcca->hcca_frame_number) + 1268 sizeof(sc->sc_hcca->hcca_done_head), 1269 BUS_DMASYNC_POSTREAD); 1270 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1271 O32TOH(sc->sc_hcca->hcca_frame_number), 1272 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1273 } 1274 #endif 1275 1276 Static int ohci_intr1(ohci_softc_t *); 1277 1278 int 1279 ohci_intr(void *p) 1280 { 1281 ohci_softc_t *sc = p; 1282 int ret = 0; 1283 1284 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1285 1286 if (sc == NULL) 1287 return 0; 1288 1289 mutex_spin_enter(&sc->sc_intr_lock); 1290 1291 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1292 goto done; 1293 1294 /* If we get an interrupt while polling, then just ignore it. */ 1295 if (sc->sc_bus.ub_usepolling) { 1296 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1297 /* for level triggered intrs, should do something to ack */ 1298 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1299 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1300 1301 goto done; 1302 } 1303 1304 ret = ohci_intr1(sc); 1305 1306 done: 1307 mutex_spin_exit(&sc->sc_intr_lock); 1308 return ret; 1309 } 1310 1311 Static int 1312 ohci_intr1(ohci_softc_t *sc) 1313 { 1314 uint32_t intrs, eintrs; 1315 1316 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1317 1318 /* In case the interrupt occurs before initialization has completed. */ 1319 if (sc == NULL || sc->sc_hcca == NULL) { 1320 #ifdef DIAGNOSTIC 1321 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1322 #endif 1323 return 0; 1324 } 1325 1326 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1327 1328 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1329 if (!intrs) 1330 return 0; 1331 1332 /* Acknowledge */ 1333 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1334 eintrs = intrs & sc->sc_eintrs; 1335 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1336 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1337 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1338 sc->sc_eintrs); 1339 1340 if (!eintrs) { 1341 return 0; 1342 } 1343 1344 if (eintrs & OHCI_SO) { 1345 sc->sc_overrun_cnt++; 1346 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1347 printf("%s: %u scheduling overruns\n", 1348 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1349 sc->sc_overrun_cnt = 0; 1350 } 1351 /* XXX do what */ 1352 eintrs &= ~OHCI_SO; 1353 } 1354 if (eintrs & OHCI_WDH) { 1355 /* 1356 * We block the interrupt below, and reenable it later from 1357 * ohci_softintr(). 1358 */ 1359 usb_schedsoftintr(&sc->sc_bus); 1360 } 1361 if (eintrs & OHCI_SF) { 1362 struct ohci_xfer *ox, *tmp; 1363 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1364 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 1365 (uintptr_t)ox, 0, 0); 1366 ox->ox_abintrs &= ~OHCI_SF; 1367 KASSERT(ox->ox_abintrs == 0); 1368 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1369 } 1370 cv_broadcast(&sc->sc_abort_cv); 1371 1372 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1373 DPRINTFN(10, "end SOF %#jx", (uintptr_t)sc, 0, 0, 0); 1374 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1375 } 1376 if (eintrs & OHCI_RD) { 1377 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1378 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1379 /* XXX process resume detect */ 1380 } 1381 if (eintrs & OHCI_UE) { 1382 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1383 printf("%s: unrecoverable error, controller halted\n", 1384 device_xname(sc->sc_dev)); 1385 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1386 /* XXX what else */ 1387 } 1388 if (eintrs & OHCI_RHSC) { 1389 /* 1390 * We block the interrupt below, and reenable it later from 1391 * a timeout. 1392 */ 1393 softint_schedule(sc->sc_rhsc_si); 1394 } 1395 1396 if (eintrs != 0) { 1397 /* Block unprocessed interrupts. */ 1398 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1399 sc->sc_eintrs &= ~eintrs; 1400 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1401 eintrs, 0, 0); 1402 } 1403 1404 return 1; 1405 } 1406 1407 void 1408 ohci_rhsc_enable(void *v_sc) 1409 { 1410 ohci_softc_t *sc = v_sc; 1411 1412 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1413 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1414 mutex_spin_enter(&sc->sc_intr_lock); 1415 sc->sc_eintrs |= OHCI_RHSC; 1416 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1417 mutex_spin_exit(&sc->sc_intr_lock); 1418 } 1419 1420 #ifdef OHCI_DEBUG 1421 const char *const ohci_cc_strs[] = { 1422 "NO_ERROR", 1423 "CRC", 1424 "BIT_STUFFING", 1425 "DATA_TOGGLE_MISMATCH", 1426 "STALL", 1427 "DEVICE_NOT_RESPONDING", 1428 "PID_CHECK_FAILURE", 1429 "UNEXPECTED_PID", 1430 "DATA_OVERRUN", 1431 "DATA_UNDERRUN", 1432 "BUFFER_OVERRUN", 1433 "BUFFER_UNDERRUN", 1434 "reserved", 1435 "reserved", 1436 "NOT_ACCESSED", 1437 "NOT_ACCESSED", 1438 }; 1439 #endif 1440 1441 void 1442 ohci_softintr(void *v) 1443 { 1444 struct usbd_bus *bus = v; 1445 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1446 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1447 ohci_soft_td_t *std, *sdone, *stdnext; 1448 struct usbd_xfer *xfer; 1449 struct ohci_pipe *opipe; 1450 int len, cc; 1451 int i, j, actlen, iframes, uedir; 1452 ohci_physaddr_t done = 0; 1453 1454 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1455 1456 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1457 1458 /* 1459 * Only read hccadone if WDH is set - we might get here from places 1460 * other than an interrupt 1461 */ 1462 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1463 DPRINTFN(10, "no WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1464 return; 1465 } 1466 1467 DPRINTFN(10, "WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1468 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1469 sizeof(sc->sc_hcca->hcca_done_head), 1470 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1471 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1472 sc->sc_hcca->hcca_done_head = 0; 1473 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1474 sizeof(sc->sc_hcca->hcca_done_head), 1475 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1476 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1477 sc->sc_eintrs |= OHCI_WDH; 1478 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1479 1480 /* Reverse the done list. */ 1481 for (sdone = NULL, sidone = NULL; done != 0; ) { 1482 std = ohci_hash_find_td(sc, done); 1483 if (std != NULL) { 1484 usb_syncmem(&std->dma, std->offs, sizeof(*std->td), 1485 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1486 std->dnext = sdone; 1487 done = O32TOH(std->td->td_nexttd); 1488 sdone = std; 1489 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1490 continue; 1491 } 1492 sitd = ohci_hash_find_itd(sc, done); 1493 if (sitd != NULL) { 1494 usb_syncmem(&sitd->dma, sitd->offs, sizeof(*sitd->itd), 1495 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1496 sitd->dnext = sidone; 1497 done = O32TOH(sitd->itd->itd_nextitd); 1498 sidone = sitd; 1499 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1500 continue; 1501 } 1502 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1503 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1504 (u_long)done); 1505 break; 1506 } 1507 1508 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1509 (uintptr_t)sidone, 0, 0); 1510 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1511 #ifdef OHCI_DEBUG 1512 if (ohcidebug >= 10) { 1513 for (std = sdone; std; std = std->dnext) 1514 ohci_dump_td(sc, std); 1515 } 1516 #endif 1517 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1518 1519 for (std = sdone; std; std = stdnext) { 1520 stdnext = std->dnext; 1521 if (std->held == NULL) { 1522 DPRINTFN(10, "std=%#jx held is null", (uintptr_t)std, 1523 0, 0, 0); 1524 ohci_hash_rem_td(sc, std); 1525 ohci_free_std_locked(sc, std); 1526 continue; 1527 } 1528 1529 xfer = std->xfer; 1530 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx dnext=%#jx", 1531 (uintptr_t)std, (uintptr_t)xfer, 1532 (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), (uintptr_t)stdnext); 1533 if (xfer == NULL) { 1534 /* 1535 * xfer == NULL: There seems to be no xfer associated 1536 * with this TD. It is tailp that happened to end up on 1537 * the done queue. 1538 * Shouldn't happen, but some chips are broken(?). 1539 */ 1540 continue; 1541 } 1542 /* 1543 * Try to claim this xfer for completion. If it has 1544 * already completed or aborted, drop it on the floor. 1545 */ 1546 if (!usbd_xfer_trycomplete(xfer)) 1547 continue; 1548 1549 len = std->len; 1550 if (std->td->td_cbp != 0) 1551 len -= O32TOH(std->td->td_be) - 1552 O32TOH(std->td->td_cbp) + 1; 1553 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1554 if (std->flags & OHCI_ADD_LEN) 1555 xfer->ux_actlen += len; 1556 1557 cc = OHCI_TD_GET_CC(O32TOH(std->td->td_flags)); 1558 if (cc == OHCI_CC_NO_ERROR) { 1559 ohci_hash_rem_td(sc, std); 1560 if (std->flags & OHCI_CALL_DONE) { 1561 xfer->ux_status = USBD_NORMAL_COMPLETION; 1562 usb_transfer_complete(xfer); 1563 } 1564 } else { 1565 /* 1566 * Endpoint is halted. First unlink all the TDs 1567 * belonging to the failed transfer, and then restart 1568 * the endpoint. 1569 */ 1570 ohci_soft_td_t *p, *n; 1571 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1572 1573 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1574 1575 /* remove xfer's TDs from the hash */ 1576 for (p = std; p->xfer == xfer; p = n) { 1577 n = p->nexttd; 1578 ohci_hash_rem_td(sc, p); 1579 } 1580 1581 ohci_soft_ed_t *sed = opipe->sed; 1582 1583 /* clear halt and TD chain, preserving toggle carry */ 1584 sed->ed->ed_headp = HTOO32(p->physaddr | 1585 (O32TOH(sed->ed->ed_headp) & OHCI_TOGGLECARRY)); 1586 usb_syncmem(&sed->dma, 1587 sed->offs + offsetof(ohci_ed_t, ed_headp), 1588 sizeof(sed->ed->ed_headp), 1589 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1590 1591 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1592 1593 if (cc == OHCI_CC_DATA_UNDERRUN) 1594 xfer->ux_status = USBD_NORMAL_COMPLETION; 1595 else if (cc == OHCI_CC_STALL) 1596 xfer->ux_status = USBD_STALLED; 1597 else 1598 xfer->ux_status = USBD_IOERROR; 1599 usb_transfer_complete(xfer); 1600 } 1601 } 1602 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1603 #ifdef OHCI_DEBUG 1604 if (ohcidebug >= 10) { 1605 for (sitd = sidone; sitd; sitd = sitd->dnext) 1606 ohci_dump_itd(sc, sitd); 1607 } 1608 #endif 1609 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1610 1611 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1612 xfer = sitd->xfer; 1613 sitdnext = sitd->dnext; 1614 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1615 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1616 0); 1617 if (xfer == NULL) 1618 continue; 1619 1620 /* 1621 * Try to claim this xfer for completion. If it has 1622 * already completed or aborted, drop it on the floor. 1623 */ 1624 if (!usbd_xfer_trycomplete(xfer)) 1625 continue; 1626 1627 KASSERT(!sitd->isdone); 1628 #ifdef DIAGNOSTIC 1629 sitd->isdone = true; 1630 #endif 1631 if (sitd->flags & OHCI_CALL_DONE) { 1632 ohci_soft_itd_t *next; 1633 1634 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1635 opipe->isoc.inuse -= xfer->ux_nframes; 1636 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1637 bEndpointAddress); 1638 xfer->ux_status = USBD_NORMAL_COMPLETION; 1639 actlen = 0; 1640 for (i = 0, sitd = xfer->ux_hcpriv;; 1641 sitd = next) { 1642 next = sitd->nextitd; 1643 1644 usb_syncmem(&sitd->dma, sitd->offs, sizeof(*sitd->itd), 1645 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1646 1647 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1648 itd->itd_flags)) != OHCI_CC_NO_ERROR) 1649 xfer->ux_status = USBD_IOERROR; 1650 /* For input, update frlengths with actual */ 1651 /* XXX anything necessary for output? */ 1652 if (uedir == UE_DIR_IN && 1653 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1654 iframes = OHCI_ITD_GET_FC(O32TOH( 1655 sitd->itd->itd_flags)); 1656 for (j = 0; j < iframes; i++, j++) { 1657 len = O16TOH(sitd-> 1658 itd->itd_offset[j]); 1659 if ((OHCI_ITD_PSW_GET_CC(len) & 1660 OHCI_CC_NOT_ACCESSED_MASK) 1661 == OHCI_CC_NOT_ACCESSED) 1662 len = 0; 1663 else 1664 len = OHCI_ITD_PSW_SIZE(len); 1665 xfer->ux_frlengths[i] = len; 1666 actlen += len; 1667 } 1668 } 1669 if (sitd->flags & OHCI_CALL_DONE) 1670 break; 1671 ohci_hash_rem_itd(sc, sitd); 1672 1673 } 1674 ohci_hash_rem_itd(sc, sitd); 1675 if (uedir == UE_DIR_IN && 1676 xfer->ux_status == USBD_NORMAL_COMPLETION) 1677 xfer->ux_actlen = actlen; 1678 xfer->ux_hcpriv = NULL; 1679 1680 usb_transfer_complete(xfer); 1681 } 1682 } 1683 1684 DPRINTFN(10, "done", 0, 0, 0, 0); 1685 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1686 } 1687 1688 void 1689 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1690 { 1691 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1692 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1693 int len = UGETW(xfer->ux_request.wLength); 1694 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1695 1696 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1697 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1698 1699 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1700 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1701 1702 if (len) 1703 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1704 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1705 usb_syncmem(&opipe->ctrl.reqdma, 0, 1706 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1707 } 1708 1709 void 1710 ohci_device_intr_done(struct usbd_xfer *xfer) 1711 { 1712 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1713 int isread = 1714 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1715 1716 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1717 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1718 xfer->ux_actlen, 0, 0); 1719 1720 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1721 1722 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1723 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1724 } 1725 1726 void 1727 ohci_device_bulk_done(struct usbd_xfer *xfer) 1728 { 1729 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1730 1731 int isread = 1732 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1733 1734 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1735 1736 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1737 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1738 0, 0); 1739 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1740 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1741 } 1742 1743 Static void 1744 ohci_rhsc_softint(void *arg) 1745 { 1746 ohci_softc_t *sc = arg; 1747 1748 mutex_enter(&sc->sc_lock); 1749 1750 ohci_rhsc(sc, sc->sc_intrxfer); 1751 1752 /* Do not allow RHSC interrupts > 1 per second */ 1753 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1754 1755 mutex_exit(&sc->sc_lock); 1756 } 1757 1758 void 1759 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1760 { 1761 u_char *p; 1762 int i, m; 1763 int hstatus __unused; 1764 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1765 1766 KASSERT(mutex_owned(&sc->sc_lock)); 1767 1768 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1769 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1770 (uintptr_t)xfer, hstatus, 0); 1771 1772 if (xfer == NULL) { 1773 /* Just ignore the change. */ 1774 return; 1775 } 1776 KASSERT(xfer == sc->sc_intrxfer); 1777 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1778 1779 p = xfer->ux_buf; 1780 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1781 memset(p, 0, xfer->ux_length); 1782 for (i = 1; i <= m; i++) { 1783 /* Pick out CHANGE bits from the status reg. */ 1784 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1785 p[i/8] |= 1 << (i%8); 1786 } 1787 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1788 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1789 xfer->ux_actlen = xfer->ux_length; 1790 xfer->ux_status = USBD_NORMAL_COMPLETION; 1791 1792 usb_transfer_complete(xfer); 1793 } 1794 1795 void 1796 ohci_root_intr_done(struct usbd_xfer *xfer) 1797 { 1798 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1799 1800 KASSERT(mutex_owned(&sc->sc_lock)); 1801 1802 /* Claim the xfer so it doesn't get completed again. */ 1803 KASSERT(sc->sc_intrxfer == xfer); 1804 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1805 sc->sc_intrxfer = NULL; 1806 } 1807 1808 void 1809 ohci_poll(struct usbd_bus *bus) 1810 { 1811 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1812 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1813 1814 #ifdef OHCI_DEBUG 1815 static int last; 1816 int new; 1817 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1818 if (new != last) { 1819 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1820 last = new; 1821 } 1822 #endif 1823 sc->sc_eintrs |= OHCI_WDH; 1824 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1825 mutex_spin_enter(&sc->sc_intr_lock); 1826 ohci_intr1(sc); 1827 mutex_spin_exit(&sc->sc_intr_lock); 1828 } 1829 } 1830 1831 /* 1832 * Add an ED to the schedule. Called with USB lock held. 1833 */ 1834 Static void 1835 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1836 { 1837 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1838 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1839 0); 1840 1841 KASSERT(mutex_owned(&sc->sc_lock)); 1842 1843 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1844 sizeof(head->ed->ed_nexted), 1845 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1846 sed->next = head->next; 1847 sed->ed->ed_nexted = head->ed->ed_nexted; 1848 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1849 sizeof(sed->ed->ed_nexted), 1850 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1851 head->next = sed; 1852 head->ed->ed_nexted = HTOO32(sed->physaddr); 1853 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1854 sizeof(head->ed->ed_nexted), 1855 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1856 } 1857 1858 /* 1859 * Remove an ED from the schedule. Called with USB lock held. 1860 */ 1861 Static void 1862 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1863 { 1864 ohci_soft_ed_t *p; 1865 1866 KASSERT(mutex_owned(&sc->sc_lock)); 1867 1868 /* XXX */ 1869 for (p = head; p != NULL && p->next != sed; p = p->next) 1870 ; 1871 KASSERT(p != NULL); 1872 1873 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1874 sizeof(sed->ed->ed_nexted), 1875 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1876 p->next = sed->next; 1877 p->ed->ed_nexted = sed->ed->ed_nexted; 1878 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1879 sizeof(p->ed->ed_nexted), 1880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1881 } 1882 1883 /* 1884 * When a transfer is completed the TD is added to the done queue by 1885 * the host controller. This queue is the processed by software. 1886 * Unfortunately the queue contains the physical address of the TD 1887 * and we have no simple way to translate this back to a kernel address. 1888 * To make the translation possible (and fast) we use a hash table of 1889 * TDs currently in the schedule. The physical address is used as the 1890 * hash value. 1891 */ 1892 1893 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1894 /* Called with USB lock held. */ 1895 void 1896 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1897 { 1898 int h = HASH(std->physaddr); 1899 1900 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1901 1902 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1903 } 1904 1905 /* Called with USB lock held. */ 1906 void 1907 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1908 { 1909 1910 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1911 1912 LIST_REMOVE(std, hnext); 1913 } 1914 1915 ohci_soft_td_t * 1916 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1917 { 1918 int h = HASH(a); 1919 ohci_soft_td_t *std; 1920 1921 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1922 std != NULL; 1923 std = LIST_NEXT(std, hnext)) 1924 if (std->physaddr == a) 1925 return std; 1926 return NULL; 1927 } 1928 1929 /* Called with USB lock held. */ 1930 void 1931 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1932 { 1933 int h = HASH(sitd->physaddr); 1934 1935 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1936 1937 KASSERT(mutex_owned(&sc->sc_lock)); 1938 1939 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1940 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1941 1942 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1943 } 1944 1945 /* Called with USB lock held. */ 1946 void 1947 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1948 { 1949 1950 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1951 1952 KASSERT(mutex_owned(&sc->sc_lock)); 1953 1954 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1955 sitd->physaddr, 0, 0); 1956 1957 LIST_REMOVE(sitd, hnext); 1958 } 1959 1960 ohci_soft_itd_t * 1961 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1962 { 1963 int h = HASH(a); 1964 ohci_soft_itd_t *sitd; 1965 1966 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1967 sitd != NULL; 1968 sitd = LIST_NEXT(sitd, hnext)) 1969 if (sitd->physaddr == a) 1970 return sitd; 1971 return NULL; 1972 } 1973 1974 #ifdef OHCI_DEBUG 1975 void 1976 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1977 { 1978 for (; std; std = std->nexttd) { 1979 ohci_dump_td(sc, std); 1980 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1981 "std %p next %p", std, std->nexttd); 1982 } 1983 } 1984 1985 void 1986 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1987 { 1988 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1989 1990 usb_syncmem(&std->dma, std->offs, sizeof(*std->td), 1991 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1992 1993 uint32_t flags = O32TOH(std->td->td_flags); 1994 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1995 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1996 !!(flags & OHCI_TD_R), 1997 OHCI_TD_GET_DP(flags), 1998 OHCI_TD_GET_DI(flags), 1999 OHCI_TD_GET_TOGGLE(flags)); 2000 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 2001 OHCI_TD_GET_CC(flags), 0, 0); 2002 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 2003 (u_long)O32TOH(std->td->td_cbp), 2004 (u_long)O32TOH(std->td->td_nexttd), 2005 (u_long)O32TOH(std->td->td_be), 0); 2006 } 2007 2008 void 2009 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2010 { 2011 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2012 2013 usb_syncmem(&sitd->dma, sitd->offs, sizeof(*sitd->itd), 2014 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2015 2016 uint32_t flags = O32TOH(sitd->itd->itd_flags); 2017 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 2018 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 2019 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2020 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2021 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 2022 O32TOH(sitd->itd->itd_bp0), 2023 O32TOH(sitd->itd->itd_nextitd), 2024 O32TOH(sitd->itd->itd_be), 0); 2025 CTASSERT(OHCI_ITD_NOFFSET == 8); 2026 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 2027 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 2028 O16TOH(sitd->itd->itd_offset[0]), 2029 O16TOH(sitd->itd->itd_offset[1]), 2030 O16TOH(sitd->itd->itd_offset[2]), 2031 O16TOH(sitd->itd->itd_offset[3])); 2032 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 2033 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 2034 O16TOH(sitd->itd->itd_offset[4]), 2035 O16TOH(sitd->itd->itd_offset[5]), 2036 O16TOH(sitd->itd->itd_offset[6]), 2037 O16TOH(sitd->itd->itd_offset[7])); 2038 } 2039 2040 void 2041 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2042 { 2043 for (; sitd; sitd = sitd->nextitd) 2044 ohci_dump_itd(sc, sitd); 2045 } 2046 2047 void 2048 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2049 { 2050 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2051 2052 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 2053 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2054 2055 uint32_t flags = O32TOH(sed->ed->ed_flags); 2056 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2057 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2058 OHCI_ED_GET_FA(flags), 2059 OHCI_ED_GET_EN(flags), 2060 OHCI_ED_GET_MAXP(flags), 2061 0); 2062 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2063 OHCI_ED_GET_DIR(flags), 2064 __SHIFTOUT(flags, OHCI_ED_SPEED), 2065 __SHIFTOUT(flags, OHCI_ED_SKIP), 2066 OHCI_ED_GET_FORMAT(flags)); 2067 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed->ed_tailp), 2068 0, 0, 0); 2069 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2070 O32TOH(sed->ed->ed_headp), O32TOH(sed->ed->ed_nexted), 2071 !!(O32TOH(sed->ed->ed_headp) & OHCI_HALTED), 2072 !!(O32TOH(sed->ed->ed_headp) & OHCI_TOGGLECARRY)); 2073 } 2074 #endif 2075 2076 usbd_status 2077 ohci_open(struct usbd_pipe *pipe) 2078 { 2079 struct usbd_device *dev = pipe->up_dev; 2080 struct usbd_bus *bus = dev->ud_bus; 2081 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2082 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2083 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2084 uint8_t addr = dev->ud_addr; 2085 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2086 ohci_soft_ed_t *sed; 2087 ohci_soft_td_t *std; 2088 ohci_soft_itd_t *sitd; 2089 ohci_physaddr_t tdphys; 2090 uint32_t fmt; 2091 usbd_status err = USBD_NOMEM; 2092 int ival; 2093 2094 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2095 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2096 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2097 2098 if (sc->sc_dying) { 2099 return USBD_IOERROR; 2100 } 2101 2102 std = NULL; 2103 sed = NULL; 2104 2105 if (addr == bus->ub_rhaddr) { 2106 switch (ed->bEndpointAddress) { 2107 case USB_CONTROL_ENDPOINT: 2108 pipe->up_methods = &roothub_ctrl_methods; 2109 break; 2110 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2111 pipe->up_methods = &ohci_root_intr_methods; 2112 break; 2113 default: 2114 err = USBD_INVAL; 2115 goto bad; 2116 } 2117 } else { 2118 sed = ohci_alloc_sed(sc); 2119 if (sed == NULL) 2120 goto bad; 2121 opipe->sed = sed; 2122 if (xfertype == UE_ISOCHRONOUS) { 2123 sitd = ohci_alloc_sitd(sc); 2124 if (sitd == NULL) 2125 goto bad; 2126 2127 opipe->tail.itd = sitd; 2128 sitd->held = &opipe->tail.itd; 2129 tdphys = sitd->physaddr; 2130 fmt = OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_ISO); 2131 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2132 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_IN); 2133 else 2134 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_OUT); 2135 } else { 2136 std = ohci_alloc_std(sc); 2137 if (std == NULL) 2138 goto bad; 2139 2140 opipe->tail.td = std; 2141 std->held = &opipe->tail.td; 2142 tdphys = std->physaddr; 2143 fmt = 2144 OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_GEN) | 2145 OHCI_ED_SET_DIR(OHCI_ED_DIR_TD); 2146 } 2147 sed->ed->ed_flags = HTOO32( 2148 OHCI_ED_SET_FA(addr) | 2149 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2150 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2151 fmt | 2152 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2153 sed->ed->ed_headp = HTOO32(tdphys | 2154 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2155 sed->ed->ed_tailp = HTOO32(tdphys); 2156 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 2157 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2158 2159 switch (xfertype) { 2160 case UE_CONTROL: 2161 pipe->up_methods = &ohci_device_ctrl_methods; 2162 int error = usb_allocmem(sc->sc_bus.ub_dmatag, 2163 sizeof(usb_device_request_t), 0, 2164 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2165 if (error) 2166 goto bad; 2167 mutex_enter(&sc->sc_lock); 2168 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2169 mutex_exit(&sc->sc_lock); 2170 break; 2171 case UE_INTERRUPT: 2172 pipe->up_methods = &ohci_device_intr_methods; 2173 ival = pipe->up_interval; 2174 if (ival == USBD_DEFAULT_INTERVAL) 2175 ival = ed->bInterval; 2176 err = ohci_device_setintr(sc, opipe, ival); 2177 if (err) 2178 goto bad; 2179 break; 2180 case UE_ISOCHRONOUS: 2181 pipe->up_serialise = false; 2182 pipe->up_methods = &ohci_device_isoc_methods; 2183 return ohci_setup_isoc(pipe); 2184 case UE_BULK: 2185 pipe->up_methods = &ohci_device_bulk_methods; 2186 mutex_enter(&sc->sc_lock); 2187 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2188 mutex_exit(&sc->sc_lock); 2189 break; 2190 } 2191 } 2192 2193 return USBD_NORMAL_COMPLETION; 2194 2195 bad: 2196 if (std != NULL) { 2197 ohci_free_std(sc, std); 2198 } 2199 if (sed != NULL) 2200 ohci_free_sed(sc, sed); 2201 return err; 2202 2203 } 2204 2205 /* 2206 * Close a regular pipe. 2207 * Assumes that there are no pending transactions. 2208 */ 2209 void 2210 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2211 { 2212 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2213 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2214 ohci_soft_ed_t *sed = opipe->sed; 2215 2216 KASSERT(mutex_owned(&sc->sc_lock)); 2217 2218 #ifdef DIAGNOSTIC 2219 // XXXNH usb_sync 2220 sed->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); 2221 if ((O32TOH(sed->ed->ed_tailp) & OHCI_HEADMASK) != 2222 (O32TOH(sed->ed->ed_headp) & OHCI_HEADMASK)) { 2223 ohci_soft_td_t *std; 2224 std = ohci_hash_find_td(sc, O32TOH(sed->ed->ed_headp)); 2225 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2226 "tl=%#x pipe=%p, std=%p\n", sed, 2227 (int)O32TOH(sed->ed->ed_headp), 2228 (int)O32TOH(sed->ed->ed_tailp), 2229 pipe, std); 2230 #ifdef OHCI_DEBUG 2231 usbd_dump_pipe(&opipe->pipe); 2232 ohci_dump_ed(sc, sed); 2233 if (std) 2234 ohci_dump_td(sc, std); 2235 #endif 2236 usb_delay_ms(&sc->sc_bus, 2); 2237 if ((O32TOH(sed->ed->ed_tailp) & OHCI_HEADMASK) != 2238 (O32TOH(sed->ed->ed_headp) & OHCI_HEADMASK)) 2239 printf("ohci_close_pipe: pipe still not empty\n"); 2240 } 2241 #endif 2242 ohci_rem_ed(sc, sed, head); 2243 /* Make sure the host controller is not touching this ED */ 2244 usb_delay_ms(&sc->sc_bus, 1); 2245 pipe->up_endpoint->ue_toggle = 2246 (O32TOH(sed->ed->ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2247 ohci_free_sed_locked(sc, opipe->sed); 2248 } 2249 2250 /* 2251 * Arrange for the hardware to tells us that it is not still processing 2252 * the TDs by setting the sKip bit and requesting a SOF interrupt 2253 * 2254 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2255 * they've been processed and either 2256 * a) if they're unused recover them for later use, or 2257 * b) if they've been used allocate new TD/iTDs to replace those 2258 * used. The softint handler will free the old ones. 2259 */ 2260 void 2261 ohci_abortx(struct usbd_xfer *xfer) 2262 { 2263 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2264 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2265 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2266 ohci_soft_ed_t *sed = opipe->sed; 2267 ohci_soft_td_t *p, *n; 2268 ohci_physaddr_t headp; 2269 int hit; 2270 2271 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2272 (uintptr_t)opipe, (uintptr_t)sed, 0); 2273 2274 KASSERT(mutex_owned(&sc->sc_lock)); 2275 ASSERT_SLEEPABLE(); 2276 2277 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2278 xfer->ux_status == USBD_TIMEOUT), 2279 "bad abort status: %d", xfer->ux_status); 2280 2281 /* 2282 * If we're dying, skip the hardware action and just notify the 2283 * software that we're done. 2284 */ 2285 if (sc->sc_dying) { 2286 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2287 xfer->ux_status, 0, 0); 2288 goto dying; 2289 } 2290 2291 /* 2292 * HC Step 1: Unless the endpoint is already halted, we set the 2293 * endpoint descriptor sKip bit and wait for hardware to complete 2294 * processing. We ensure the HC stops processing the endpoint by 2295 * waiting for the next start of frame (OHCI_SF) 2296 */ 2297 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2298 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 2299 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2300 if (!(sed->ed->ed_flags & OHCI_HALTED)) { 2301 /* force hardware skip */ 2302 DPRINTFN(1, "pausing ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2303 sed->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); 2304 usb_syncmem(&sed->dma, 2305 sed->offs + offsetof(ohci_ed_t, ed_flags), 2306 sizeof(sed->ed->ed_flags), 2307 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2308 2309 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 2310 (uintptr_t)xfer, 0, 0); 2311 2312 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2313 ox->ox_abintrs = OHCI_SF; 2314 2315 mutex_enter(&sc->sc_intr_lock); 2316 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2317 2318 /* Clear any previous SF interrupt */ 2319 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2320 2321 /* Tell interrupt handler and HC SF interrupt is requested */ 2322 sc->sc_eintrs |= OHCI_SF; 2323 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2324 /* 2325 * Step 2: Wait until we know hardware has finished any 2326 * processing of the end-point. 2327 */ 2328 while (ox->ox_abintrs != 0) { 2329 DPRINTFN(10, "SF %#jx xfer %#jx intrs %#x", 2330 (uintptr_t)sc, (uintptr_t)xfer, 2331 (uintptr_t)ox->ox_abintrs, 0); 2332 cv_wait(&sc->sc_abort_cv, &sc->sc_intr_lock); 2333 } 2334 mutex_exit(&sc->sc_intr_lock); 2335 } else { 2336 DPRINTFN(1, "halted ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2337 } 2338 2339 /* 2340 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2341 * There are two complications here 2342 * 2343 * 1) the hardware may have executed beyond the xfer we're trying to 2344 * abort. So as we're scanning the TDs of this xfer we check if 2345 * the hardware points to any of them. 2346 * 2347 * 2) the hardware may have only partially excuted the transfer 2348 * which means some TDs will appear on the done list. Wait for 2349 * WDH so we can remove them safely. 2350 */ 2351 p = xfer->ux_hcpriv; 2352 KASSERT(p); 2353 2354 #ifdef OHCI_DEBUG 2355 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2356 2357 if (ohcidebug >= 2) { 2358 DPRINTF("sed:", 0, 0, 0, 0); 2359 ohci_dump_ed(sc, sed); 2360 ohci_dump_tds(sc, p); 2361 } 2362 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2363 #endif 2364 2365 2366 #define OHCI_CC_ACCESSED_P(x) \ 2367 (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2368 2369 headp = O32TOH(sed->ed->ed_headp) & OHCI_HEADMASK; 2370 hit = 0; 2371 for (; p->xfer == xfer; p = n) { 2372 hit |= headp == p->physaddr; 2373 n = p->nexttd; 2374 2375 usb_syncmem(&p->dma, p->offs + offsetof(ohci_td_t, td_flags), 2376 sizeof(p->td->td_flags), 2377 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2378 int cc = OHCI_TD_GET_CC(O32TOH(p->td->td_flags)); 2379 if (!OHCI_CC_ACCESSED_P(cc)) { 2380 ohci_hash_rem_td(sc, p); 2381 continue; 2382 } 2383 DPRINTFN(10, "xfer=%#jx has been touched by HC", (uintptr_t)p, 2384 0, 0, 0); 2385 2386 mutex_exit(&sc->sc_lock); 2387 ohci_soft_td_t *std; 2388 for (;;) { 2389 std = ohci_alloc_std(sc); 2390 if (std) 2391 break; 2392 kpause("ohciabt2", true, hz, NULL); 2393 } 2394 2395 mutex_enter(&sc->sc_lock); 2396 if (sc->sc_dying) { 2397 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2398 xfer->ux_status, 0, 0); 2399 goto dying; 2400 } 2401 2402 DPRINTFN(10, "new std=%#jx now held at %#jx", (uintptr_t)std, 2403 (uintptr_t)p->held, 0, 0); 2404 *(p->held) = std; 2405 std->held = p->held; 2406 std->xfer = xfer; 2407 p->held = NULL; 2408 } 2409 /* Zap headp register if hardware pointed inside the xfer. */ 2410 if (hit) { 2411 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2412 (int)O32TOH(sed->ed->ed_tailp), 0, 0); 2413 /* unlink TDs, preserving toggle carry */ 2414 sed->ed->ed_headp = HTOO32(p->physaddr | 2415 (O32TOH(sed->ed->ed_headp) & OHCI_TOGGLECARRY)); 2416 usb_syncmem(&sed->dma, 2417 sed->offs + offsetof(ohci_ed_t, ed_headp), 2418 sizeof(sed->ed->ed_headp), 2419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2420 } else { 2421 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2422 } 2423 2424 /* 2425 * HC Step 4: Turn on hardware again. 2426 */ 2427 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2428 sizeof(sed->ed->ed_flags), 2429 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2430 sed->ed->ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2431 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2432 sizeof(sed->ed->ed_flags), 2433 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2434 dying: 2435 DPRINTFN(14, "end", 0, 0, 0, 0); 2436 2437 KASSERT(mutex_owned(&sc->sc_lock)); 2438 } 2439 2440 /* 2441 * Data structures and routines to emulate the root hub. 2442 */ 2443 Static int 2444 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2445 void *buf, int buflen) 2446 { 2447 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2448 usb_port_status_t ps; 2449 uint16_t len, value, index; 2450 int l, totlen = 0; 2451 int port, i; 2452 uint32_t v; 2453 2454 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2455 2456 if (sc->sc_dying) 2457 return -1; 2458 2459 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2460 req->bRequest, 0, 0); 2461 2462 len = UGETW(req->wLength); 2463 value = UGETW(req->wValue); 2464 index = UGETW(req->wIndex); 2465 2466 #define C(x,y) ((x) | ((y) << 8)) 2467 switch (C(req->bRequest, req->bmRequestType)) { 2468 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2469 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2470 if (len == 0) 2471 break; 2472 switch (value) { 2473 #define sd ((usb_string_descriptor_t *)buf) 2474 case C(2, UDESC_STRING): 2475 /* Product */ 2476 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2477 break; 2478 #undef sd 2479 default: 2480 /* default from usbroothub */ 2481 return buflen; 2482 } 2483 break; 2484 2485 /* Hub requests */ 2486 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2487 break; 2488 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2489 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2490 index, value, 0, 0); 2491 if (index < 1 || index > sc->sc_noport) { 2492 return -1; 2493 } 2494 port = OHCI_RH_PORT_STATUS(index); 2495 switch(value) { 2496 case UHF_PORT_ENABLE: 2497 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2498 break; 2499 case UHF_PORT_SUSPEND: 2500 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2501 break; 2502 case UHF_PORT_POWER: 2503 /* Yes, writing to the LOW_SPEED bit clears power. */ 2504 OWRITE4(sc, port, UPS_LOW_SPEED); 2505 break; 2506 case UHF_C_PORT_CONNECTION: 2507 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2508 break; 2509 case UHF_C_PORT_ENABLE: 2510 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2511 break; 2512 case UHF_C_PORT_SUSPEND: 2513 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2514 break; 2515 case UHF_C_PORT_OVER_CURRENT: 2516 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2517 break; 2518 case UHF_C_PORT_RESET: 2519 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2520 break; 2521 default: 2522 return -1; 2523 } 2524 switch(value) { 2525 case UHF_C_PORT_CONNECTION: 2526 case UHF_C_PORT_ENABLE: 2527 case UHF_C_PORT_SUSPEND: 2528 case UHF_C_PORT_OVER_CURRENT: 2529 case UHF_C_PORT_RESET: 2530 /* Enable RHSC interrupt if condition is cleared. */ 2531 if ((OREAD4(sc, port) >> 16) == 0) 2532 ohci_rhsc_enable(sc); 2533 break; 2534 default: 2535 break; 2536 } 2537 break; 2538 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2539 if (len == 0) 2540 break; 2541 if ((value & 0xff) != 0) { 2542 return -1; 2543 } 2544 usb_hub_descriptor_t hubd; 2545 2546 totlen = uimin(buflen, sizeof(hubd)); 2547 memcpy(&hubd, buf, totlen); 2548 2549 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2550 hubd.bNbrPorts = sc->sc_noport; 2551 USETW(hubd.wHubCharacteristics, 2552 (v & OHCI_RHD_NPS ? UHD_PWR_NO_SWITCH : 2553 v & OHCI_RHD_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2554 /* XXX overcurrent */ 2555 ); 2556 hubd.bPwrOn2PwrGood = OHCI_RHD_GET_POTPGT(v); 2557 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2558 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2559 hubd.DeviceRemovable[i++] = (uint8_t)v; 2560 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2561 totlen = uimin(totlen, hubd.bDescLength); 2562 memcpy(buf, &hubd, totlen); 2563 break; 2564 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2565 if (len != 4) { 2566 return -1; 2567 } 2568 memset(buf, 0, len); /* ? XXX */ 2569 totlen = len; 2570 break; 2571 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2572 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2573 if (index < 1 || index > sc->sc_noport) { 2574 return -1; 2575 } 2576 if (len != 4) { 2577 return -1; 2578 } 2579 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2580 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2581 USETW(ps.wPortStatus, v); 2582 USETW(ps.wPortChange, v >> 16); 2583 totlen = uimin(len, sizeof(ps)); 2584 memcpy(buf, &ps, totlen); 2585 break; 2586 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2587 return -1; 2588 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2589 break; 2590 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2591 if (index < 1 || index > sc->sc_noport) { 2592 return -1; 2593 } 2594 port = OHCI_RH_PORT_STATUS(index); 2595 switch(value) { 2596 case UHF_PORT_ENABLE: 2597 OWRITE4(sc, port, UPS_PORT_ENABLED); 2598 break; 2599 case UHF_PORT_SUSPEND: 2600 OWRITE4(sc, port, UPS_SUSPEND); 2601 break; 2602 case UHF_PORT_RESET: 2603 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2604 OWRITE4(sc, port, UPS_RESET); 2605 for (i = 0; i < 5; i++) { 2606 usb_delay_ms(&sc->sc_bus, 2607 USB_PORT_ROOT_RESET_DELAY); 2608 if (sc->sc_dying) { 2609 return -1; 2610 } 2611 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2612 break; 2613 } 2614 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2615 OREAD4(sc, port), 0, 0); 2616 break; 2617 case UHF_PORT_POWER: 2618 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2619 OWRITE4(sc, port, UPS_PORT_POWER); 2620 break; 2621 default: 2622 return -1; 2623 } 2624 break; 2625 default: 2626 /* default from usbroothub */ 2627 return buflen; 2628 } 2629 2630 return totlen; 2631 } 2632 2633 Static usbd_status 2634 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2635 { 2636 2637 /* Pipe isn't running, start first */ 2638 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2639 } 2640 2641 Static usbd_status 2642 ohci_root_intr_start(struct usbd_xfer *xfer) 2643 { 2644 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2645 2646 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2647 2648 if (sc->sc_dying) 2649 return USBD_IOERROR; 2650 2651 KASSERT(sc->sc_intrxfer == NULL); 2652 sc->sc_intrxfer = xfer; 2653 xfer->ux_status = USBD_IN_PROGRESS; 2654 2655 return USBD_IN_PROGRESS; 2656 } 2657 2658 /* Abort a root interrupt request. */ 2659 Static void 2660 ohci_root_intr_abort(struct usbd_xfer *xfer) 2661 { 2662 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2663 2664 KASSERT(mutex_owned(&sc->sc_lock)); 2665 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2666 2667 /* If xfer has already completed, nothing to do here. */ 2668 if (sc->sc_intrxfer == NULL) 2669 return; 2670 2671 /* 2672 * Otherwise, sc->sc_intrxfer had better be this transfer. 2673 * Cancel it. 2674 */ 2675 KASSERT(sc->sc_intrxfer == xfer); 2676 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2677 xfer->ux_status = USBD_CANCELLED; 2678 usb_transfer_complete(xfer); 2679 } 2680 2681 /* Close the root pipe. */ 2682 Static void 2683 ohci_root_intr_close(struct usbd_pipe *pipe) 2684 { 2685 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2686 2687 KASSERT(mutex_owned(&sc->sc_lock)); 2688 2689 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2690 2691 /* 2692 * Caller must guarantee the xfer has completed first, by 2693 * closing the pipe only after normal completion or an abort. 2694 */ 2695 KASSERT(sc->sc_intrxfer == NULL); 2696 } 2697 2698 /************************/ 2699 2700 int 2701 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2702 { 2703 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2704 usb_device_request_t *req = &xfer->ux_request; 2705 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2706 ohci_soft_td_t *stat, *setup; 2707 int isread = req->bmRequestType & UT_READ; 2708 int len = xfer->ux_bufsize; 2709 int err = ENOMEM; 2710 2711 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2712 2713 setup = ohci_alloc_std(sc); 2714 if (setup == NULL) { 2715 goto bad1; 2716 } 2717 stat = ohci_alloc_std(sc); 2718 if (stat == NULL) { 2719 goto bad2; 2720 } 2721 2722 ox->ox_setup = setup; 2723 ox->ox_stat = stat; 2724 ox->ox_nstd = 0; 2725 setup->held = &ox->ox_setup; 2726 stat->held = &ox->ox_stat; 2727 2728 DPRINTFN(10, "xfer=%#jx setup=%#jx held at %#jx", (uintptr_t)ox, 2729 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2730 DPRINTFN(10, "xfer=%#jx stat= %#jx held at %#jx", (uintptr_t)ox, 2731 (uintptr_t)stat, (uintptr_t)stat->held, 0); 2732 2733 /* Set up data transaction */ 2734 if (len != 0) { 2735 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2736 if (err) { 2737 goto bad3; 2738 } 2739 } 2740 return 0; 2741 2742 bad3: 2743 ohci_free_std(sc, stat); 2744 bad2: 2745 ohci_free_std(sc, setup); 2746 bad1: 2747 return err; 2748 } 2749 2750 void 2751 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2752 { 2753 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2754 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2755 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2756 2757 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2758 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2759 2760 mutex_enter(&sc->sc_lock); 2761 if (ox->ox_setup != opipe->tail.td) { 2762 ohci_free_std_locked(sc, ox->ox_setup); 2763 } 2764 for (size_t i = 0; i < ox->ox_nstd; i++) { 2765 ohci_soft_td_t *std = ox->ox_stds[i]; 2766 if (std == NULL) 2767 break; 2768 ohci_free_std_locked(sc, std); 2769 } 2770 ohci_free_std_locked(sc, ox->ox_stat); 2771 mutex_exit(&sc->sc_lock); 2772 2773 if (ox->ox_nstd) { 2774 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2775 kmem_free(ox->ox_stds, sz); 2776 } 2777 } 2778 2779 Static usbd_status 2780 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2781 { 2782 2783 /* Pipe isn't running, start first */ 2784 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2785 } 2786 2787 Static usbd_status 2788 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2789 { 2790 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2791 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2792 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2793 usb_device_request_t *req = &xfer->ux_request; 2794 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2795 ohci_soft_td_t *setup, *stat, *next, *tail; 2796 ohci_soft_ed_t *sed; 2797 int isread; 2798 int len; 2799 2800 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2801 2802 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2803 2804 if (sc->sc_dying) 2805 return USBD_IOERROR; 2806 2807 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2808 2809 isread = req->bmRequestType & UT_READ; 2810 len = UGETW(req->wLength); 2811 2812 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2813 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2814 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2815 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2816 UGETW(req->wIndex)); 2817 2818 /* 2819 * Use the pipe "tail" TD as our first and loan our first TD to the 2820 * next transfer 2821 */ 2822 setup = opipe->tail.td; 2823 opipe->tail.td = ox->ox_setup; 2824 ox->ox_setup = setup; 2825 setup->held = &ox->ox_setup; 2826 2827 DPRINTFN(10, "xfer=%#jx new setup=%#jx held at %#jx", (uintptr_t)ox, 2828 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2829 2830 stat = ox->ox_stat; 2831 2832 /* point at sentinel */ 2833 tail = opipe->tail.td; 2834 tail->held = &opipe->tail.td; 2835 sed = opipe->sed; 2836 2837 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", (uintptr_t)ox, 2838 (uintptr_t)tail, (uintptr_t)tail->held, 0); 2839 2840 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed->ed_flags)) == dev->ud_addr, 2841 "address ED %" __PRIuBITS " pipe %d\n", 2842 OHCI_ED_GET_FA(O32TOH(sed->ed->ed_flags)), dev->ud_addr); 2843 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed->ed_flags)) == 2844 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2845 "MPL ED %" __PRIuBITS " pipe %d\n", 2846 OHCI_ED_GET_MAXP(O32TOH(sed->ed->ed_flags)), 2847 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2848 2849 /* next will point to data if len != 0 */ 2850 next = stat; 2851 2852 /* Set up data transaction */ 2853 if (len != 0) { 2854 ohci_soft_td_t *std; 2855 ohci_soft_td_t *end; 2856 2857 next = ox->ox_stds[0]; 2858 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2859 2860 end->td->td_nexttd = HTOO32(stat->physaddr); 2861 end->nexttd = stat; 2862 2863 usb_syncmem(&end->dma, end->offs, sizeof(*end->td), 2864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2865 2866 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2867 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2868 std = ox->ox_stds[0]; 2869 /* Start toggle at 1 and then use the carried toggle. */ 2870 std->td->td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2871 std->td->td_flags |= HTOO32(OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1)); 2872 usb_syncmem(&std->dma, 2873 std->offs + offsetof(ohci_td_t, td_flags), 2874 sizeof(std->td->td_flags), 2875 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2876 } 2877 2878 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2879 (uintptr_t)setup, 2880 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2881 (uintptr_t)tail); 2882 KASSERT(opipe->tail.td == tail); 2883 2884 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2885 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2886 2887 setup->td->td_flags = HTOO32( 2888 OHCI_TD_SET_DP(OHCI_TD_DP_SETUP) | 2889 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2890 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_0) | 2891 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 2892 ); 2893 setup->td->td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2894 setup->td->td_nexttd = HTOO32(next->physaddr); 2895 setup->td->td_be = HTOO32(O32TOH(setup->td->td_cbp) + sizeof(*req) - 1); 2896 setup->nexttd = next; 2897 setup->len = 0; 2898 setup->xfer = xfer; 2899 setup->flags = 0; 2900 ohci_hash_add_td(sc, setup); 2901 2902 xfer->ux_hcpriv = setup; 2903 usb_syncmem(&setup->dma, setup->offs, sizeof(*setup->td), 2904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2905 2906 stat->td->td_flags = HTOO32( 2907 OHCI_TD_SET_DP(isread ? OHCI_TD_DP_OUT : OHCI_TD_DP_IN) | 2908 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2909 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1) | 2910 OHCI_TD_SET_DI(1) 2911 ); 2912 stat->td->td_cbp = 0; 2913 stat->td->td_nexttd = HTOO32(tail->physaddr); 2914 stat->td->td_be = 0; 2915 stat->nexttd = tail; 2916 stat->flags = OHCI_CALL_DONE; 2917 stat->len = 0; 2918 stat->xfer = xfer; 2919 ohci_hash_add_td(sc, stat); 2920 2921 usb_syncmem(&stat->dma, stat->offs, sizeof(*stat->td), 2922 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2923 2924 memset(tail->td, 0, sizeof(*tail->td)); 2925 tail->nexttd = NULL; 2926 tail->xfer = NULL; 2927 2928 usb_syncmem(&tail->dma, tail->offs, sizeof(*tail->td), 2929 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2930 2931 #ifdef OHCI_DEBUG 2932 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2933 if (ohcidebug >= 5) { 2934 ohci_dump_ed(sc, sed); 2935 ohci_dump_tds(sc, setup); 2936 } 2937 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2938 #endif 2939 2940 /* Insert ED in schedule */ 2941 sed->ed->ed_tailp = HTOO32(tail->physaddr); 2942 usb_syncmem(&sed->dma, 2943 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2944 sizeof(sed->ed->ed_tailp), 2945 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2946 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2947 xfer->ux_status = USBD_IN_PROGRESS; 2948 usbd_xfer_schedule_timeout(xfer); 2949 2950 DPRINTF("done", 0, 0, 0, 0); 2951 2952 return USBD_IN_PROGRESS; 2953 } 2954 2955 /* Abort a device control request. */ 2956 Static void 2957 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2958 { 2959 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2960 2961 KASSERT(mutex_owned(&sc->sc_lock)); 2962 2963 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2964 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2965 usbd_xfer_abort(xfer); 2966 } 2967 2968 /* Close a device control pipe. */ 2969 Static void 2970 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2971 { 2972 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2973 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2974 2975 KASSERT(mutex_owned(&sc->sc_lock)); 2976 2977 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2978 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2979 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2980 ohci_free_std_locked(sc, opipe->tail.td); 2981 2982 usb_freemem(&opipe->ctrl.reqdma); 2983 } 2984 2985 /************************/ 2986 2987 Static void 2988 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2989 { 2990 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2991 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2992 ohci_soft_ed_t *sed = opipe->sed; 2993 2994 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_headp), 2995 sizeof(sed->ed->ed_headp), 2996 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2997 2998 opipe->sed->ed->ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2999 3000 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_headp), 3001 sizeof(sed->ed->ed_headp), 3002 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3003 } 3004 3005 Static void 3006 ohci_noop(struct usbd_pipe *pipe) 3007 { 3008 } 3009 3010 Static int 3011 ohci_device_bulk_init(struct usbd_xfer *xfer) 3012 { 3013 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3014 int len = xfer->ux_bufsize; 3015 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3016 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3017 int err; 3018 3019 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3020 3021 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3022 3023 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3024 len, isread, xfer->ux_flags); 3025 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3026 3027 /* Allocate a chain of new TDs (including a new tail). */ 3028 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3029 if (err) 3030 return err; 3031 3032 return 0; 3033 } 3034 3035 Static void 3036 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3037 { 3038 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3039 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3040 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3041 3042 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3043 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3044 3045 mutex_enter(&sc->sc_lock); 3046 for (size_t i = 0; i < ox->ox_nstd; i++) { 3047 ohci_soft_td_t *std = ox->ox_stds[i]; 3048 if (std == NULL) 3049 break; 3050 if (std != opipe->tail.td) 3051 ohci_free_std_locked(sc, std); 3052 } 3053 mutex_exit(&sc->sc_lock); 3054 3055 if (ox->ox_nstd) { 3056 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3057 kmem_free(ox->ox_stds, sz); 3058 } 3059 } 3060 3061 Static usbd_status 3062 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3063 { 3064 3065 /* Pipe isn't running, start first */ 3066 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3067 } 3068 3069 Static usbd_status 3070 ohci_device_bulk_start(struct usbd_xfer *xfer) 3071 { 3072 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3073 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3074 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3075 ohci_soft_td_t *last; 3076 ohci_soft_td_t *data, *tail, *tdp; 3077 ohci_soft_ed_t *sed; 3078 int len, isread, endpt; 3079 3080 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3081 3082 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3083 3084 if (sc->sc_dying) 3085 return USBD_IOERROR; 3086 3087 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3088 3089 len = xfer->ux_length; 3090 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3091 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3092 sed = opipe->sed; 3093 3094 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3095 len, isread, xfer->ux_flags); 3096 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3097 3098 /* 3099 * Use the pipe "tail" TD as our first and loan our first TD to the 3100 * next transfer 3101 */ 3102 data = opipe->tail.td; 3103 opipe->tail.td = ox->ox_stds[0]; 3104 ox->ox_stds[0] = data; 3105 data->held = &ox->ox_stds[0]; 3106 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3107 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3108 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3109 3110 /* point at sentinel */ 3111 tail = opipe->tail.td; 3112 memset(tail->td, 0, sizeof(*tail->td)); 3113 tail->held = &opipe->tail.td; 3114 tail->nexttd = NULL; 3115 tail->xfer = NULL; 3116 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#ux", 3117 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3118 usb_syncmem(&tail->dma, tail->offs, sizeof(*tail->td), 3119 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3120 xfer->ux_hcpriv = data; 3121 3122 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3123 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3124 KASSERT(opipe->tail.td == tail); 3125 3126 /* We want interrupt at the end of the transfer. */ 3127 last->td->td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3128 last->td->td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3129 last->td->td_nexttd = HTOO32(tail->physaddr); 3130 last->nexttd = tail; 3131 last->flags |= OHCI_CALL_DONE; 3132 usb_syncmem(&last->dma, last->offs, sizeof(*last->td), 3133 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3134 3135 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3136 "td_cbp=0x%08jx td_be=0x%08jx", 3137 (int)O32TOH(sed->ed->ed_flags), 3138 (int)O32TOH(data->td->td_flags), 3139 (int)O32TOH(data->td->td_cbp), 3140 (int)O32TOH(data->td->td_be)); 3141 3142 #ifdef OHCI_DEBUG 3143 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3144 if (ohcidebug >= 5) { 3145 ohci_dump_ed(sc, sed); 3146 ohci_dump_tds(sc, data); 3147 } 3148 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3149 #endif 3150 3151 /* Insert ED in schedule */ 3152 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3153 KASSERT(tdp->xfer == xfer); 3154 } 3155 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3156 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3157 sed->ed->ed_tailp = HTOO32(tail->physaddr); 3158 sed->ed->ed_flags &= HTOO32(~OHCI_ED_SKIP); 3159 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3161 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3162 xfer->ux_status = USBD_IN_PROGRESS; 3163 usbd_xfer_schedule_timeout(xfer); 3164 3165 return USBD_IN_PROGRESS; 3166 } 3167 3168 Static void 3169 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3170 { 3171 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3172 3173 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3174 3175 KASSERT(mutex_owned(&sc->sc_lock)); 3176 3177 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3178 usbd_xfer_abort(xfer); 3179 } 3180 3181 /* 3182 * Close a device bulk pipe. 3183 */ 3184 Static void 3185 ohci_device_bulk_close(struct usbd_pipe *pipe) 3186 { 3187 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3188 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3189 3190 KASSERT(mutex_owned(&sc->sc_lock)); 3191 3192 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3193 3194 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3195 ohci_close_pipe(pipe, sc->sc_bulk_head); 3196 ohci_free_std_locked(sc, opipe->tail.td); 3197 } 3198 3199 /************************/ 3200 3201 Static int 3202 ohci_device_intr_init(struct usbd_xfer *xfer) 3203 { 3204 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3205 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3206 int len = xfer->ux_bufsize; 3207 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3208 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3209 int err; 3210 3211 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3212 3213 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3214 KASSERT(len != 0); 3215 3216 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3217 len, isread, xfer->ux_flags); 3218 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3219 3220 ox->ox_nstd = 0; 3221 3222 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3223 if (err) { 3224 return err; 3225 } 3226 3227 return 0; 3228 } 3229 3230 Static void 3231 ohci_device_intr_fini(struct usbd_xfer *xfer) 3232 { 3233 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3234 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3235 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3236 3237 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3238 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3239 3240 mutex_enter(&sc->sc_lock); 3241 for (size_t i = 0; i < ox->ox_nstd; i++) { 3242 ohci_soft_td_t *std = ox->ox_stds[i]; 3243 if (std != NULL) 3244 break; 3245 if (std != opipe->tail.td) 3246 ohci_free_std_locked(sc, std); 3247 } 3248 mutex_exit(&sc->sc_lock); 3249 3250 if (ox->ox_nstd) { 3251 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3252 kmem_free(ox->ox_stds, sz); 3253 } 3254 } 3255 3256 Static usbd_status 3257 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3258 { 3259 3260 /* Pipe isn't running, start first */ 3261 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3262 } 3263 3264 Static usbd_status 3265 ohci_device_intr_start(struct usbd_xfer *xfer) 3266 { 3267 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3268 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3269 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3270 ohci_soft_ed_t *sed = opipe->sed; 3271 ohci_soft_td_t *data, *last, *tail; 3272 int len, isread, endpt; 3273 3274 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3275 3276 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3277 3278 if (sc->sc_dying) 3279 return USBD_IOERROR; 3280 3281 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3282 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3283 3284 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3285 3286 len = xfer->ux_length; 3287 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3288 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3289 3290 /* 3291 * Use the pipe "tail" TD as our first and loan our first TD to the 3292 * next transfer. 3293 */ 3294 data = opipe->tail.td; 3295 opipe->tail.td = ox->ox_stds[0]; 3296 ox->ox_stds[0] = data; 3297 data->held = &ox->ox_stds[0]; 3298 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3299 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3300 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3301 3302 /* point at sentinel */ 3303 tail = opipe->tail.td; 3304 memset(tail->td, 0, sizeof(*tail->td)); 3305 tail->held = &opipe->tail.td; 3306 tail->nexttd = NULL; 3307 tail->xfer = NULL; 3308 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3309 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3310 usb_syncmem(&tail->dma, tail->offs, sizeof(*tail->td), 3311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3312 xfer->ux_hcpriv = data; 3313 3314 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3315 (uintptr_t)tail, 0, 0); 3316 KASSERT(opipe->tail.td == tail); 3317 3318 /* We want interrupt at the end of the transfer. */ 3319 last->td->td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3320 last->td->td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3321 3322 last->td->td_nexttd = HTOO32(tail->physaddr); 3323 last->nexttd = tail; 3324 last->flags |= OHCI_CALL_DONE; 3325 usb_syncmem(&last->dma, last->offs, sizeof(*last->td), 3326 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3327 3328 #ifdef OHCI_DEBUG 3329 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3330 if (ohcidebug >= 5) { 3331 ohci_dump_ed(sc, sed); 3332 ohci_dump_tds(sc, data); 3333 } 3334 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3335 #endif 3336 3337 /* Insert ED in schedule */ 3338 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3339 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3340 sed->ed->ed_tailp = HTOO32(tail->physaddr); 3341 sed->ed->ed_flags &= HTOO32(~OHCI_ED_SKIP); 3342 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3344 3345 xfer->ux_status = USBD_IN_PROGRESS; 3346 3347 return USBD_IN_PROGRESS; 3348 } 3349 3350 /* Abort a device interrupt request. */ 3351 Static void 3352 ohci_device_intr_abort(struct usbd_xfer *xfer) 3353 { 3354 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3355 3356 KASSERT(mutex_owned(&sc->sc_lock)); 3357 3358 usbd_xfer_abort(xfer); 3359 } 3360 3361 /* Close a device interrupt pipe. */ 3362 Static void 3363 ohci_device_intr_close(struct usbd_pipe *pipe) 3364 { 3365 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3366 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3367 int nslots = opipe->intr.nslots; 3368 int pos = opipe->intr.pos; 3369 int j; 3370 ohci_soft_ed_t *p, *sed = opipe->sed; 3371 3372 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3373 3374 KASSERT(mutex_owned(&sc->sc_lock)); 3375 3376 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3377 pos, 0); 3378 usb_syncmem(&sed->dma, sed->offs, 3379 sizeof(*sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3380 sed->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); 3381 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3382 sizeof(sed->ed->ed_flags), 3383 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3384 if ((O32TOH(sed->ed->ed_tailp) & OHCI_HEADMASK) != 3385 (O32TOH(sed->ed->ed_headp) & OHCI_HEADMASK)) 3386 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3387 3388 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3389 continue; 3390 KASSERT(p); 3391 p->next = sed->next; 3392 p->ed->ed_nexted = sed->ed->ed_nexted; 3393 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3394 sizeof(p->ed->ed_nexted), 3395 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3396 3397 for (j = 0; j < nslots; j++) 3398 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3399 3400 ohci_free_std_locked(sc, opipe->tail.td); 3401 ohci_free_sed_locked(sc, opipe->sed); 3402 } 3403 3404 Static usbd_status 3405 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3406 { 3407 int i, j, best; 3408 u_int npoll, slow, shigh, nslots; 3409 u_int bestbw, bw; 3410 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3411 3412 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3413 3414 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3415 if (ival == 0) { 3416 printf("ohci_setintr: 0 interval\n"); 3417 return USBD_INVAL; 3418 } 3419 3420 npoll = OHCI_NO_INTRS; 3421 while (npoll > ival) 3422 npoll /= 2; 3423 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3424 3425 /* 3426 * We now know which level in the tree the ED must go into. 3427 * Figure out which slot has most bandwidth left over. 3428 * Slots to examine: 3429 * npoll 3430 * 1 0 3431 * 2 1 2 3432 * 4 3 4 5 6 3433 * 8 7 8 9 10 11 12 13 14 3434 * N (N-1) .. (N-1+N-1) 3435 */ 3436 slow = npoll-1; 3437 shigh = slow + npoll; 3438 nslots = OHCI_NO_INTRS / npoll; 3439 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3440 bw = 0; 3441 for (j = 0; j < nslots; j++) 3442 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3443 if (bw < bestbw) { 3444 best = i; 3445 bestbw = bw; 3446 } 3447 } 3448 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3449 3450 mutex_enter(&sc->sc_lock); 3451 hsed = sc->sc_eds[best]; 3452 sed->next = hsed->next; 3453 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 3454 sizeof(sed->ed->ed_nexted), 3455 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3456 sed->ed->ed_nexted = hsed->ed->ed_nexted; 3457 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 3458 sizeof(sed->ed->ed_nexted), 3459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3460 3461 hsed->next = sed; 3462 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_nexted), 3463 sizeof(hsed->ed->ed_nexted), 3464 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3465 hsed->ed->ed_nexted = HTOO32(sed->physaddr); 3466 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_nexted), 3467 sizeof(hsed->ed->ed_nexted), 3468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3469 mutex_exit(&sc->sc_lock); 3470 3471 for (j = 0; j < nslots; j++) 3472 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3473 opipe->intr.nslots = nslots; 3474 opipe->intr.pos = best; 3475 3476 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3477 return USBD_NORMAL_COMPLETION; 3478 } 3479 3480 /***********************/ 3481 3482 Static int 3483 ohci_device_isoc_init(struct usbd_xfer *xfer) 3484 { 3485 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3486 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3487 ohci_soft_itd_t *sitd; 3488 size_t i; 3489 int err; 3490 3491 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3492 3493 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3494 xfer->ux_length, xfer->ux_flags, 0); 3495 3496 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3497 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3498 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3499 3500 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3501 KM_SLEEP); 3502 ox->ox_nsitd = nsitd; 3503 3504 for (i = 0; i < nsitd; i++) { 3505 /* Allocate next ITD */ 3506 sitd = ohci_alloc_sitd(sc); 3507 if (sitd == NULL) { 3508 err = ENOMEM; 3509 goto fail; 3510 } 3511 ox->ox_sitds[i] = sitd; 3512 sitd->held = &ox->ox_sitds[i]; 3513 sitd->xfer = xfer; 3514 sitd->flags = 0; 3515 // DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3516 // (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3517 } 3518 3519 return 0; 3520 fail: 3521 for (; i > 0;) { 3522 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3523 } 3524 return err; 3525 } 3526 3527 Static void 3528 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3529 { 3530 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3531 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3532 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3533 3534 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3535 3536 mutex_enter(&sc->sc_lock); 3537 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3538 if (ox->ox_sitds[i] != opipe->tail.itd) { 3539 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3540 } 3541 } 3542 mutex_exit(&sc->sc_lock); 3543 3544 if (ox->ox_nsitd) { 3545 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3546 kmem_free(ox->ox_sitds, sz); 3547 } 3548 } 3549 3550 3551 usbd_status 3552 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3553 { 3554 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3555 3556 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3557 3558 /* insert into schedule, */ 3559 ohci_device_isoc_enter(xfer); 3560 3561 /* and start if the pipe wasn't running */ 3562 return USBD_IN_PROGRESS; 3563 } 3564 3565 void 3566 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3567 { 3568 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3569 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3570 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3571 ohci_soft_ed_t *sed = opipe->sed; 3572 ohci_soft_itd_t *sitd, *nsitd, *tail; 3573 ohci_physaddr_t buf, offs, bp0, bp1; 3574 int i, ncur, nframes; 3575 size_t boff, frlen; 3576 3577 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3578 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3579 3580 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3581 3582 if (sc->sc_dying) 3583 return; 3584 3585 struct isoc *isoc = &opipe->isoc; 3586 3587 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3588 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3589 3590 int isread = 3591 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3592 3593 if (xfer->ux_length) 3594 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3595 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3596 3597 if (isoc->next == -1) { 3598 /* Not in use yet, schedule it a few frames ahead. */ 3599 usb_syncmem(&sc->sc_hccadma, 3600 offsetof(struct ohci_hcca, hcca_frame_number), 3601 sizeof(sc->sc_hcca->hcca_frame_number), 3602 BUS_DMASYNC_POSTREAD); 3603 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3604 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3605 } 3606 3607 sitd = opipe->tail.itd; 3608 opipe->tail.itd = ox->ox_sitds[0]; 3609 ox->ox_sitds[0] = sitd; 3610 sitd->held = &ox->ox_sitds[0]; 3611 3612 boff = 0; 3613 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3614 bp0 = bp1 = OHCI_PAGE(buf); 3615 offs = OHCI_PAGE_OFFSET(buf); 3616 3617 ohci_physaddr_t end = bp0; /* XXX stupid GCC */ 3618 3619 nframes = xfer->ux_nframes; 3620 xfer->ux_hcpriv = sitd; 3621 size_t j = 1; 3622 for (i = ncur = 0; i < nframes; i++, ncur++) { 3623 frlen = xfer->ux_frlengths[i]; 3624 3625 DPRINTFN(1, "frame=%jd ux_frlengths[%jd]=%jd", i, i, 3626 xfer->ux_frlengths[i], 0); 3627 /* 3628 * XXXNH: The loop assumes this is never true, because 3629 * incrementing 'i' assumes all the ux_frlengths[i] is covered. 3630 */ 3631 if (frlen > 2 * OHCI_PAGE_SIZE - offs) 3632 frlen = 2 * OHCI_PAGE_SIZE - offs; 3633 3634 boff += frlen; 3635 buf = DMAADDR(&xfer->ux_dmabuf, boff); 3636 ohci_physaddr_t noffs = OHCI_PAGE_OFFSET(buf); 3637 3638 ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1); 3639 const ohci_physaddr_t nep = OHCI_PAGE(nend); 3640 3641 /* Note the first page crossing in bp1 */ 3642 if (bp0 == bp1 && bp1 != nep) 3643 bp1 = nep; 3644 3645 DPRINTFN(1, "ncur=%jd bp0=%#jx bp1=%#jx nend=%#jx", 3646 ncur, bp0, bp1, nend); 3647 3648 /* all offsets used or too many page crossings */ 3649 if (ncur == OHCI_ITD_NOFFSET || (bp0 != bp1 && bp1 != nep)) { 3650 /* Allocate next ITD */ 3651 nsitd = ox->ox_sitds[j++]; 3652 KASSERT(nsitd != NULL); 3653 KASSERT(j < ox->ox_nsitd); 3654 3655 /* Fill current ITD */ 3656 sitd->itd->itd_flags = HTOO32( 3657 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3658 OHCI_ITD_SET_SF(isoc->next) | 3659 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3660 OHCI_ITD_SET_FC(ncur) 3661 ); 3662 sitd->itd->itd_bp0 = HTOO32(bp0); 3663 sitd->itd->itd_nextitd = HTOO32(nsitd->physaddr); 3664 sitd->itd->itd_be = HTOO32(end); 3665 sitd->nextitd = nsitd; 3666 sitd->xfer = xfer; 3667 sitd->flags = 0; 3668 #ifdef DIAGNOSTIC 3669 sitd->isdone = false; 3670 #endif 3671 ohci_hash_add_itd(sc, sitd); 3672 usb_syncmem(&sitd->dma, sitd->offs, sizeof(*sitd->itd), 3673 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3674 3675 sitd = nsitd; 3676 isoc->next = isoc->next + ncur; 3677 bp0 = bp1 = OHCI_PAGE(buf); 3678 ncur = 0; 3679 } 3680 sitd->itd->itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3681 end = nend; 3682 offs = noffs; 3683 } 3684 KASSERT(j <= ox->ox_nsitd); 3685 3686 /* point at sentinel */ 3687 tail = opipe->tail.itd; 3688 memset(tail->itd, 0, sizeof(*tail->itd)); 3689 tail->held = &opipe->tail.itd; 3690 tail->nextitd = NULL; 3691 tail->xfer = NULL; 3692 usb_syncmem(&tail->dma, tail->offs, sizeof(*tail->itd), 3693 BUS_DMASYNC_PREWRITE); 3694 3695 /* Fixup last used ITD */ 3696 sitd->itd->itd_flags = HTOO32( 3697 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3698 OHCI_ITD_SET_SF(isoc->next) | 3699 OHCI_ITD_SET_DI(0) | 3700 OHCI_ITD_SET_FC(ncur) 3701 ); 3702 sitd->itd->itd_bp0 = HTOO32(bp0); 3703 sitd->itd->itd_nextitd = HTOO32(tail->physaddr); 3704 sitd->itd->itd_be = HTOO32(end); 3705 sitd->nextitd = tail; 3706 sitd->xfer = xfer; 3707 sitd->flags = OHCI_CALL_DONE; 3708 #ifdef DIAGNOSTIC 3709 sitd->isdone = false; 3710 #endif 3711 ohci_hash_add_itd(sc, sitd); 3712 usb_syncmem(&sitd->dma, sitd->offs, sizeof(*sitd->itd), 3713 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3714 3715 isoc->next = isoc->next + ncur; 3716 isoc->inuse += nframes; 3717 3718 /* XXX pretend we did it all */ 3719 xfer->ux_actlen = offs; 3720 xfer->ux_status = USBD_IN_PROGRESS; 3721 3722 #ifdef OHCI_DEBUG 3723 if (ohcidebug >= 5) { 3724 usb_syncmem(&sc->sc_hccadma, 3725 offsetof(struct ohci_hcca, hcca_frame_number), 3726 sizeof(sc->sc_hcca->hcca_frame_number), 3727 BUS_DMASYNC_POSTREAD); 3728 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3729 0, 0, 0); 3730 ohci_dump_itds(sc, xfer->ux_hcpriv); 3731 ohci_dump_ed(sc, sed); 3732 } 3733 #endif 3734 3735 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3736 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3737 sed->ed->ed_tailp = HTOO32(tail->physaddr); 3738 sed->ed->ed_flags &= HTOO32(~OHCI_ED_SKIP); 3739 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3740 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3741 } 3742 3743 void 3744 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3745 { 3746 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3747 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3748 ohci_soft_ed_t *sed; 3749 ohci_soft_itd_t *sitd; 3750 3751 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3752 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3753 3754 KASSERT(mutex_owned(&sc->sc_lock)); 3755 3756 /* Transfer is already done. */ 3757 if (xfer->ux_status != USBD_NOT_STARTED && 3758 xfer->ux_status != USBD_IN_PROGRESS) { 3759 printf("ohci_device_isoc_abort: early return\n"); 3760 goto done; 3761 } 3762 3763 /* Give xfer the requested abort code. */ 3764 xfer->ux_status = USBD_CANCELLED; 3765 3766 sed = opipe->sed; 3767 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3768 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3769 sed->ed->ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3770 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3771 sizeof(sed->ed->ed_flags), 3772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3773 3774 sitd = xfer->ux_hcpriv; 3775 KASSERT(sitd); 3776 3777 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3778 3779 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3780 ohci_hash_rem_itd(sc, sitd); 3781 #ifdef DIAGNOSTIC 3782 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3783 0, 0, 0); 3784 sitd->isdone = true; 3785 #endif 3786 } 3787 3788 /* Run callback. */ 3789 usb_transfer_complete(xfer); 3790 3791 sed->ed->ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3792 sed->ed->ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3793 usb_syncmem(&sed->dma, sed->offs, sizeof(*sed->ed), 3794 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3795 3796 done: 3797 KASSERT(mutex_owned(&sc->sc_lock)); 3798 } 3799 3800 void 3801 ohci_device_isoc_done(struct usbd_xfer *xfer) 3802 { 3803 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3804 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3805 3806 int isread = 3807 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3808 3809 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3810 0, 0); 3811 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3812 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3813 } 3814 3815 usbd_status 3816 ohci_setup_isoc(struct usbd_pipe *pipe) 3817 { 3818 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3819 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3820 struct isoc *isoc = &opipe->isoc; 3821 3822 isoc->next = -1; 3823 isoc->inuse = 0; 3824 3825 mutex_enter(&sc->sc_lock); 3826 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3827 mutex_exit(&sc->sc_lock); 3828 3829 return USBD_NORMAL_COMPLETION; 3830 } 3831 3832 void 3833 ohci_device_isoc_close(struct usbd_pipe *pipe) 3834 { 3835 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3836 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3837 3838 KASSERT(mutex_owned(&sc->sc_lock)); 3839 3840 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3841 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3842 ohci_close_pipe(pipe, sc->sc_isoc_head); 3843 #ifdef DIAGNOSTIC 3844 opipe->tail.itd->isdone = true; 3845 #endif 3846 ohci_free_sitd_locked(sc, opipe->tail.itd); 3847 } 3848
Indexes created Sat Sep 20 22:09:52 GMT 2025