1 /* $NetBSD: alpha_instruction.h,v 1.2 2023/11/21 22:27:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Mach Operating System 35 * Copyright (c) 1993,1992 Carnegie Mellon University 36 * All Rights Reserved. 37 * 38 * Permission to use, copy, modify and distribute this software and its 39 * documentation is hereby granted, provided that both the copyright 40 * notice and this permission notice appear in all copies of the 41 * software, derivative works or modified versions, and any portions 42 * thereof, and that both notices appear in supporting documentation. 43 * 44 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 45 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 46 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 47 * 48 * Carnegie Mellon requests users of this software to return to 49 * 50 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 51 * School of Computer Science 52 * Carnegie Mellon University 53 * Pittsburgh PA 15213-3890 54 * 55 * any improvements or extensions that they make and grant Carnegie Mellon 56 * the rights to redistribute these changes. 57 */ 58 59 /* 60 * File: alpha_instruction.h 61 * Author: Alessandro Forin, Carnegie Mellon University 62 * Date: 11/91 63 * 64 * Alpha Instruction set definition 65 * 66 * Reference: "Alpha System Reference Manual", V4.0, April 1991 67 * 68 */ 69 70 #ifndef _ALPHA_INSTRUCTION_H_ 71 #define _ALPHA_INSTRUCTION_H_ 1 72 73 #if !defined(ASSEMBLER) 74 75 /* 76 * All instructions are in one of five formats: 77 * Memory, Branch, Operate, Floating-point Operate, PAL 78 * 79 * The original Mach sources attempted to use 'smarter' names 80 * for registers, which reflected source and destination. These 81 * definitions use the names from the Architecture Reference Manual, 82 * both for clarity and because you can't differentiate between 83 * 'source' and 'destinations' for some types of instructions (loads 84 * and stores; they'd be correct for one, but swapped for the other). 85 */ 86 87 88 typedef union { 89 /* 90 * All instructions are 32 bits wide 91 */ 92 unsigned int bits; 93 94 /* 95 * Generic instruction pseudo format; look at 96 * opcode to see how to interpret the rest. 97 */ 98 struct { 99 unsigned bits:26, 100 opcode:6; 101 } generic_format; 102 103 /* 104 * Memory instructions contain a 16 bit 105 * signed immediate value and two register 106 * specifiers 107 */ 108 struct { 109 signed short displacement; 110 unsigned rb : 5, 111 ra : 5, 112 opcode : 6; 113 } mem_format; 114 115 /* 116 * Branch instruction contain a 21 bit offset, 117 * which is sign-extended, shifted and combined 118 * with the PC to form a 64 bit destination address. 119 * 120 * In computed jump instructions the opcode is further 121 * specified in the offset field, the rest of it is 122 * used as branch target hint. The destination of the 123 * jump is the source register. 124 */ 125 struct { 126 signed int displacement : 21; 127 unsigned ra : 5, 128 opcode : 6; 129 } branch_format; 130 131 struct { 132 signed int hint : 14; 133 unsigned action : 2, 134 rb : 5, 135 ra : 5, 136 opcode : 6; 137 } jump_format; 138 139 140 /* 141 * Operate instructions are of two types, with 142 * a second source register or with a literal 143 * specifier. Bit 12 sez which is which. 144 */ 145 struct { 146 unsigned rc : 5, 147 function : 7, 148 is_lit : 1, 149 sbz_or_litlo : 3, 150 rb_or_lithi : 5, 151 ra : 5, 152 opcode : 6; 153 } operate_generic_format; 154 155 struct { 156 unsigned rc : 5, 157 function : 7, 158 zero : 1, 159 sbz : 3, 160 rb : 5, 161 ra : 5, 162 opcode : 6; 163 } operate_reg_format; 164 165 struct { 166 unsigned rc : 5, 167 function : 7, 168 one : 1, 169 literal : 8, 170 ra : 5, 171 opcode : 6; 172 } operate_lit_format; 173 174 175 /* 176 * Floating point operate instruction are quite 177 * uniform in the encoding. As for the semantics.. 178 */ 179 struct { 180 unsigned fc : 5, 181 function : 11, 182 fb : 5, 183 fa : 5, 184 opcode : 6; 185 } float_format; 186 187 struct { 188 unsigned fc : 5, 189 opclass : 4, 190 src : 2, 191 rnd : 2, 192 trp : 3, 193 fb : 5, 194 fa : 5, 195 opcode : 6; 196 } float_detail; 197 198 /* 199 * PAL instructions just define the major opcode 200 */ 201 202 struct { 203 unsigned function : 26, 204 opcode : 6; 205 } pal_format; 206 207 } alpha_instruction; 208 209 #endif /* !defined(ASSEMBLER) */ 210 211 /* 212 * 213 * Encoding of regular instructions (Appendix C op cit) 214 * 215 */ 216 217 /* OPCODE, bits 26..31 */ 218 219 #define op_pal 0x00 /* see PAL sub-table */ 220 /* 1..7 reserved */ 221 #define op_lda 0x08 222 #define op_ldah 0x09 223 #define op_ldbu 0x0a 224 #define op_ldq_u 0x0b 225 #define op_ldwu 0x0c 226 #define op_stw 0x0d 227 #define op_stb 0x0e 228 #define op_stq_u 0x0f 229 230 #define op_arit 0x10 /* see ARIT sub-table */ 231 #define op_logical 0x11 /* see LOGICAL sub-table */ 232 #define op_bit 0x12 /* see BIT sub-table */ 233 #define op_mul 0x13 /* see MUL sub-table */ 234 #define op_fix_float 0x14 /* if ALPHA_AMASK_FIX */ 235 #define op_vax_float 0x15 /* see FLOAT sub-table */ 236 #define op_ieee_float 0x16 /* see FLOAT sub-table */ 237 #define op_any_float 0x17 /* see FLOAT sub-table */ 238 239 #define op_special 0x18 /* see SPECIAL sub-table */ 240 #define op_pal19 0x19 /* reserved for pal code */ 241 #define op_j 0x1a /* see JUMP sub-table */ 242 #define op_pal1b 0x1b /* reserved for pal code */ 243 #define op_intmisc 0x1c /* see INTMISC sub-table */ 244 #define op_pal1d 0x1d /* reserved for pal code */ 245 #define op_pal1e 0x1e /* reserved for pal code */ 246 #define op_pal1f 0x1f /* reserved for pal code */ 247 248 #define op_ldf 0x20 249 #define op_ldg 0x21 250 #define op_lds 0x22 251 #define op_ldt 0x23 252 #define op_stf 0x24 253 #define op_stg 0x25 254 #define op_sts 0x26 255 #define op_stt 0x27 256 #define op_ldl 0x28 257 #define op_ldq 0x29 258 #define op_ldl_l 0x2a 259 #define op_ldq_l 0x2b 260 #define op_stl 0x2c 261 #define op_stq 0x2d 262 #define op_stl_c 0x2e 263 #define op_stq_c 0x2f 264 #define op_br 0x30 265 #define op_fbeq 0x31 266 #define op_fblt 0x32 267 #define op_fble 0x33 268 #define op_bsr 0x34 269 #define op_fbne 0x35 270 #define op_fbge 0x36 271 #define op_fbgt 0x37 272 #define op_blbc 0x38 273 #define op_beq 0x39 274 #define op_blt 0x3a 275 #define op_ble 0x3b 276 #define op_blbs 0x3c 277 #define op_bne 0x3d 278 #define op_bge 0x3e 279 #define op_bgt 0x3f 280 281 282 /* PAL, "function" opcodes (bits 0..25) */ 283 /* 284 * What we will implement is TBD. These are the unprivileged ones 285 * that we probably have to support for compat reasons. 286 */ 287 288 /* See <machine/pal.h> */ 289 290 /* ARIT, "function" opcodes (bits 5..11) */ 291 292 #define op_addl 0x00 293 #define op_s4addl 0x02 294 #define op_subl 0x09 295 #define op_s4subl 0x0b 296 #define op_cmpbge 0x0f 297 #define op_s8addl 0x12 298 #define op_s8subl 0x1b 299 #define op_cmpult 0x1d 300 #define op_addq 0x20 301 #define op_s4addq 0x22 302 #define op_subq 0x29 303 #define op_s4subq 0x2b 304 #define op_cmpeq 0x2d 305 #define op_s8addq 0x32 306 #define op_s8subq 0x3b 307 #define op_cmpule 0x3d 308 #define op_addl_v 0x40 309 #define op_subl_v 0x49 310 #define op_cmplt 0x4d 311 #define op_addq_v 0x60 312 #define op_subq_v 0x69 313 #define op_cmple 0x6d 314 315 316 /* LOGICAL, "function" opcodes (bits 5..11) */ 317 318 #define op_and 0x00 319 #define op_andnot 0x08 /* bic */ 320 #define op_cmovlbs 0x14 321 #define op_cmovlbc 0x16 322 #define op_or 0x20 /* bis */ 323 #define op_cmoveq 0x24 324 #define op_cmovne 0x26 325 #define op_ornot 0x28 326 #define op_xor 0x40 327 #define op_cmovlt 0x44 328 #define op_cmovge 0x46 329 #define op_xornot 0x48 /* eqv */ 330 #define op_amask 0x61 331 #define op_cmovle 0x64 332 #define op_cmovgt 0x66 333 #define op_implver 0x6c 334 335 /* BIT, "function" opcodes (bits 5..11) */ 336 337 #define op_mskbl 0x02 338 #define op_extbl 0x06 339 #define op_insbl 0x0b 340 #define op_mskwl 0x12 341 #define op_extwl 0x16 342 #define op_inswl 0x1b 343 #define op_mskll 0x22 344 #define op_extll 0x26 345 #define op_insll 0x2b 346 #define op_zap 0x30 347 #define op_zapnot 0x31 348 #define op_mskql 0x32 349 #define op_srl 0x34 350 #define op_extql 0x36 351 #define op_sll 0x39 352 #define op_insql 0x3b 353 #define op_sra 0x3c 354 #define op_mskwh 0x52 355 #define op_inswh 0x57 356 #define op_extwh 0x5a 357 #define op_msklh 0x62 358 #define op_inslh 0x67 359 #define op_extlh 0x6a 360 #define op_mskqh 0x72 361 #define op_insqh 0x77 362 #define op_extqh 0x7a 363 364 /* MUL, "function" opcodes (bits 5..11) */ 365 366 #define op_mull 0x00 367 #define op_mulq_v 0x60 368 #define op_mull_v 0x40 369 #define op_umulh 0x30 370 #define op_mulq 0x20 371 372 373 /* SPECIAL, "displacement" opcodes (bits 0..15) */ 374 375 #define op_trapb 0x0000 376 #define op_excb 0x0400 377 #define op_mb 0x4000 378 #define op_wmb 0x4400 379 #define op_fetch 0x8000 380 #define op_fetch_m 0xa000 381 #define op_rpcc 0xc000 382 #define op_rc 0xe000 383 #define op_ecb 0xe800 384 #define op_rs 0xf000 385 #define op_wh64 0xf800 386 387 /* JUMP, "action" opcodes (bits 14..15) */ 388 389 #define op_jmp 0x0 390 #define op_jsr 0x1 391 #define op_ret 0x2 392 #define op_jcr 0x3 393 394 /* INTMISC, "function" opcodes (operate format) */ 395 396 #define op_sextb 0x00 397 #define op_sextw 0x01 398 #define op_ctpop 0x30 399 #define op_perr 0x31 400 #define op_ctlz 0x32 401 #define op_cttz 0x33 402 #define op_unpkbw 0x34 403 #define op_unpkbl 0x35 404 #define op_pkwb 0x36 405 #define op_pklb 0x37 406 #define op_minsb8 0x38 407 #define op_minsw4 0x39 408 #define op_minub8 0x3a 409 #define op_minuw4 0x3b 410 #define op_maxub8 0x3c 411 #define op_maxuw4 0x3d 412 #define op_maxsb8 0x3e 413 #define op_maxsw4 0x3f 414 #define op_ftoit 0x70 415 #define op_ftois 0x78 416 417 /* 418 * 419 * Encoding of floating point instructions (pagg. C-5..6 op cit) 420 * 421 * Load and store operations use opcodes op_ldf..op_stt 422 */ 423 424 /* src encoding from function, 9..10 */ 425 #define op_src_sf 0 426 #define op_src_xd 1 427 #define op_src_tg 2 428 #define op_src_qq 3 429 430 /* any FLOAT, "function" opcodes (bits 5..11) */ 431 432 #define op_cvtlq 0x010 433 #define op_cpys 0x020 434 #define op_cpysn 0x021 435 #define op_cpyse 0x022 436 #define op_mt_fpcr 0x024 437 #define op_mf_fpcr 0x025 438 #define op_fcmoveq 0x02a 439 #define op_fcmovne 0x02b 440 #define op_fcmovlt 0x02c 441 #define op_fcmovge 0x02d 442 #define op_fcmovle 0x02e 443 #define op_fcmovgt 0x02f 444 #define op_cvtql 0x030 445 #define op_cvtql_v 0x130 446 #define op_cvtql_sv 0x530 447 448 /* FIX FLOAT, "function" opcodes (bits 5..11) */ 449 450 #define op_itofs 0x004 451 #define op_itoff 0x014 452 #define op_itoft 0x024 453 454 /* ieee FLOAT, "function" opcodes (bits 5..11) */ 455 456 #define op_adds_c 0x000 457 #define op_subs_c 0x001 458 #define op_muls_c 0x002 459 #define op_divs_c 0x003 460 #define op_addt_c 0x020 461 #define op_subt_c 0x021 462 #define op_mult_c 0x022 463 #define op_divt_c 0x023 464 #define op_cvtts_c 0x02c 465 #define op_cvttq_c 0x02f 466 #define op_cvtqs_c 0x03c 467 #define op_cvtqt_c 0x03e 468 #define op_adds_m 0x040 469 #define op_subs_m 0x041 470 #define op_muls_m 0x042 471 #define op_divs_m 0x043 472 #define op_addt_m 0x060 473 #define op_subt_m 0x061 474 #define op_mult_m 0x062 475 #define op_divt_m 0x063 476 #define op_cvtts_m 0x06c 477 #define op_cvtqs_m 0x07c 478 #define op_cvtqt_m 0x07e 479 #define op_adds 0x080 480 #define op_subs 0x081 481 #define op_muls 0x082 482 #define op_divs 0x083 483 #define op_addt 0x0a0 484 #define op_subt 0x0a1 485 #define op_mult 0x0a2 486 #define op_divt 0x0a3 487 #define op_cmptun 0x0a4 488 #define op_cmpteq 0x0a5 489 #define op_cmptlt 0x0a6 490 #define op_cmptle 0x0a7 491 #define op_cvtts 0x0ac 492 #define op_cvttq 0x0af 493 #define op_cvtqs 0x0bc 494 #define op_cvtqt 0x0be 495 #define op_adds_d 0x0c0 496 #define op_subs_d 0x0c1 497 #define op_muls_d 0x0c2 498 #define op_divs_d 0x0c3 499 #define op_addt_d 0x0e0 500 #define op_subt_d 0x0e1 501 #define op_mult_d 0x0e2 502 #define op_divt_d 0x0e3 503 #define op_cvtts_d 0x0ec 504 #define op_cvtqs_d 0x0fc 505 #define op_cvtqt_d 0x0fe 506 #define op_adds_uc 0x100 507 #define op_subs_uc 0x101 508 #define op_muls_uc 0x102 509 #define op_divs_uc 0x103 510 #define op_addt_uc 0x120 511 #define op_subt_uc 0x121 512 #define op_mult_uc 0x122 513 #define op_divt_uc 0x123 514 #define op_cvtts_uc 0x12c 515 #define op_cvttq_vc 0x12f 516 #define op_adds_um 0x140 517 #define op_subs_um 0x141 518 #define op_muls_um 0x142 519 #define op_divs_um 0x143 520 #define op_addt_um 0x160 521 #define op_subt_um 0x161 522 #define op_mult_um 0x162 523 #define op_divt_um 0x163 524 #define op_cvtts_um 0x16c 525 #define op_adds_u 0x180 526 #define op_subs_u 0x181 527 #define op_muls_u 0x182 528 #define op_divs_u 0x183 529 #define op_addt_u 0x1a0 530 #define op_subt_u 0x1a1 531 #define op_mult_u 0x1a2 532 #define op_divt_u 0x1a3 533 #define op_cvtts_u 0x1ac 534 #define op_cvttq_v 0x1af 535 #define op_adds_ud 0x1c0 536 #define op_subs_ud 0x1c1 537 #define op_muls_ud 0x1c2 538 #define op_divs_ud 0x1c3 539 #define op_addt_ud 0x1e0 540 #define op_subt_ud 0x1e1 541 #define op_mult_ud 0x1e2 542 #define op_divt_ud 0x1e3 543 #define op_cvtts_ud 0x1ec 544 #define op_cvtst 0x2ac 545 #define op_adds_suc 0x500 546 #define op_subs_suc 0x501 547 #define op_muls_suc 0x502 548 #define op_divs_suc 0x503 549 #define op_addt_suc 0x520 550 #define op_subt_suc 0x521 551 #define op_mult_suc 0x522 552 #define op_divt_suc 0x523 553 #define op_cvtts_suc 0x52c 554 #define op_cvttq_svc 0x52f 555 #define op_adds_sum 0x540 556 #define op_subs_sum 0x541 557 #define op_muls_sum 0x542 558 #define op_divs_sum 0x543 559 #define op_addt_sum 0x560 560 #define op_subt_sum 0x561 561 #define op_mult_sum 0x562 562 #define op_divt_sum 0x563 563 #define op_cvtts_sum 0x56c 564 #define op_adds_su 0x580 565 #define op_subs_su 0x581 566 #define op_muls_su 0x582 567 #define op_divs_su 0x583 568 #define op_addt_su 0x5a0 569 #define op_subt_su 0x5a1 570 #define op_mult_su 0x5a2 571 #define op_divt_su 0x5a3 572 #define op_cmptun_su 0x5a4 573 #define op_cmpteq_su 0x5a5 574 #define op_cmptlt_su 0x5a6 575 #define op_cmptle_su 0x5a7 576 #define op_cvtts_su 0x5ac 577 #define op_cvttq_sv 0x5af 578 #define op_adds_sud 0x5c0 579 #define op_subs_sud 0x5c1 580 #define op_muls_sud 0x5c2 581 #define op_divs_sud 0x5c3 582 #define op_addt_sud 0x5e0 583 #define op_subt_sud 0x5e1 584 #define op_mult_sud 0x5e2 585 #define op_divt_sud 0x5e3 586 #define op_cvtts_sud 0x5ec 587 #define op_cvtst_u 0x6ac 588 #define op_adds_suic 0x700 589 #define op_subs_suic 0x701 590 #define op_muls_suic 0x702 591 #define op_divs_suic 0x703 592 #define op_addt_suic 0x720 593 #define op_subt_suic 0x721 594 #define op_mult_suic 0x722 595 #define op_divt_suic 0x723 596 #define op_cvtts_suic 0x72c 597 #define op_cvttq_svic 0x72f 598 #define op_cvtqs_suic 0x73c 599 #define op_cvtqt_suic 0x73e 600 #define op_adds_suim 0x740 601 #define op_subs_suim 0x741 602 #define op_muls_suim 0x742 603 #define op_divs_suim 0x743 604 #define op_addt_suim 0x760 605 #define op_subt_suim 0x761 606 #define op_mult_suim 0x762 607 #define op_divt_suim 0x763 608 #define op_cvtts_suim 0x76c 609 #define op_cvtqs_suim 0x77c 610 #define op_cvtqt_suim 0x77e 611 #define op_adds_sui 0x780 612 #define op_subs_sui 0x781 613 #define op_muls_sui 0x782 614 #define op_divs_sui 0x783 615 #define op_addt_sui 0x7a0 616 #define op_subt_sui 0x7a1 617 #define op_mult_sui 0x7a2 618 #define op_divt_sui 0x7a3 619 #define op_cvtts_sui 0x7ac 620 #define op_cvttq_svi 0x7af 621 #define op_cvtqs_sui 0x7bc 622 #define op_cvtqt_sui 0x7be 623 #define op_adds_suid 0x7c0 624 #define op_subs_suid 0x7c1 625 #define op_muls_suid 0x7c2 626 #define op_divs_suid 0x7c3 627 #define op_addt_suid 0x7e0 628 #define op_subt_suid 0x7e1 629 #define op_mult_suid 0x7e2 630 #define op_divt_suid 0x7e3 631 #define op_cvtts_suid 0x7ec 632 #define op_cvtqs_suid 0x7fc 633 #define op_cvtqt_suid 0x7fe 634 635 636 /* vax FLOAT, "function" opcodes (bits 5..11) */ 637 638 #define op_addf_c 0x000 639 #define op_subf_c 0x001 640 #define op_mulf_c 0x002 641 #define op_divf_c 0x003 642 #define op_cvtdg_c 0x01e 643 #define op_addg_c 0x020 644 #define op_subg_c 0x021 645 #define op_mulg_c 0x022 646 #define op_divg_c 0x023 647 #define op_cvtgf_c 0x02c 648 #define op_cvtgd_c 0x02d 649 #define op_cvtgqg_c 0x02f 650 #define op_cvtqf_c 0x03c 651 #define op_cvtqg_c 0x03e 652 #define op_addf 0x080 653 #define op_subf 0x081 654 #define op_mulf 0x082 655 #define op_divf 0x083 656 #define op_cvtdg 0x09e 657 #define op_addg 0x0a0 658 #define op_subg 0x0a1 659 #define op_mulg 0x0a2 660 #define op_divg 0x0a3 661 #define op_cmpgeq 0x0a5 662 #define op_cmpglt 0x0a6 663 #define op_cmpgle 0x0a7 664 #define op_cvtgf 0x0ac 665 #define op_cvtgd 0x0ad 666 #define op_cvtgq 0x0af 667 #define op_cvtqf 0x0bc 668 #define op_cvtqg 0x0be 669 #define op_addf_uc 0x100 670 #define op_subf_uc 0x101 671 #define op_mulf_uc 0x102 672 #define op_divf_uc 0x103 673 #define op_cvtdg_uc 0x11e 674 #define op_addg_uc 0x120 675 #define op_subg_uc 0x121 676 #define op_mulg_uc 0x122 677 #define op_divg_uc 0x123 678 #define op_cvtgf_uc 0x12c 679 #define op_cvtgd_uc 0x12d 680 #define op_cvtgqg_vc 0x12f 681 #define op_addf_u 0x180 682 #define op_subf_u 0x181 683 #define op_mulf_u 0x182 684 #define op_divf_u 0x183 685 #define op_cvtdg_u 0x19e 686 #define op_addg_u 0x1a0 687 #define op_subg_u 0x1a1 688 #define op_mulg_u 0x1a2 689 #define op_divg_u 0x1a3 690 #define op_cvtgf_u 0x1ac 691 #define op_cvtgd_u 0x1ad 692 #define op_cvtgqg_v 0x1af 693 #define op_addf_sc 0x400 694 #define op_subf_sc 0x401 695 #define op_mulf_sc 0x402 696 #define op_divf_sc 0x403 697 #define op_cvtdg_sc 0x41e 698 #define op_addg_sc 0x420 699 #define op_subg_sc 0x421 700 #define op_mulg_sc 0x422 701 #define op_divg_sc 0x423 702 #define op_cvtgf_sc 0x42c 703 #define op_cvtgd_sc 0x42d 704 #define op_cvtgqg_sc 0x42f 705 #define op_cvtqf_sc 0x43c 706 #define op_cvtqg_sc 0x43e 707 #define op_addf_s 0x480 708 #define op_subf_s 0x481 709 #define op_mulf_s 0x482 710 #define op_divf_s 0x483 711 #define op_cvtdg_s 0x49e 712 #define op_addg_s 0x4a0 713 #define op_subg_s 0x4a1 714 #define op_mulg_s 0x4a2 715 #define op_divg_s 0x4a3 716 #define op_cmpgeq_s 0x4a5 717 #define op_cmpglt_s 0x4a6 718 #define op_cmpgle_s 0x4a7 719 #define op_cvtgf_s 0x4ac 720 #define op_cvtgd_s 0x4ad 721 #define op_cvtgqg_s 0x4af 722 #define op_cvtqf_s 0x4bc 723 #define op_cvtqg_s 0x4be 724 #define op_addf_suc 0x500 725 #define op_subf_suc 0x501 726 #define op_mulf_suc 0x502 727 #define op_divf_suc 0x503 728 #define op_cvtdg_suc 0x51e 729 #define op_addg_suc 0x520 730 #define op_subg_suc 0x521 731 #define op_mulg_suc 0x522 732 #define op_divg_suc 0x523 733 #define op_cvtgf_suc 0x52c 734 #define op_cvtgd_suc 0x52d 735 #define op_cvtgqg_svc 0x52f 736 #define op_addf_su 0x580 737 #define op_subf_su 0x581 738 #define op_mulf_su 0x582 739 #define op_divf_su 0x583 740 #define op_cvtdg_su 0x59e 741 #define op_addg_su 0x5a0 742 #define op_subg_su 0x5a1 743 #define op_mulg_su 0x5a2 744 #define op_divg_su 0x5a3 745 #define op_cvtgf_su 0x5ac 746 #define op_cvtgd_su 0x5ad 747 #define op_cvtgqg_sv 0x5af 748 749 struct alpha_print_instruction_context { 750 unsigned long pc; /* address of insn */ 751 alpha_instruction insn; /* instruction bits */ 752 char *buf; /* output buffer (if not DDB) */ 753 size_t bufsize; /* size of output buffer */ 754 size_t cursor; /* current next output location */ 755 }; 756 757 #ifdef _KERNEL 758 int alpha_print_instruction(struct alpha_print_instruction_context *); 759 #endif /* _KERNEL */ 760 761 #endif /* _ALPHA_INSTRUCTION_H_ */ 762
Indexes created Sat Sep 20 22:09:52 GMT 2025