1 /* $NetBSD: db_disasm.c,v 1.31 2023/04/12 19:47:41 riastradh Exp $ */ 2 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ 3 4 #include <sys/cdefs.h> 5 __KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.31 2023/04/12 19:47:41 riastradh Exp $"); 6 7 #ifdef _KERNEL_OPT 8 #include "opt_ppcarch.h" 9 #endif 10 11 #include <sys/param.h> 12 #include <sys/types.h> 13 14 #include <sys/proc.h> 15 #include <sys/systm.h> 16 17 #include <machine/db_machdep.h> 18 19 #include <ddb/db_access.h> 20 #include <ddb/db_sym.h> 21 #include <ddb/db_variables.h> 22 #include <ddb/db_interface.h> 23 #include <ddb/db_output.h> 24 25 enum function_mask { 26 Op_A = 0x00000001, 27 Op_B = 0x00000002, 28 Op_BI = 0x00000004, 29 Op_BO = 0x00000008, 30 Op_BC = Op_BI | Op_BO, 31 Op_CRM = 0x00000010, 32 Op_D = 0x00000020, 33 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */ 34 Op_S = 0x00000040, /* S-field is swapped with A-field */ 35 Op_FM = Op_D | Op_S, /* kludge (reduce Op_s) */ 36 Op_dA = 0x00000080, 37 Op_LK = 0x00000100, 38 Op_Rc = 0x00000200, 39 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ 40 Op_LKM = Op_AA, 41 Op_RcM = Op_AA, 42 Op_OE = 0x00000400, 43 Op_SR = 0x00000800, 44 Op_TO = 0x00001000, 45 Op_sign = 0x00002000, 46 Op_const = 0x00004000, 47 Op_SIMM = Op_const | Op_sign, 48 Op_UIMM = Op_const, 49 Op_crbA = 0x00008000, 50 Op_crbB = 0x00010000, 51 Op_WS = Op_crbB, /* kludge, same field as crbB */ 52 Op_rSH = Op_crbB, /* kludge, same field as crbB */ 53 Op_crbD = 0x00020000, 54 Op_crfD = 0x00040000, 55 Op_crfS = 0x00080000, 56 Op_ds = 0x00100000, 57 Op_me = 0x00200000, 58 Op_spr = 0x00400000, 59 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ 60 Op_tbr = 0x00800000, 61 62 Op_BP = 0x01000000, 63 Op_BD = 0x02000000, 64 Op_LI = 0x04000000, 65 Op_C = 0x08000000, 66 67 Op_NB = 0x10000000, 68 69 Op_sh_mb_sh = 0x20000000, 70 Op_sh = 0x40000000, 71 Op_SH = Op_sh | Op_sh_mb_sh, 72 Op_mb = 0x80000000, 73 Op_MB = Op_mb | Op_sh_mb_sh, 74 Op_ME = Op_MB, 75 76 }; 77 78 struct opcode { 79 const char *name; 80 u_int32_t mask; 81 u_int32_t code; 82 enum function_mask func; 83 }; 84 85 typedef u_int32_t instr_t; 86 typedef void (op_class_func) (instr_t, vaddr_t); 87 88 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); 89 void disasm_fields(const struct opcode *popcode, instr_t instr, vaddr_t loc); 90 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vaddr_t loc); 91 92 op_class_func op_ill, op_base; 93 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; 94 op_class_func op_cl_x3a, op_cl_x3b; 95 op_class_func op_cl_x3e, op_cl_x3f; 96 97 op_class_func *opcodes_base[] = { 98 /*x00*/ op_ill, op_ill, op_base, op_ill, 99 /*x04*/ op_ill, op_ill, op_ill, op_base, 100 /*x08*/ op_base, op_base, op_base, op_base, 101 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, 102 /*x10*/ op_base, op_base, op_base, op_cl_x13, 103 /*x14*/ op_base, op_base, op_ill, op_base, 104 /*x18*/ op_base, op_base, op_base, op_base, 105 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, 106 /*x20*/ op_base, op_base, op_base, op_base, 107 /*x24*/ op_base, op_base, op_base, op_base, 108 /*x28*/ op_base, op_base, op_base, op_base, 109 /*x2C*/ op_base, op_base, op_base, op_base, 110 /*x30*/ op_base, op_base, op_base, op_base, 111 /*x34*/ op_base, op_base, op_base, op_base, 112 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, 113 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f 114 }; 115 116 117 /* This table could be modified to make significant the "reserved" fields 118 * of the opcodes, But I didn't feel like it when typing in the table, 119 * I would recommend that this table be looked over for errors, 120 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) 121 * PowerPC Microprocessor Family: The Programming Environments 122 */ 123 124 const struct opcode opcodes[] = { 125 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, 126 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, 127 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, 128 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, 129 { "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM }, 130 { "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM }, 131 { "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM }, 132 { "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM }, 133 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, 134 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, 135 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, 136 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, 137 { "b", 0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */ 138 { "sc", 0xffffffff, 0x44000002, 0 }, 139 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, 140 141 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 142 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 143 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 144 145 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, 146 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, 147 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, 148 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, 149 150 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, 151 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, 152 153 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_dA }, 154 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_dA }, 155 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_dA }, 156 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_dA }, 157 { "stw", 0xfc000000, 0x90000000, Op_ST | Op_dA }, 158 { "stwu", 0xfc000000, 0x94000000, Op_ST | Op_dA }, 159 { "stb", 0xfc000000, 0x98000000, Op_ST | Op_dA }, 160 { "stbu", 0xfc000000, 0x9c000000, Op_ST | Op_dA }, 161 162 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_dA }, 163 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_dA }, 164 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_dA }, 165 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_dA }, 166 { "sth", 0xfc000000, 0xb0000000, Op_ST | Op_dA }, 167 { "sthu", 0xfc000000, 0xb4000000, Op_ST | Op_dA }, 168 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_dA }, 169 { "stmw", 0xfc000000, 0xbc000000, Op_ST | Op_dA }, 170 171 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_dA }, 172 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_dA }, 173 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_dA }, 174 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_dA }, 175 176 { "stfs", 0xfc000000, 0xd0000000, Op_ST | Op_dA }, 177 { "stfsu", 0xfc000000, 0xd4000000, Op_ST | Op_dA }, 178 { "stfd", 0xfc000000, 0xd8000000, Op_ST | Op_dA }, 179 { "stfdu", 0xfc000000, 0xdc000000, Op_ST | Op_dA }, 180 { "", 0x0, 0x0, 0 } 181 182 }; 183 /* 13 * 4 = 4c */ 184 const struct opcode opcodes_13[] = { 185 /* 0x13 << 2 */ 186 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, 187 { "b", 0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */ 188 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, 189 { "rfi", 0xfc0007fe, 0x4c000064, 0 }, 190 { "crandc", 0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB }, 191 { "isync", 0xfc0007fe, 0x4c00012c, 0 }, 192 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, 193 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, 194 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, 195 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, 196 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, 197 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, 198 { "b", 0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */ 199 { "", 0x0, 0x0, 0 } 200 }; 201 202 /* 1e * 4 = 78 */ 203 const struct opcode opcodes_1e[] = { 204 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 205 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, 206 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 207 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 208 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, 209 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 210 { "", 0x0, 0x0, 0 } 211 }; 212 213 /* 1f * 4 = 7c */ 214 const struct opcode opcodes_1f[] = { 215 /* 1f << 2 */ 216 { "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B }, 217 { "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B }, 218 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, 219 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 220 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, 221 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 222 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, 223 { "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B }, 224 { "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B }, 225 { "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B }, 226 227 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, 228 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, 229 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, 230 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, 231 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, 232 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_D | Op_A | Op_Rc }, 233 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, 234 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, 235 { "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B }, 236 { "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B }, 237 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 238 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, 239 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, 240 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, 241 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, 242 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, 243 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, 244 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, 245 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, 246 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, 247 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, 248 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, 249 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, 250 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, 251 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, 252 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, 253 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, 254 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 255 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 256 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, 257 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, 258 { "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B }, 259 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B }, 260 { "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B }, 261 { "wrteei", 0xfc0003fe, 0x7c000146, 0 }, /* XXX: out of flags! */ 262 { "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B }, 263 { "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B }, 264 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, 265 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, 266 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, 267 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B }, 268 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B }, 269 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, 270 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 271 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, 272 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 273 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, 274 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, 275 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B }, 276 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 277 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, 278 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, 279 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, 280 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, 281 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, 282 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, 283 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, 284 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, 285 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, 286 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, 287 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, 288 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, 289 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, 290 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, 291 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, 292 { "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B }, 293 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, 294 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc }, 295 { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, 296 { "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B }, 297 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, 298 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, 299 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 300 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 301 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, 302 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, 303 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, 304 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, 305 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 306 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 307 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 308 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, 309 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, 310 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, 311 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, 312 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, 313 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, 314 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, 315 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, 316 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, 317 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, 318 { "sync", 0xfc0007fe, 0x7c0004ac, 0 }, 319 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, 320 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, 321 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, 322 { "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B }, 323 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B }, 324 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B }, 325 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B }, 326 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB }, 327 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B }, 328 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B }, 329 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, 330 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, 331 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, 332 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc }, 333 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, 334 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, 335 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, 336 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B }, 337 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc }, 338 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, 339 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, 340 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, 341 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, 342 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B }, 343 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, 344 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, 345 { "", 0x0, 0x0, 0 } 346 }; 347 348 /* 3a * 4 = e8 */ 349 const struct opcode opcodes_3a[] = { 350 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, 351 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, 352 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, 353 { "", 0x0, 0x0, 0 } 354 }; 355 /* 3b * 4 = ec */ 356 const struct opcode opcodes_3b[] = { 357 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, 358 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, 359 360 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, 361 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, 362 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, 363 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, 364 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 365 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 366 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 367 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 368 { "", 0x0, 0x0, 0 } 369 }; 370 /* 3e * 4 = f8 */ 371 const struct opcode opcodes_3e[] = { 372 { "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds }, 373 { "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds }, 374 { "", 0x0, 0x0, 0 } 375 }; 376 377 /* 3f * 4 = fc */ 378 const struct opcode opcodes_3f[] = { 379 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, 380 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, 381 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, 382 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, 383 384 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, 385 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, 386 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, 387 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, 388 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 389 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, 390 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, 391 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 392 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 393 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 394 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 395 396 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, 397 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, 398 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, 399 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, 400 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, 401 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, 402 { "mtfsfi", 0xfc0007fe, 0xfc00010c, 0 }, /* XXX: out of flags! */ 403 404 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, 405 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, 406 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, 407 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, 408 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, 409 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, 410 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, 411 { "", 0x0, 0x0, 0 } 412 }; 413 414 415 struct specialreg { 416 unsigned reg; 417 const char *name; 418 }; 419 420 const struct specialreg sprregs[] = { 421 { 0x000, "mq" }, 422 { 0x001, "xer" }, 423 { 0x008, "lr" }, 424 { 0x009, "ctr" }, 425 { 0x012, "dsisr" }, 426 { 0x013, "dar" }, 427 { 0x016, "dec" }, 428 { 0x019, "sdr1" }, 429 { 0x01a, "srr0" }, 430 { 0x01b, "srr1" }, 431 #ifdef PPC_IBM4XX 432 { 0x100, "usprg0" }, 433 #else 434 { 0x100, "vrsave" }, 435 #endif 436 { 0x110, "sprg0" }, 437 { 0x111, "sprg1" }, 438 { 0x112, "sprg2" }, 439 { 0x113, "sprg3" }, 440 { 0x114, "sprg4" }, 441 { 0x115, "sprg5" }, 442 { 0x116, "sprg6" }, 443 { 0x117, "sprg7" }, 444 { 0x118, "asr" }, 445 { 0x11a, "aer" }, 446 { 0x11c, "tbl" }, 447 { 0x11d, "tbu" }, 448 { 0x11f, "pvr" }, 449 { 0x210, "ibat0u" }, 450 { 0x211, "ibat0l" }, 451 { 0x212, "ibat1u" }, 452 { 0x213, "ibat1l" }, 453 { 0x214, "ibat2u" }, 454 { 0x215, "ibat2l" }, 455 { 0x216, "ibat3u" }, 456 { 0x217, "ibat3l" }, 457 { 0x218, "dbat0u" }, 458 { 0x219, "dbat0l" }, 459 { 0x21a, "dbat1u" }, 460 { 0x21b, "dbat1l" }, 461 { 0x21c, "dbat2u" }, 462 { 0x21d, "dbat2l" }, 463 { 0x21e, "dbat3u" }, 464 { 0x21f, "dbat3l" }, 465 { 0x230, "ibat4u" }, 466 { 0x231, "ibat4l" }, 467 { 0x232, "ibat5u" }, 468 { 0x233, "ibat5l" }, 469 { 0x234, "ibat6u" }, 470 { 0x235, "ibat6l" }, 471 { 0x236, "ibat7u" }, 472 { 0x237, "ibat7l" }, 473 { 0x238, "dbat4u" }, 474 { 0x239, "dbat4l" }, 475 { 0x23a, "dbat5u" }, 476 { 0x23b, "dbat5l" }, 477 { 0x23c, "dbat6u" }, 478 { 0x23d, "dbat6l" }, 479 { 0x23e, "dbat7u" }, 480 { 0x23f, "dbat7l" }, 481 { 0x3b0, "zpr" }, 482 { 0x3b1, "pid" }, 483 { 0x3b3, "ccr0" }, 484 { 0x3b4, "iac3" }, 485 { 0x3b5, "iac4" }, 486 { 0x3b6, "dvc1" }, 487 { 0x3b7, "dvc2" }, 488 { 0x3b9, "sgr" }, 489 { 0x3ba, "dcwr" }, 490 { 0x3bb, "sler" }, 491 { 0x3bc, "su0r" }, 492 { 0x3bd, "dbcr1" }, 493 { 0x3d3, "icdbdr" }, 494 { 0x3d4, "esr" }, 495 { 0x3d5, "dear" }, 496 { 0x3d6, "evpr" }, 497 { 0x3d8, "tsr" }, 498 { 0x3da, "tcr" }, 499 { 0x3db, "pit" }, 500 { 0x3de, "srr2" }, 501 { 0x3df, "srr3" }, 502 #ifdef PPC_IBM4XX 503 { 0x3f0, "dbsr" }, 504 { 0x3f2, "dbcr0" }, 505 { 0x3f4, "iac1" }, 506 { 0x3f5, "iac2" }, 507 { 0x3f6, "dac1" }, 508 { 0x3f7, "dac2" }, 509 #else 510 { 0x3f0, "hid0" }, 511 { 0x3f1, "hid1" }, 512 { 0x3f2, "iabr" }, 513 { 0x3f3, "hid2" }, 514 { 0x3f5, "dabr" }, 515 { 0x3f6, "msscr0" }, 516 { 0x3f7, "msscr1" }, 517 #endif 518 { 0x3f9, "l2cr" }, 519 { 0x3fa, "dccr" }, 520 { 0x3fb, "iccr" }, 521 { 0x3ff, "pir" }, 522 { 0, NULL } 523 }; 524 525 const struct specialreg dcrregs[] = { 526 { 0x010, "sdram0_cfgaddr" }, 527 { 0x011, "sdram0_cfgdata" }, 528 { 0x012, "ebc0_cfgaddr" }, 529 { 0x013, "ebc0_cfgdata" }, 530 { 0x014, "dcp0_cfgaddr" }, 531 { 0x015, "dcp0_cfgdata" }, 532 { 0x018, "ocm0_isarc" }, 533 { 0x019, "ocm0_iscntl" }, 534 { 0x01a, "ocm0_dsarc" }, 535 { 0x01b, "ocm0_dscntl" }, 536 { 0x084, "plb0_besr" }, 537 { 0x086, "plb0_bear" }, 538 { 0x087, "plb0_acr" }, 539 { 0x0a0, "pob0_besr0" }, 540 { 0x0a2, "pob0_bear" }, 541 { 0x0a4, "pob0_besr1" }, 542 { 0x0b0, "cpc0_pllmr" }, 543 { 0x0b1, "cpc0_cr0" }, 544 { 0x0b2, "cpc0_cr1" }, 545 { 0x0b4, "cpc0_psr" }, 546 { 0x0b5, "cpc0_jtagid" }, 547 { 0x0b8, "cpc0_sr" }, 548 { 0x0b9, "cpc0_er" }, 549 { 0x0ba, "cpc0_fr" }, 550 { 0x0c0, "uic0_sr" }, 551 { 0x0c2, "uic0_er" }, 552 { 0x0c3, "uic0_cr" }, 553 { 0x0c4, "uic0_pr" }, 554 { 0x0c5, "uic0_tr" }, 555 { 0x0c6, "uic0_msr" }, 556 { 0x0c7, "uic0_vr" }, 557 { 0x0c8, "uic0_vcr" }, 558 { 0x100, "dma0_cr0" }, 559 { 0x101, "dma0_ct0" }, 560 { 0x102, "dma0_da0" }, 561 { 0x103, "dma0_sa0" }, 562 { 0x104, "dma0_sg0" }, 563 { 0x108, "dma0_cr1" }, 564 { 0x109, "dma0_ct1" }, 565 { 0x10a, "dma0_da1" }, 566 { 0x10b, "dma0_sa1" }, 567 { 0x10c, "dma0_sg1" }, 568 { 0x110, "dma0_cr2" }, 569 { 0x111, "dma0_ct2" }, 570 { 0x112, "dma0_da2" }, 571 { 0x113, "dma0_sa2" }, 572 { 0x114, "dma0_sg2" }, 573 { 0x118, "dma0_cr3" }, 574 { 0x119, "dma0_ct3" }, 575 { 0x11a, "dma0_da3" }, 576 { 0x11b, "dma0_sa3" }, 577 { 0x11c, "dma0_sg3" }, 578 { 0x120, "dma0_sr" }, 579 { 0x123, "dma0_sgc" }, 580 { 0x125, "dma0_slp" }, 581 { 0x126, "dma0_pol" }, 582 { 0x180, "mal0_cfg" }, 583 { 0x181, "mal0_esr" }, 584 { 0x182, "mal0_ier" }, 585 { 0x184, "mal0_txcasr" }, 586 { 0x185, "mal0_txcarr" }, 587 { 0x186, "mal0_txeobisr" }, 588 { 0x187, "mal0_txdeir" }, 589 { 0x190, "mal0_rxcasr" }, 590 { 0x191, "mal0_rxcarr" }, 591 { 0x192, "mal0_rxeobisr" }, 592 { 0x193, "mal0_rxdeir" }, 593 { 0x1a0, "mal0_txctp0r" }, 594 { 0x1a1, "mal0_txctp1r" }, 595 { 0x1a2, "mal0_txctp2r" }, 596 { 0x1a3, "mal0_txctp3r" }, 597 { 0x1c0, "mal0_rxctp0r" }, 598 { 0x1e0, "mal0_rcbs0" }, 599 { 0, NULL } 600 }; 601 602 static const char *condstr[8] = { 603 "ge", "le", "ne", "ns", "lt", "gt", "eq", "so" 604 }; 605 606 607 void 608 op_ill(instr_t instr, vaddr_t loc) 609 { 610 db_printf("illegal instruction %x\n", instr); 611 } 612 613 u_int32_t 614 extract_field(u_int32_t value, u_int32_t base, u_int32_t width) 615 { 616 u_int32_t mask = (1 << width) - 1; 617 return ((value >> base) & mask); 618 } 619 620 const struct opcode * search_op(const struct opcode *); 621 622 void 623 disasm_fields(const struct opcode *popcode, instr_t instr, vaddr_t loc) 624 { 625 enum function_mask func; 626 627 func = popcode->func; 628 if (func & Op_BC) { 629 u_int BO, BI; 630 BO = extract_field(instr, 31 - 10, 5); 631 BI = extract_field(instr, 31 - 15, 5); 632 func &= ~Op_BC; 633 if (BO & 4) { 634 /* standard, no decrement */ 635 if (BO & 16) { 636 if (popcode->code == 0x40000000) { 637 db_printf("c"); 638 func |= Op_BO | Op_BI; 639 } 640 } 641 else { 642 db_printf("%s", 643 condstr[((BO & 8) >> 1) + (BI & 3)]); 644 if (BI >= 4) 645 func |= Op_crfS; 646 } 647 } 648 else { 649 /* decrement and branch */ 650 if (BO & 2) 651 db_printf("dz"); 652 else 653 db_printf("dnz"); 654 if ((BO & 24) == 0) 655 db_printf("f"); 656 else if ((BO & 24) == 8) 657 db_printf("t"); 658 else 659 func |= Op_BI; 660 } 661 if (popcode->code == 0x4c000020) 662 db_printf("lr"); 663 else if (popcode->code == 0x4c000420) 664 db_printf("ctr"); 665 if ((BO & 20) != 20 && (func & Op_BO) == 0) 666 func |= Op_BP; /* branch prediction hint */ 667 } 668 if (func & Op_OE) { 669 u_int OE; 670 OE = extract_field(instr, 31 - 21, 1); 671 if (OE) { 672 db_printf("o"); 673 } 674 func &= ~Op_OE; 675 } 676 switch (func & Op_LKM) { 677 case Op_Rc: 678 if (instr & 0x1) 679 db_printf("."); 680 break; 681 case Op_AA: 682 if (instr & 0x1) 683 db_printf("l"); 684 if (instr & 0x2) { 685 db_printf("a"); 686 loc = 0; /* Absolute address */ 687 } 688 break; 689 case Op_LK: 690 if (instr & 0x1) 691 db_printf("l"); 692 break; 693 default: 694 func &= ~Op_LKM; 695 } 696 if (func & Op_BP) { 697 int y; 698 y = (instr & 0x200000) != 0; 699 if (popcode->code == 0x40000000) { 700 int BD; 701 BD = extract_field(instr, 31 - 29, 14); 702 BD = BD << 18; 703 BD = BD >> 16; 704 BD += loc; 705 if ((vaddr_t)BD < loc) 706 y ^= 1; 707 } 708 db_printf("%c", y ? '+' : '-'); 709 func &= ~Op_BP; 710 } 711 db_printf("\t"); 712 713 /* XXX: special cases here, out of flags in a 32bit word. */ 714 if (strcmp(popcode->name, "wrteei") == 0) { 715 int E; 716 E = extract_field(instr, 31 - 16, 5); 717 db_printf("%d", E); 718 return; 719 } 720 else if (strcmp(popcode->name, "mtfsfi") == 0) { 721 u_int UI; 722 UI = extract_field(instr, 31 - 8, 3); 723 db_printf("crf%u, ", UI); 724 UI = extract_field(instr, 31 - 19, 4); 725 db_printf("0x%x", UI); 726 } 727 /* XXX: end of special cases here. */ 728 729 if ((func & Op_FM) == Op_FM) { 730 u_int FM; 731 FM = extract_field(instr, 31 - 14, 8); 732 db_printf("0x%x, ", FM); 733 func &= ~Op_FM; 734 } 735 if (func & Op_D) { /* Op_ST is the same */ 736 u_int D; 737 D = extract_field(instr, 31 - 10, 5); 738 db_printf("r%d, ", D); 739 func &= ~Op_D; 740 } 741 if (func & Op_crbD) { 742 u_int crbD; 743 crbD = extract_field(instr, 31 - 10, 5); 744 db_printf("crb%d, ", crbD); 745 func &= ~Op_crbD; 746 } 747 if (func & Op_crfD) { 748 u_int crfD; 749 crfD = extract_field(instr, 31 - 8, 3); 750 db_printf("crf%d, ", crfD); 751 func &= ~Op_crfD; 752 } 753 if (func & Op_TO) { 754 u_int TO; 755 TO = extract_field(instr, 31 - 10, 1); 756 db_printf("%d, ", TO); 757 func &= ~Op_TO; 758 } 759 if (func & Op_crfS) { 760 u_int crfS; 761 crfS = extract_field(instr, 31 - 13, 3); 762 db_printf("crf%d, ", crfS); 763 func &= ~Op_crfS; 764 } 765 if (func & Op_CRM) { 766 u_int CRM; 767 CRM = extract_field(instr, 31 - 19, 8); 768 db_printf("0x%x, ", CRM); 769 func &= ~Op_CRM; 770 } 771 if (func & Op_BO) { 772 u_int BO; 773 BO = extract_field(instr, 31 - 10, 5); 774 db_printf("%d, ", BO); 775 func &= ~Op_BO; 776 } 777 if (func & Op_BI) { 778 u_int BI; 779 BI = extract_field(instr, 31 - 15, 5); 780 db_printf("%d, ", BI); 781 func &= ~Op_BI; 782 } 783 if (func & Op_dA) { /* register A indirect with displacement */ 784 u_int A; 785 A = extract_field(instr, 31 - 31, 16); 786 if (A & 0x8000) { 787 db_printf("-"); 788 A = 0x10000-A; 789 } 790 db_printf("0x%x", A); 791 A = extract_field(instr, 31 - 15, 5); 792 db_printf("(r%d)", A); 793 func &= ~Op_dA; 794 } 795 if (func & Op_spr) { 796 u_int spr; 797 u_int sprl; 798 u_int sprh; 799 const struct specialreg *regs; 800 int i; 801 sprl = extract_field(instr, 31 - 15, 5); 802 sprh = extract_field(instr, 31 - 20, 5); 803 spr = sprh << 5 | sprl; 804 805 /* ugly hack - out of bitfields in the function mask */ 806 if (popcode->name[2] == 'd') /* m.Dcr */ 807 regs = dcrregs; 808 else 809 regs = sprregs; 810 for (i = 0; regs[i].name != NULL; i++) 811 if (spr == regs[i].reg) 812 break; 813 if (regs[i].name == NULL) 814 db_printf("[unknown special reg (%d)]", spr); 815 else 816 db_printf("%s", regs[i].name); 817 818 if (popcode->name[1] == 't') /* spr is destination */ 819 db_printf(", "); 820 func &= ~Op_spr; 821 } 822 if (func & Op_SR) { 823 u_int SR; 824 SR = extract_field(instr, 31 - 15, 3); 825 db_printf("sr%d", SR); 826 if (popcode->name[1] == 't') /* SR is destination */ 827 db_printf(", "); 828 func &= ~Op_SR; 829 } 830 if (func & Op_A) { 831 u_int A; 832 A = extract_field(instr, 31 - 15, 5); 833 db_printf("r%d, ", A); 834 func &= ~Op_A; 835 } 836 if (func & Op_S) { 837 u_int D; 838 D = extract_field(instr, 31 - 10, 5); 839 db_printf("r%d, ", D); 840 func &= ~Op_S; 841 } 842 if (func & Op_C) { 843 u_int C; 844 C = extract_field(instr, 31 - 25, 5); 845 db_printf("r%d, ", C); 846 func &= ~Op_C; 847 } 848 if (func & Op_B) { 849 u_int B; 850 B = extract_field(instr, 31 - 20, 5); 851 db_printf("r%d", B); 852 func &= ~Op_B; 853 } 854 if (func & Op_crbA) { 855 u_int crbA; 856 crbA = extract_field(instr, 31 - 15, 5); 857 db_printf("%d, ", crbA); 858 func &= ~Op_crbA; 859 } 860 if (func & Op_crbB) { 861 u_int crbB; 862 crbB = extract_field(instr, 31 - 20, 5); 863 db_printf("%d, ", crbB); 864 func &= ~Op_crbB; 865 } 866 if (func & Op_LI) { 867 int LI; 868 LI = extract_field(instr, 31 - 29, 24); 869 /* Need to sign extend and shift up 2, then add addr */ 870 LI = LI << 8; 871 LI = LI >> 6; 872 LI += loc; 873 db_printsym(LI, DB_STGY_ANY, db_printf); 874 func &= ~Op_LI; 875 } 876 switch (func & Op_SIMM) { 877 u_int IMM; 878 case Op_SIMM: /* same as Op_d */ 879 IMM = extract_field(instr, 31 - 31, 16); 880 if (IMM & 0x8000) { 881 db_printf("-"); 882 IMM = 0x10000-IMM; 883 } 884 func &= ~Op_SIMM; 885 goto common; 886 case Op_UIMM: 887 IMM = extract_field(instr, 31 - 31, 16); 888 func &= ~Op_UIMM; 889 goto common; 890 common: 891 db_printf("0x%x", IMM); 892 break; 893 default: 894 ; 895 } 896 if (func & Op_BD) { 897 int BD; 898 BD = extract_field(instr, 31 - 29, 14); 899 /* Need to sign extend and shift up 2, then add addr */ 900 BD = BD << 18; 901 BD = BD >> 16; 902 BD += loc; 903 db_printsym(BD, DB_STGY_ANY, db_printf); 904 func &= ~Op_BD; 905 } 906 if (func & Op_ds) { 907 u_int ds; 908 ds = extract_field(instr, 31 - 29, 14) << 2; 909 db_printf("0x%x", ds); 910 func &= ~Op_ds; 911 } 912 if (func & Op_me) { 913 u_int me, mel, meh; 914 mel = extract_field(instr, 31 - 25, 4); 915 meh = extract_field(instr, 31 - 26, 1); 916 me = meh << 4 | mel; 917 db_printf(", 0x%x", me); 918 func &= ~Op_me; 919 } 920 if ((func & Op_SH) && (func & Op_sh_mb_sh)) { 921 u_int SH; 922 SH = extract_field(instr, 31 - 20, 5); 923 db_printf("%d", SH); 924 } 925 if ((func & Op_MB) && (func & Op_sh_mb_sh)) { 926 u_int MB; 927 u_int ME; 928 MB = extract_field(instr, 31 - 25, 5); 929 db_printf(", %d", MB); 930 ME = extract_field(instr, 31 - 30, 5); 931 db_printf(", %d", ME); 932 } 933 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { 934 u_int sh, shl, shh; 935 shl = extract_field(instr, 31 - 19, 4); 936 shh = extract_field(instr, 31 - 20, 1); 937 sh = shh << 4 | shl; 938 db_printf(", %d", sh); 939 } 940 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { 941 u_int mb, mbl, mbh; 942 mbl = extract_field(instr, 31 - 25, 4); 943 mbh = extract_field(instr, 31 - 26, 1); 944 mb = mbh << 4 | mbl; 945 db_printf(", %d", mb); 946 } 947 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { 948 u_int me, mel, meh; 949 mel = extract_field(instr, 31 - 25, 4); 950 meh = extract_field(instr, 31 - 26, 1); 951 me = meh << 4 | mel; 952 db_printf(", %d", me); 953 } 954 if (func & Op_tbr) { 955 u_int tbr; 956 u_int tbrl; 957 u_int tbrh; 958 const char *reg; 959 tbrl = extract_field(instr, 31 - 15, 5); 960 tbrh = extract_field(instr, 31 - 20, 5); 961 tbr = tbrh << 5 | tbrl; 962 963 switch (tbr) { 964 case 268: 965 reg = "tbl"; 966 break; 967 case 269: 968 reg = "tbu"; 969 break; 970 default: 971 reg = 0; 972 } 973 if (reg == 0) 974 db_printf(", [unknown tbr %d ]", tbr); 975 else 976 db_printf(", %s", reg); 977 func &= ~Op_tbr; 978 } 979 if (func & Op_NB) { 980 u_int NB; 981 NB = extract_field(instr, 31 - 20, 5); 982 if (NB == 0) 983 NB = 32; 984 db_printf(", %d", NB); 985 func &= ~Op_SR; 986 } 987 } 988 989 void 990 op_base(instr_t instr, vaddr_t loc) 991 { 992 dis_ppc(opcodes, instr, loc); 993 } 994 995 void 996 op_cl_x13(instr_t instr, vaddr_t loc) 997 { 998 dis_ppc(opcodes_13, instr, loc); 999 } 1000 1001 void 1002 op_cl_x1e(instr_t instr, vaddr_t loc) 1003 { 1004 dis_ppc(opcodes_1e, instr, loc); 1005 } 1006 1007 void 1008 op_cl_x1f(instr_t instr, vaddr_t loc) 1009 { 1010 dis_ppc(opcodes_1f, instr, loc); 1011 } 1012 1013 void 1014 op_cl_x3a(instr_t instr, vaddr_t loc) 1015 { 1016 dis_ppc(opcodes_3a, instr, loc); 1017 } 1018 1019 void 1020 op_cl_x3b(instr_t instr, vaddr_t loc) 1021 { 1022 dis_ppc(opcodes_3b, instr, loc); 1023 } 1024 1025 void 1026 op_cl_x3e(instr_t instr, vaddr_t loc) 1027 { 1028 dis_ppc(opcodes_3e, instr, loc); 1029 } 1030 1031 void 1032 op_cl_x3f(instr_t instr, vaddr_t loc) 1033 { 1034 dis_ppc(opcodes_3f, instr, loc); 1035 } 1036 1037 void 1038 dis_ppc(const struct opcode *opcodeset, instr_t instr, vaddr_t loc) 1039 { 1040 const struct opcode *op; 1041 int found = 0; 1042 int i; 1043 1044 for (i = 0, op = &opcodeset[0]; 1045 found == 0 && op->mask != 0; 1046 i++, op = &opcodeset[i]) { 1047 if ((instr & op->mask) == op->code) { 1048 found = 1; 1049 db_printf("%s", op->name); 1050 disasm_fields(op, instr, loc); 1051 return; 1052 } 1053 } 1054 op_ill(instr, loc); 1055 } 1056 1057 db_addr_t 1058 db_disasm(db_addr_t loc, bool extended) 1059 { 1060 int class; 1061 instr_t opcode; 1062 1063 db_read_bytes(loc, sizeof(opcode), (char *)&opcode); 1064 class = opcode >> 26; 1065 (opcodes_base[class])(opcode, loc); 1066 1067 return (loc + 4); 1068 } 1069 1070 vaddr_t opc_disasm(vaddr_t loc, int); 1071 1072 vaddr_t 1073 opc_disasm(vaddr_t loc, int xin) 1074 { 1075 int class; 1076 instr_t opcode; 1077 opcode = xin; 1078 class = opcode >> 26; 1079 (opcodes_base[class])(opcode, loc); 1080 1081 return (loc + 4); 1082 } 1083
Indexes created Sat Sep 20 22:09:52 GMT 2025