| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_mpc.c | 142 unsigned int opp_id; local in function:mpc1_is_mpcc_idle
146 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
148 if (top_sel == 0xf && opp_id == 0xf && idle)
229 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
235 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
291 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
295 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
362 int opp_id; local in function:mpc1_mpc_init
373 for (opp_id = 0; opp_id < MAX_OPP; opp_id++)
382 int opp_id; local in function:mpc1_mpc_init_single_inst
402 unsigned int opp_id; local in function:mpc1_init_mpcc_list_from_hw
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 335 if (s.opp_id != 0xf)
337 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
1088 int opp_id = hubp->opp_id; local in function:dcn10_plane_atomic_disable
1096 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
1217 hubp->opp_id = OPP_ID_INVALID;
1220 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2017 int opp_id)
2217 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2562 * fairly hacky right now, using opp_id as indicato
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| hubp.h | 62 int opp_id; member in struct:hubp
|
| mpc.h | 116 int opp_id; /* The OPP instance that owns this MPC tree */ member in struct:mpc_tree
130 uint32_t opp_id; member in struct:mpcc_state
228 int opp_id,
233 int opp_id,
237 int opp_id,
242 int opp_id,
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