1 /* 2 * Copyright 1999 through 2004 by Marc Aurele La France (TSI @ UQV), tsi (at) xfree86.org 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of Marc Aurele La France not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. Marc Aurele La France makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as-is" without express or implied warranty. 13 * 14 * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO 16 * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 * 22 * DRI support by: 23 * Gareth Hughes <gareth (at) valinux.com> 24 * Leif Delgass <ldelgass (at) retinalburn.net> 25 */ 26 27 #ifndef ___ATISTRUCT_H___ 28 #define ___ATISTRUCT_H___ 1 29 30 #include "atibank.h" 31 #include "aticlock.h" 32 #include "atiregs.h" 33 34 #ifdef XF86DRI_DEVEL 35 36 /* 37 * DRI support 38 */ 39 #define _XF86DRI_SERVER_ 40 #include "atidripriv.h" 41 #include "mach64_dri.h" 42 #include "sarea.h" 43 #include "xf86drm.h" 44 #include "dri.h" 45 46 #endif /* XF86DRI_DEVEL */ 47 48 #ifdef TV_OUT 49 50 #include "vbe.h" 51 52 #endif /* TV_OUT */ 53 54 #include "picturestr.h" 55 #ifdef USE_EXA 56 #include "exa.h" 57 #endif 58 #include "xf86Cursor.h" 59 #include "xf86Pci.h" 60 61 #include "atipcirename.h" 62 63 #include "compat-api.h" 64 65 #define CacheSlotOf(____Register) ((____Register) / UnitOf(DWORD_SELECT)) 66 67 /* 68 * This is probably as good a place as any to put this note, as it applies to 69 * the entire driver, but especially here. CARD8's are used rather than the 70 * appropriate enum types because the latter would nearly quadruple storage 71 * requirements (they are stored as int's). This reduces the usefulness of 72 * enum types to their ability to declare index values. I've also elected to 73 * forgo the strong typing capabilities of enum types. C is not terribly adept 74 * at strong typing anyway. 75 */ 76 77 /* A structure for local data related to video modes */ 78 typedef struct _ATIHWRec 79 { 80 /* Clock number for mode */ 81 CARD8 clock; 82 83 /* The CRTC used to drive the screen (VGA, 8514, Mach64) */ 84 CARD8 crtc; 85 86 /* Colour lookup table */ 87 CARD8 lut[256 * 3]; 88 89 #ifndef AVOID_CPIO 90 91 /* VGA registers */ 92 CARD8 genmo, crt[25], seq[5], gra[9], attr[21]; 93 94 /* VGA Wonder registers */ 95 CARD8 a3, a6, a7, ab, ac, ad, ae, 96 b0, b1, b2, b3, b5, b6, b8, b9, ba, bd, be, bf; 97 98 /* Shadow VGA CRTC registers */ 99 CARD8 shadow_vga[25]; 100 101 #endif /* AVOID_CPIO */ 102 103 /* Generic DAC registers */ 104 CARD8 dac_read, dac_write, dac_mask; 105 106 /* IBM RGB 514 registers */ 107 CARD8 ibmrgb514[0x0092U]; /* All that's needed for now */ 108 109 /* Mach64 PLL registers */ 110 CARD8 pll_vclk_cntl, pll_vclk_post_div, 111 pll_vclk0_fb_div, pll_vclk1_fb_div, 112 pll_vclk2_fb_div, pll_vclk3_fb_div, 113 pll_xclk_cntl, pll_ext_vpll_cntl; 114 115 /* Mach64 CPIO registers */ 116 CARD32 crtc_h_total_disp, crtc_h_sync_strt_wid, 117 crtc_v_total_disp, crtc_v_sync_strt_wid, 118 crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off, mem_buf_cntl, 119 ovr_clr, ovr_wid_left_right, ovr_wid_top_bottom, 120 cur_clr0, cur_clr1, cur_offset, 121 cur_horz_vert_posn, cur_horz_vert_off, 122 clock_cntl, bus_cntl, mem_cntl, mem_vga_wp_sel, mem_vga_rp_sel, 123 dac_cntl, gen_test_cntl, config_cntl, mpp_config, mpp_strobe_seq, 124 tvo_cntl; 125 126 /* LCD registers */ 127 CARD32 lcd_index, config_panel, lcd_gen_ctrl, 128 horz_stretching, vert_stretching, ext_vert_stretch; 129 130 /* Shadow Mach64 CRTC registers */ 131 CARD32 shadow_h_total_disp, shadow_h_sync_strt_wid, 132 shadow_v_total_disp, shadow_v_sync_strt_wid; 133 134 /* Mach64 MMIO Block 0 registers and related subfields */ 135 CARD32 dst_off_pitch; 136 CARD16 dst_x, dst_y, dst_height; 137 CARD32 dst_bres_err, dst_bres_inc, dst_bres_dec, dst_cntl; 138 CARD32 src_off_pitch; 139 CARD16 src_x, src_y, src_width1, src_height1, 140 src_x_start, src_y_start, src_width2, src_height2; 141 CARD32 src_cntl; 142 CARD32 host_cntl; 143 CARD32 pat_reg0, pat_reg1, pat_cntl; 144 CARD16 sc_left, sc_right, sc_top, sc_bottom; 145 CARD32 dp_bkgd_clr, dp_frgd_clr, dp_write_mask, dp_chain_mask, 146 dp_pix_width, dp_mix, dp_src; 147 CARD32 clr_cmp_clr, clr_cmp_msk, clr_cmp_cntl; 148 CARD32 context_mask, context_load_cntl; 149 150 CARD32 scale_3d_cntl, tex_size_pitch, tex_cntl, tex_offset; 151 152 /* Mach64 MMIO Block 1 registers */ 153 CARD32 overlay_y_x_start, overlay_y_x_end, overlay_graphics_key_clr, 154 overlay_graphics_key_msk, overlay_key_cntl, overlay_scale_inc, 155 overlay_scale_cntl, scaler_height_width, scaler_test, 156 scaler_buf0_offset, scaler_buf1_offset, scaler_buf_pitch, 157 video_format, overlay_exclusive_horz, overlay_exclusive_vert, 158 buf0_offset, buf0_pitch, buf1_offset, buf1_pitch, 159 scaler_colour_cntl, scaler_h_coeff0, scaler_h_coeff1, 160 scaler_h_coeff2, scaler_h_coeff3, scaler_h_coeff4, gui_cntl, 161 scaler_buf0_offset_u, scaler_buf0_offset_v, scaler_buf1_offset_u, 162 scaler_buf1_offset_v; 163 164 /* Clock programming data */ 165 int FeedbackDivider, ReferenceDivider, PostDivider; 166 167 #ifndef AVOID_CPIO 168 169 /* This is used by ATISwap() */ 170 pointer frame_buffer; 171 ATIBankProcPtr SetBank; 172 unsigned int nBank, nPlane; 173 174 #endif /* AVOID_CPIO */ 175 176 } ATIHWRec; 177 178 #ifdef USE_EXA 179 /* 180 * Card engine state for communication across RENDER acceleration hooks. 181 */ 182 typedef struct _Mach64ContextRegs3D 183 { 184 CARD32 dp_mix; 185 CARD32 dp_src; 186 CARD32 dp_write_mask; 187 CARD32 dp_pix_width; 188 CARD32 dst_pitch_offset; 189 190 CARD32 scale_3d_cntl; 191 192 CARD32 tex_cntl; 193 CARD32 tex_size_pitch; 194 CARD32 tex_offset; 195 196 int tex_width; /* src/mask texture width (pixels) */ 197 int tex_height; /* src/mask texture height (pixels) */ 198 199 Bool frag_src; /* solid src uses fragment color */ 200 Bool frag_mask; /* solid mask uses fragment color */ 201 CARD32 frag_color; /* solid src/mask color */ 202 203 Bool color_alpha; /* the alpha value is contained in the color 204 channels instead of the alpha channel */ 205 206 PictTransform *transform; 207 } Mach64ContextRegs3D; 208 #endif /* USE_EXA */ 209 210 /* 211 * This structure defines the driver's private area. 212 */ 213 typedef struct _ATIRec 214 { 215 216 #ifndef AVOID_CPIO 217 218 CARD8 VGAAdapter; 219 220 #endif /* AVOID_CPIO */ 221 222 /* 223 * Chip-related definitions. 224 */ 225 CARD32 config_chip_id; 226 CARD16 ChipType; 227 CARD8 Chip; 228 CARD8 ChipClass, ChipRevision, ChipRev, ChipVersion, ChipFoundry; 229 230 /* 231 * Processor I/O decoding definitions. 232 */ 233 CARD8 CPIODecoding; 234 unsigned long CPIOBase; 235 236 #ifndef AVOID_CPIO 237 238 /* 239 * Processor I/O port definition for VGA. 240 */ 241 unsigned long CPIO_VGABase; 242 243 /* 244 * Processor I/O port definitions for VGA Wonder. 245 */ 246 unsigned long CPIO_VGAWonder; 247 248 #endif /* AVOID_CPIO */ 249 250 /* 251 * DAC-related definitions. 252 */ 253 254 #ifndef AVOID_CPIO 255 256 unsigned long CPIO_DAC_MASK, CPIO_DAC_DATA, CPIO_DAC_READ, CPIO_DAC_WRITE, 257 CPIO_DAC_WAIT; 258 259 #endif /* AVOID_CPIO */ 260 261 CARD16 DAC; 262 CARD8 rgbBits; 263 264 /* 265 * Definitions related to system bus interface. 266 */ 267 pciVideoPtr PCIInfo; 268 CARD8 BusType; 269 270 #ifndef AVOID_CPIO 271 #ifndef XSERVER_LIBPCIACCESS 272 resRange VGAWonderResources[2]; 273 #endif 274 #endif /* AVOID_CPIO */ 275 276 /* 277 * Definitions related to video memory. 278 */ 279 CARD8 MemoryType; 280 int VideoRAM; 281 282 /* 283 * BIOS-related definitions. 284 */ 285 CARD8 I2CType, Tuner, Decoder, Audio; 286 287 /* 288 * Definitions related to video memory apertures. 289 */ 290 pointer pMemory, pShadow; 291 pointer pMemoryLE; /* Always little-endian */ 292 unsigned long LinearBase; 293 int LinearSize, FBPitch, FBBytesPerPixel; 294 295 #ifndef AVOID_CPIO 296 297 /* 298 * Banking interface. 299 */ 300 pointer pBank; 301 302 #endif /* AVOID_CPIO */ 303 304 /* 305 * Definitions related to MMIO register apertures. 306 */ 307 pointer pMMIO, pBlock[2]; 308 unsigned long Block0Base, Block1Base; 309 310 /* 311 * EXA interface. 312 */ 313 Bool useEXA; 314 #ifdef USE_EXA 315 ExaDriverPtr pExa; 316 #endif 317 int nAvailableFIFOEntries, nFIFOEntries, nHostFIFOEntries; 318 CARD8 EngineIsBusy, EngineIsLocked, XModifier; 319 CARD32 dst_cntl; /* For SetupFor/Subsequent communication */ 320 CARD32 sc_left_right, sc_top_bottom; 321 CARD16 sc_left, sc_right, sc_top, sc_bottom; /* Current scissors */ 322 pointer pHOST_DATA; /* Current HOST_DATA_* transfer window address */ 323 #ifdef USE_EXA 324 Bool RenderAccelEnabled; 325 Mach64ContextRegs3D m3d; 326 #endif 327 328 /* 329 * Cursor-related definitions. 330 */ 331 xf86CursorInfoPtr pCursorInfo; 332 pointer pCursorPage, pCursorImage; 333 unsigned long CursorBase; 334 CARD32 CursorOffset; 335 CARD16 CursorXOffset, CursorYOffset; 336 CARD8 Cursor; 337 338 /* 339 * MMIO cache. 340 */ 341 CARD32 MMIOCache[CacheSlotOf(DWORD_SELECT) + 1]; 342 CARD8 MMIOCached[(CacheSlotOf(DWORD_SELECT) + 8) >> 3]; 343 344 /* 345 * Clock-related definitions. 346 */ 347 int refclk; 348 int ClockNumberToProgramme, ReferenceNumerator, ReferenceDenominator; 349 int ProgrammableClock, maxClock; 350 ClockRec ClockDescriptor; 351 352 /* 353 * DSP register data. 354 */ 355 int XCLKFeedbackDivider, XCLKReferenceDivider, XCLKPostDivider; 356 CARD16 XCLKMaxRASDelay, XCLKPageFaultDelay, 357 DisplayLoopLatency, DisplayFIFODepth; 358 359 /* 360 * LCD panel data. 361 */ 362 int LCDPanelID, LCDClock, LCDHorizontal, LCDVertical; 363 unsigned LCDHSyncStart, LCDHSyncWidth, LCDHBlankWidth; 364 unsigned LCDVSyncStart, LCDVSyncWidth, LCDVBlankWidth; 365 int LCDVBlendFIFOSize; 366 367 /* 368 * Data used by ATIAdjustFrame(). 369 */ 370 int AdjustDepth, AdjustMaxX, AdjustMaxY; 371 unsigned long AdjustMask, AdjustMaxBase; 372 373 /* 374 * DGA and non-DGA common data. 375 */ 376 DisplayModePtr currentMode; 377 CARD8 depth, bitsPerPixel; 378 short int displayWidth; 379 rgb weight; 380 381 #ifndef AVOID_DGA 382 383 /* 384 * DGA-related data. 385 */ 386 DGAModePtr pDGAMode; 387 DGAFunctionRec ATIDGAFunctions; 388 int nDGAMode; 389 390 #endif /* AVOID_DGA */ 391 392 /* 393 * XVideo-related data. 394 */ 395 DevUnion XVPortPrivate[1]; 396 pointer pXVBuffer; /* USE_EXA: ExaOffscreenArea */ 397 RegionRec VideoClip; 398 int SurfacePitch, SurfaceOffset; 399 CARD8 AutoPaint, DoubleBuffer, CurrentBuffer, ActiveSurface; 400 401 /* 402 * Data saved by ATIUnlock() and restored by ATILock(). 403 */ 404 struct 405 { 406 /* Mach64 registers */ 407 CARD32 crtc_int_cntl, crtc_gen_cntl, i2c_cntl_0, hw_debug, 408 scratch_reg3, bus_cntl, lcd_index, mem_cntl, i2c_cntl_1, 409 dac_cntl, gen_test_cntl, mpp_config, mpp_strobe_seq, tvo_cntl; 410 411 #ifndef AVOID_CPIO 412 413 CARD32 config_cntl; 414 415 /* VGA Wonder registers */ 416 CARD8 a6, ab, b1, b4, b5, b6, b8, b9, be; 417 418 /* VGA registers */ 419 CARD8 crt03, crt11; 420 421 /* VGA shadow registers */ 422 CARD8 shadow_crt03, shadow_crt11; 423 424 #endif /* AVOID_CPIO */ 425 426 } LockData; 427 428 /* Mode data */ 429 ATIHWRec OldHW, NewHW; 430 431 /* 432 * Resource Access Control entity index. 433 */ 434 int iEntity; 435 436 /* 437 * Driver options. 438 */ 439 unsigned int OptionProbeSparse:1; /* Force probe for fixed (sparse) I/O */ 440 unsigned int OptionAccel:1; /* Use hardware draw engine */ 441 unsigned int OptionBIOSDisplay:1; /* Allow BIOS interference */ 442 unsigned int OptionBlend:1; /* Force horizontal blending */ 443 unsigned int OptionCRTDisplay:1; /* Display on both CRT & DFP */ 444 unsigned int OptionCSync:1; /* Use composite sync */ 445 unsigned int OptionDevel:1; /* Intentionally undocumented */ 446 447 #ifdef TV_OUT 448 449 CARD8 OptionTvOut; /* Enable TV out if TV is connected */ 450 CARD8 OptionTvStd; /* Requested TV standard - see ATITVStandard enum in atioption.h */ 451 452 #endif /* TV_OUT */ 453 454 unsigned int OptionMMIOCache:1; /* Cache MMIO writes */ 455 unsigned int OptionTestMMIOCache:1;/* Test MMIO cache integrity */ 456 unsigned int OptionPanelDisplay:1; /* Prefer digital panel over CRT */ 457 unsigned int OptionShadowFB:1; /* Use shadow frame buffer */ 458 unsigned int OptionLCDSync:1; /* Temporary */ 459 460 /* 461 * State flags. 462 */ 463 CARD8 Unlocked, Mapped, Closeable; 464 CARD8 MMIOInLinear; 465 466 /* 467 * Wrapped functions. 468 */ 469 CloseScreenProcPtr CloseScreen; 470 471 #ifdef XF86DRI_DEVEL 472 473 /* 474 * DRI data. 475 */ 476 int directRenderingEnabled; 477 DRIInfoPtr pDRIInfo; 478 int drmFD; 479 int irq; 480 ATIDRIServerInfoPtr pDRIServerInfo; 481 Bool NeedDRISync; 482 Bool have3DWindows; 483 484 /* offscreen memory management */ 485 CARD8 OptionIsPCI; /* Force PCI mode */ 486 CARD8 OptionDMAMode; /* async, sync, mmio */ 487 CARD8 OptionAGPMode; /* AGP mode */ 488 CARD8 OptionAGPSize; /* AGP size in MB */ 489 CARD8 OptionLocalTextures; /* Use local textures + AGP textures (only valid for AGP) */ 490 CARD8 OptionBufferSize; /* Command/dma buffer size in MB */ 491 492 #endif /* XF86DRI_DEVEL */ 493 494 #ifdef TV_OUT 495 /* TV out */ 496 vbeInfoPtr pVBE; 497 xf86Int10InfoPtr pInt10; 498 int vbemode; /* saved text mode */ 499 Bool tvActive; 500 #endif /* TV_OUT */ 501 } ATIRec; 502 503 #define ATIPTR(_p) ((ATIPtr)((_p)->driverPrivate)) 504 505 #endif /* ___ATISTRUCT_H___ */ 506
Indexes created Thu Jul 16 00:26:27 UTC 2026