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      1 /*
      2  * Copyright (C) 2021 Collabora, Ltd.
      3  *
      4  * Permission is hereby granted, free of charge, to any person obtaining a
      5  * copy of this software and associated documentation files (the "Software"),
      6  * to deal in the Software without restriction, including without limitation
      7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8  * and/or sell copies of the Software, and to permit persons to whom the
      9  * Software is furnished to do so, subject to the following conditions:
     10  *
     11  * The above copyright notice and this permission notice (including the next
     12  * paragraph) shall be included in all copies or substantial portions of the
     13  * Software.
     14  *
     15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     21  * SOFTWARE.
     22  */
     23 
     24 #include "pan_ir.h"
     25 #include "compiler/nir/nir_builder.h"
     26 
     27 /* Sample positions are supplied in a packed 8:8 fixed-point vec2 format in GPU
     28  * memory indexed by the sample. We lower in NIR to take advantage of possible
     29  * ALU optimizations at the end. This is convenient for Bifrost, since the
     30  * sample positions are passed in this format and it saves the driver from any
     31  * system value handling. For Midgard, it's a bit suboptimal (fp16 positions
     32  * could be supplied directly), but this lets us unify the implementation, and
     33  * it's a pretty trivial difference */
     34 
     35 static bool
     36 pan_lower_sample_pos_impl(struct nir_builder *b,
     37                 nir_instr *instr, UNUSED void *data)
     38 {
     39         if (instr->type != nir_instr_type_intrinsic)
     40                 return false;
     41 
     42         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
     43         if (intr->intrinsic != nir_intrinsic_load_sample_pos)
     44                 return false;
     45 
     46         b->cursor = nir_before_instr(instr);
     47 
     48         /* Elements are 4 bytes */
     49         nir_ssa_def *addr = nir_iadd(b,
     50                         nir_load_sample_positions_pan(b),
     51                         nir_u2u64(b, nir_imul_imm(b, nir_load_sample_id(b), 4)));
     52 
     53         /* Decode 8:8 fixed-point */
     54         nir_ssa_def *raw = nir_load_global(b, addr, 2, 2, 16);
     55         nir_ssa_def *decoded = nir_fmul_imm(b, nir_i2f16(b, raw), 1.0 / 256.0);
     56 
     57         /* Make NIR validator happy */
     58         if (decoded->bit_size != nir_dest_bit_size(intr->dest))
     59                 decoded = nir_f2fN(b, decoded, nir_dest_bit_size(intr->dest));
     60 
     61         nir_ssa_def_rewrite_uses(&intr->dest.ssa, decoded);
     62         return true;
     63 }
     64 
     65 bool
     66 pan_lower_sample_pos(nir_shader *shader)
     67 {
     68         if (shader->info.stage != MESA_SHADER_FRAGMENT)
     69                 return false;
     70 
     71         return nir_shader_instructions_pass(shader,
     72                         pan_lower_sample_pos_impl,
     73                         nir_metadata_block_index | nir_metadata_dominance,
     74                         NULL);
     75 }
     76