1 /* $NetBSD: pcivar.h,v 1.120 2024/06/23 00:53:34 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIVAR_H_ 34 #define _DEV_PCI_PCIVAR_H_ 35 36 /* 37 * Definitions for PCI autoconfiguration. 38 * 39 * This file describes types and functions which are used for PCI 40 * configuration. Some of this information is machine-specific, and is 41 * provided by pci_machdep.h. 42 */ 43 44 #include <sys/device.h> 45 #include <sys/pmf.h> 46 #include <sys/bus.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pci_verbose.h> 49 50 /* 51 * Structures and definitions needed by the machine-dependent header. 52 */ 53 struct pcibus_attach_args; 54 struct pci_attach_args; 55 struct pci_softc; 56 57 #ifdef _KERNEL 58 /* 59 * Machine-dependent definitions. 60 */ 61 #include <machine/pci_machdep.h> 62 63 enum pci_override_idx { 64 PCI_OVERRIDE_CONF_READ = __BIT(0) 65 , PCI_OVERRIDE_CONF_WRITE = __BIT(1) 66 , PCI_OVERRIDE_INTR_MAP = __BIT(2) 67 , PCI_OVERRIDE_INTR_STRING = __BIT(3) 68 , PCI_OVERRIDE_INTR_EVCNT = __BIT(4) 69 , PCI_OVERRIDE_INTR_ESTABLISH = __BIT(5) 70 , PCI_OVERRIDE_INTR_DISESTABLISH = __BIT(6) 71 , PCI_OVERRIDE_MAKE_TAG = __BIT(7) 72 , PCI_OVERRIDE_DECOMPOSE_TAG = __BIT(8) 73 }; 74 75 /* Only add new fields to the end of this structure! */ 76 struct pci_overrides { 77 pcireg_t (*ov_conf_read)(void *, pci_chipset_tag_t, pcitag_t, int); 78 void (*ov_conf_write)(void *, pci_chipset_tag_t, pcitag_t, int, 79 pcireg_t); 80 int (*ov_intr_map)(void *, const struct pci_attach_args *, 81 pci_intr_handle_t *); 82 const char *(*ov_intr_string)(void *, pci_chipset_tag_t, 83 pci_intr_handle_t, char *, size_t); 84 const struct evcnt *(*ov_intr_evcnt)(void *, pci_chipset_tag_t, 85 pci_intr_handle_t); 86 void *(*ov_intr_establish)(void *, pci_chipset_tag_t, pci_intr_handle_t, 87 int, int (*)(void *), void *); 88 void (*ov_intr_disestablish)(void *, pci_chipset_tag_t, void *); 89 pcitag_t (*ov_make_tag)(void *, pci_chipset_tag_t, int, int, int); 90 void (*ov_decompose_tag)(void *, pci_chipset_tag_t, pcitag_t, 91 int *, int *, int *); 92 }; 93 94 /* 95 * PCI bus attach arguments. 96 */ 97 struct pcibus_attach_args { 98 char *_pba_busname; /* XXX placeholder */ 99 bus_space_tag_t pba_iot; /* pci i/o space tag */ 100 bus_space_tag_t pba_memt; /* pci mem space tag */ 101 bus_dma_tag_t pba_dmat; /* DMA tag */ 102 bus_dma_tag_t pba_dmat64; /* DMA tag */ 103 pci_chipset_tag_t pba_pc; 104 int pba_flags; /* flags; see below */ 105 106 int pba_bus; /* PCI bus number */ 107 int pba_sub; /* pba_bus >= pba_sub: no 108 * buses are subordinate to 109 * pba_bus. 110 * 111 * pba_bus < pba_sub: buses 112 * [pba_bus + 1, pba_sub] are 113 * subordinate to pba_bus. 114 */ 115 116 /* 117 * Pointer to the pcitag of our parent bridge. If there is no 118 * parent bridge, then we assume we are a root bus. 119 */ 120 pcitag_t *pba_bridgetag; 121 122 /* 123 * Interrupt swizzling information. These fields 124 * are only used by secondary busses. 125 */ 126 u_int pba_intrswiz; /* how to swizzle pins */ 127 pcitag_t pba_intrtag; /* intr. appears to come from here */ 128 }; 129 130 /* 131 * This is used by <machine/pci_machdep.h> to access the pba_pc member. It 132 * can't use it directly since pcibus_attach_args has yet to be defined. 133 */ 134 static __inline pci_chipset_tag_t 135 pcibus_attach_args_pc(struct pcibus_attach_args *pba) 136 { 137 return pba->pba_pc; 138 } 139 140 #ifndef __HAVE_PCI_GET_SEGMENT 141 static __inline u_int 142 pci_get_segment(pci_chipset_tag_t pc) 143 { 144 return 0; 145 } 146 #endif 147 148 /* 149 * PCI device attach arguments. 150 */ 151 struct pci_attach_args { 152 bus_space_tag_t pa_iot; /* pci i/o space tag */ 153 bus_space_tag_t pa_memt; /* pci mem space tag */ 154 bus_dma_tag_t pa_dmat; /* DMA tag */ 155 bus_dma_tag_t pa_dmat64; /* DMA tag */ 156 pci_chipset_tag_t pa_pc; 157 int pa_flags; /* flags; see below */ 158 159 u_int pa_bus; 160 u_int pa_device; 161 u_int pa_function; 162 pcitag_t pa_tag; 163 pcireg_t pa_id, pa_class; 164 165 /* 166 * Interrupt information. 167 * 168 * "Intrline" is used on systems whose firmware puts 169 * the right routing data into the line register in 170 * configuration space. The rest are used on systems 171 * that do not. 172 */ 173 u_int pa_intrswiz; /* how to swizzle pins if ppb */ 174 pcitag_t pa_intrtag; /* intr. appears to come from here */ 175 pci_intr_pin_t pa_intrpin; /* intr. appears on this pin */ 176 pci_intr_line_t pa_intrline; /* intr. routing information */ 177 pci_intr_pin_t pa_rawintrpin; /* unswizzled pin */ 178 }; 179 180 /* 181 * This is used by <machine/pci_machdep.h> to access the pa_pc member. It 182 * can't use it directly since pci_attach_args has yet to be defined. 183 */ 184 static __inline pci_chipset_tag_t 185 pci_attach_args_pc(const struct pci_attach_args *pa) 186 { 187 return pa->pa_pc; 188 } 189 190 /* 191 * Flags given in the bus and device attachment args. 192 */ 193 #define PCI_FLAGS_IO_OKAY 0x01 /* I/O space is okay */ 194 #define PCI_FLAGS_MEM_OKAY 0x02 /* memory space is okay */ 195 #define PCI_FLAGS_MRL_OKAY 0x04 /* Memory Read Line okay */ 196 #define PCI_FLAGS_MRM_OKAY 0x08 /* Memory Read Multiple okay */ 197 #define PCI_FLAGS_MWI_OKAY 0x10 /* Memory Write and Invalidate 198 okay */ 199 #define PCI_FLAGS_MSI_OKAY 0x20 /* Message Signaled Interrupts 200 okay */ 201 #define PCI_FLAGS_MSIX_OKAY 0x40 /* Message Signaled Interrupts 202 (Extended) okay */ 203 204 /* 205 * PCI device 'quirks'. 206 * 207 * In general strange behaviour which can be handled by a driver (e.g. 208 * a bridge's inability to pass a type of access correctly) should be. 209 * The quirks table should only contain information which impacts 210 * the operation of the MI PCI code and which can't be pushed lower 211 * (e.g. because it's unacceptable to require a driver to be present 212 * for the information to be known). 213 */ 214 struct pci_quirkdata { 215 pci_vendor_id_t vendor; /* Vendor ID */ 216 pci_product_id_t product; /* Product ID */ 217 int quirks; /* quirks; see below */ 218 }; 219 #define PCI_QUIRK_MULTIFUNCTION __BIT(0) 220 #define PCI_QUIRK_MONOFUNCTION __BIT(1) 221 #define PCI_QUIRK_SKIP_FUNC(n) (4 << n) 222 #define PCI_QUIRK_SKIP_FUNC0 PCI_QUIRK_SKIP_FUNC(0) 223 #define PCI_QUIRK_SKIP_FUNC1 PCI_QUIRK_SKIP_FUNC(1) 224 #define PCI_QUIRK_SKIP_FUNC2 PCI_QUIRK_SKIP_FUNC(2) 225 #define PCI_QUIRK_SKIP_FUNC3 PCI_QUIRK_SKIP_FUNC(3) 226 #define PCI_QUIRK_SKIP_FUNC4 PCI_QUIRK_SKIP_FUNC(4) 227 #define PCI_QUIRK_SKIP_FUNC5 PCI_QUIRK_SKIP_FUNC(5) 228 #define PCI_QUIRK_SKIP_FUNC6 PCI_QUIRK_SKIP_FUNC(6) 229 #define PCI_QUIRK_SKIP_FUNC7 PCI_QUIRK_SKIP_FUNC(7) 230 #define PCI_QUIRK_HASEXTCNF __BIT(10) 231 #define PCI_QUIRK_NOEXTCNF __BIT(11) 232 233 struct pci_conf_state { 234 pcireg_t reg[16]; 235 236 /* For PCI-X */ 237 pcireg_t x_csr; /* Upper 16bits. Lower 16bits are read only */ 238 239 /* For PCIe */ 240 uint16_t e_dcr; 241 uint16_t e_lcr; 242 uint16_t e_slcr; 243 uint16_t e_rcr; 244 uint16_t e_dcr2; 245 uint16_t e_lcr2; 246 247 /* For MSI */ 248 pcireg_t msi_ctl; /* Upper 16bits. Lower 16bits are read only */ 249 pcireg_t msi_maddr; 250 pcireg_t msi_maddr64_hi; 251 pcireg_t msi_mdata; 252 pcireg_t msi_mask; 253 254 /* For MSI-X */ 255 pcireg_t msix_ctl; /* Upper 16bits. Lower 16bits are read only */ 256 }; 257 258 struct pci_range { 259 bus_addr_t r_offset; 260 bus_size_t r_size; 261 int r_flags; 262 }; 263 264 struct pci_child { 265 device_t c_dev; 266 bool c_psok; 267 pcireg_t c_powerstate; 268 struct pci_conf_state c_conf; 269 struct pci_range c_range[8]; 270 }; 271 272 struct pci_softc { 273 device_t sc_dev; 274 bus_space_tag_t sc_iot, sc_memt; 275 bus_dma_tag_t sc_dmat; 276 bus_dma_tag_t sc_dmat64; 277 pci_chipset_tag_t sc_pc; 278 int sc_bus, sc_maxndevs; 279 pcitag_t *sc_bridgetag; 280 u_int sc_intrswiz; 281 pcitag_t sc_intrtag; 282 int sc_flags; 283 /* accounting of child devices */ 284 struct pci_child sc_devices[32*8]; 285 #define PCI_SC_DEVICESC(d, f) sc_devices[(d) * 8 + (f)] 286 }; 287 288 extern struct cfdriver pci_cd; 289 290 extern bool pci_mapreg_map_enable_decode; 291 292 int pcibusprint(void *, const char *); 293 294 /* 295 * Configuration space access and utility functions. (Note that most, 296 * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.) 297 */ 298 int pci_mapreg_probe(pci_chipset_tag_t, pcitag_t, int, pcireg_t *); 299 pcireg_t pci_mapreg_type(pci_chipset_tag_t, pcitag_t, int); 300 int pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t, 301 bus_addr_t *, bus_size_t *, int *); 302 int pci_mapreg_map(const struct pci_attach_args *, int, pcireg_t, int, 303 bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *, 304 bus_size_t *); 305 int pci_mapreg_submap(const struct pci_attach_args *, int, pcireg_t, int, 306 bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *, 307 bus_addr_t *, bus_size_t *); 308 309 int pci_find_rom(const struct pci_attach_args *, bus_space_tag_t, 310 bus_space_handle_t, bus_size_t, 311 int, bus_space_handle_t *, bus_size_t *); 312 313 int pci_get_capability(pci_chipset_tag_t, pcitag_t, int, int *, pcireg_t *); 314 int pci_get_ht_capability(pci_chipset_tag_t, pcitag_t, int, int *, 315 pcireg_t *); 316 int pci_get_ext_capability(pci_chipset_tag_t, pcitag_t, int, int *, 317 pcireg_t *); 318 319 int pci_msi_count(pci_chipset_tag_t, pcitag_t); 320 int pci_msix_count(pci_chipset_tag_t, pcitag_t); 321 322 /* 323 * Helper functions for autoconfiguration. 324 */ 325 326 #define PCI_COMPAT_EOL_VALUE (0xffffffffU) 327 #define PCI_COMPAT_EOL { .id = PCI_COMPAT_EOL_VALUE } 328 329 const struct device_compatible_entry * 330 pci_compatible_lookup_id(pcireg_t, 331 const struct device_compatible_entry *); 332 const struct device_compatible_entry * 333 pci_compatible_lookup(const struct pci_attach_args *, 334 const struct device_compatible_entry *); 335 int pci_compatible_match(const struct pci_attach_args *, 336 const struct device_compatible_entry *); 337 const struct device_compatible_entry * 338 pci_compatible_lookup_subsys(const struct pci_attach_args *, 339 const struct device_compatible_entry *); 340 int pci_compatible_match_subsys(const struct pci_attach_args *, 341 const struct device_compatible_entry *); 342 int pci_enumerate_bus(struct pci_softc *, const int *, 343 int (*)(const struct pci_attach_args *), struct pci_attach_args *); 344 #ifndef PCI_MACHDEP_ENUMERATE_BUS1 345 int pci_enumerate_bus1(struct pci_softc *, const int *, 346 int (*)(void *, const struct pci_attach_args *), void *, 347 struct pci_attach_args *); 348 #endif 349 int pci_probe_device1(struct pci_softc *, pcitag_t tag, 350 int (*)(void *, const struct pci_attach_args *), void *, 351 struct pci_attach_args *); 352 void pci_devinfo(pcireg_t, pcireg_t, int, char *, size_t); 353 void pci_aprint_devinfo_fancy(const struct pci_attach_args *, 354 const char *, const char *, int); 355 #define pci_aprint_devinfo(pap, naive) \ 356 pci_aprint_devinfo_fancy(pap, naive, NULL, 0); 357 void pci_conf_print(pci_chipset_tag_t, pcitag_t, 358 void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)); 359 const struct pci_quirkdata * 360 pci_lookup_quirkdata(pci_vendor_id_t, pci_product_id_t); 361 362 /* 363 * Helper functions for user access to the PCI bus. 364 */ 365 struct proc; 366 int pci_devioctl(pci_chipset_tag_t, pcitag_t, u_long, void *, 367 int flag, struct lwp *); 368 369 /* 370 * Power Management (PCI 2.2) 371 */ 372 373 #define PCI_PWR_D0 0 374 #define PCI_PWR_D1 1 375 #define PCI_PWR_D2 2 376 #define PCI_PWR_D3 3 377 int pci_powerstate(pci_chipset_tag_t, pcitag_t, const int *, int *); 378 379 /* 380 * Vital Product Data (PCI 2.2) 381 */ 382 int pci_vpd_read(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 383 int pci_vpd_write(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *); 384 385 /* 386 * Misc. 387 */ 388 int pci_find_device(struct pci_attach_args *, 389 int (*match)(const struct pci_attach_args *)); 390 int pci_find_device1(struct pci_attach_args *, 391 int (*match)(void *, const struct pci_attach_args *), void *); 392 int pci_dma64_available(const struct pci_attach_args *); 393 void pci_conf_capture(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 394 void pci_conf_restore(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *); 395 int pci_get_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t *); 396 int pci_set_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t); 397 int pci_activate(pci_chipset_tag_t, pcitag_t, device_t, 398 int (*)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)); 399 int pci_activate_null(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t); 400 int pci_chipset_tag_create(pci_chipset_tag_t, uint64_t, 401 const struct pci_overrides *, 402 void *, pci_chipset_tag_t *); 403 void pci_chipset_tag_destroy(pci_chipset_tag_t); 404 int pci_bus_devorder(pci_chipset_tag_t, int, uint8_t *, int); 405 void *pci_intr_establish_xname(pci_chipset_tag_t, pci_intr_handle_t, 406 int, int (*)(void *), void *, const char *); 407 #ifndef __HAVE_PCI_MSI_MSIX 408 typedef enum { 409 PCI_INTR_TYPE_INTX = 0, 410 PCI_INTR_TYPE_MSI, 411 PCI_INTR_TYPE_MSIX, 412 PCI_INTR_TYPE_SIZE, 413 } pci_intr_type_t; 414 415 pci_intr_type_t 416 pci_intr_type(pci_chipset_tag_t, pci_intr_handle_t); 417 int pci_intr_alloc(const struct pci_attach_args *, pci_intr_handle_t **, 418 int *, pci_intr_type_t); 419 void pci_intr_release(pci_chipset_tag_t, pci_intr_handle_t *, int); 420 int pci_intx_alloc(const struct pci_attach_args *, pci_intr_handle_t **); 421 int pci_msi_alloc(const struct pci_attach_args *, pci_intr_handle_t **, 422 int *); 423 int pci_msi_alloc_exact(const struct pci_attach_args *, 424 pci_intr_handle_t **, int); 425 int pci_msix_alloc(const struct pci_attach_args *, pci_intr_handle_t **, 426 int *); 427 int pci_msix_alloc_exact(const struct pci_attach_args *, 428 pci_intr_handle_t **, int); 429 int pci_msix_alloc_map(const struct pci_attach_args *, pci_intr_handle_t **, 430 u_int *, int); 431 #endif 432 433 /* 434 * Device abstraction for inheritance by elanpci(4), for example. 435 */ 436 int pcimatch(device_t, cfdata_t, void *); 437 void pciattach(device_t, device_t, void *); 438 int pcidetach(device_t, int); 439 void pcidevdetached(device_t, device_t); 440 int pcirescan(device_t, const char *, const int *); 441 442 /* 443 * Interrupts. 444 */ 445 #define PCI_INTR_MPSAFE 1 446 447 int pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t); 448 449 /* 450 * Local constants 451 */ 452 #define PCI_INTRSTR_LEN 64 453 454 #endif /* _KERNEL */ 455 456 #endif /* _DEV_PCI_PCIVAR_H_ */ 457
Indexes created Sun Sep 21 19:09:51 GMT 2025