1 /* 2 * (C) Copyright IBM Corporation 2006 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 /** 26 * \file common_capability.c 27 * Platform independent PCI capability related routines. 28 * 29 * In addition to including the interface glue for \c pci_device_get_agp_info, 30 * this file also contains a generic implementation of that function. 31 * 32 * \author Ian Romanick <idr (at) us.ibm.com> 33 */ 34 #ifdef HAVE_CONFIG_H 35 #include "config.h" 36 #endif 37 38 #include <stdlib.h> 39 #include <stdio.h> 40 #include <errno.h> 41 42 #include "pciaccess.h" 43 #include "pciaccess_private.h" 44 45 /** 46 * Generic implementation of \c pci_system_methods::fill_capabilities. 47 * 48 * \param dev Device whose capability information is to be processed. 49 * 50 * \return 51 * Zero on success or an errno value on failure. 52 * 53 * \todo 54 * Once more than just the AGP capability is supported, the body of each of 55 * the cases in the capability processing loop should probably be broken out 56 * into its own function. 57 * 58 * \todo 59 * Once more than just the AGP capability is supported, some care will need 60 * to be taken in partial failure cases. If, say, the first capability is 61 * correctly processed but the second fails, the function would be re-called 62 * later to try again for the second capability. This could lead to memory 63 * leaks or other quirky behavior. 64 */ 65 _pci_hidden int 66 pci_fill_capabilities_generic( struct pci_device * dev ) 67 { 68 struct pci_device_private * const dev_priv = 69 (struct pci_device_private *) dev; 70 int err; 71 uint16_t status; 72 uint8_t cap_offset; 73 74 75 err = pci_device_cfg_read_u16( dev, & status, 6 ); 76 if ( err ) { 77 return err; 78 } 79 80 /* Are PCI capabilities supported by this device? 81 */ 82 if ( (status & 0x0010) == 0 ) { 83 return ENOSYS; 84 } 85 86 err = pci_device_cfg_read_u8( dev, & cap_offset, 52 ); 87 if ( err ) { 88 return err; 89 } 90 91 92 /* Process each of the capabilities list in the PCI header. 93 */ 94 while ( cap_offset != 0 ) { 95 uint8_t cap_id; 96 uint8_t next_cap; 97 98 err = pci_device_cfg_read_u8( dev, & cap_id, cap_offset ); 99 if ( err ) { 100 return err; 101 } 102 103 err = pci_device_cfg_read_u8( dev, & next_cap, cap_offset + 1 ); 104 if ( err ) { 105 return err; 106 } 107 108 switch ( cap_id ) { 109 case 2: { 110 struct pci_agp_info * agp_info; 111 uint32_t agp_status; 112 uint8_t agp_ver; 113 114 115 err = pci_device_cfg_read_u8( dev, & agp_ver, cap_offset + 2 ); 116 if ( err ) { 117 return err; 118 } 119 120 err = pci_device_cfg_read_u32( dev, & agp_status, cap_offset + 4 ); 121 if ( err ) { 122 return err; 123 } 124 125 agp_info = calloc( 1, sizeof( struct pci_agp_info ) ); 126 if ( agp_info == NULL ) { 127 return ENOMEM; 128 } 129 130 agp_info->config_offset = cap_offset; 131 132 agp_info->major_version = (agp_ver & 0x0f0) >> 4; 133 agp_info->minor_version = (agp_ver & 0x00f); 134 135 agp_info->rates = (agp_status & 0x07); 136 137 /* If AGP3 is supported, then the meaning of the rates values 138 * changes. 139 */ 140 if ( (agp_status & 0x08) != 0 ) { 141 agp_info->rates <<= 2; 142 } 143 144 /* Some devices, notably motherboard chipsets, have the AGP3 145 * capability set and the 4x bit set. This results in an 146 * impossible 16x mode being listed as available. I'm not 100% 147 * sure this is the right solution. 148 */ 149 agp_info->rates &= 0x0f; 150 151 152 agp_info->fast_writes = (agp_status & 0x0010) != 0; 153 agp_info->addr64 = (agp_status & 0x0020) != 0; 154 agp_info->htrans = (agp_status & 0x0040) == 0; 155 agp_info->gart64 = (agp_status & 0x0080) != 0; 156 agp_info->coherent = (agp_status & 0x0100) != 0; 157 agp_info->sideband = (agp_status & 0x0200) != 0; 158 agp_info->isochronus = (agp_status & 0x10000) != 0; 159 160 agp_info->async_req_size = 4 + (1 << ((agp_status & 0xe000) >> 13)); 161 agp_info->calibration_cycle_timing = ((agp_status & 0x1c00) >> 10); 162 agp_info->max_requests = 1 + ((agp_status & 0xff000000) >> 24); 163 164 dev_priv->agp = agp_info; 165 break; 166 } 167 168 /* No other capabilities are currently handled. 169 */ 170 default: 171 printf( "Unknown cap 0x%02x @ 0x%02x\n", cap_id, cap_offset ); 172 break; 173 } 174 175 cap_offset = next_cap; 176 } 177 178 return 0; 179 } 180 181 182 /** 183 * Get AGP capability data for a device. 184 */ 185 const struct pci_agp_info * 186 pci_device_get_agp_info( struct pci_device * dev ) 187 { 188 struct pci_device_private * dev_priv = (struct pci_device_private *) dev; 189 190 if ( dev == NULL ) { 191 return NULL; 192 } 193 194 if ( dev_priv->agp == NULL ) { 195 (void) (*pci_sys->methods->fill_capabilities)( dev ); 196 } 197 198 return dev_priv->agp; 199 } 200
Indexes created Fri Jul 03 00:25:33 UTC 2026