1 /* $NetBSD: pci.c,v 1.168 2024/06/23 00:53:34 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.168 2024/06/23 00:53:34 riastradh Exp $"); 40 41 #ifdef _KERNEL_OPT 42 #include "opt_pci.h" 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/malloc.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/module.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/ppbvar.h> 55 56 #include <dev/pci/pci_calls.h> 57 58 #include <net/if.h> 59 60 #include "locators.h" 61 62 static void pci_child_register(device_t); 63 64 #ifdef PCI_CONFIG_DUMP 65 int pci_config_dump = 1; 66 #else 67 int pci_config_dump = 0; 68 #endif 69 70 int pciprint(void *, const char *); 71 72 #ifdef PCI_MACHDEP_ENUMERATE_BUS1 73 #define pci_enumerate_bus1 PCI_MACHDEP_ENUMERATE_BUS1 74 #endif 75 76 /* 77 * Important note about PCI-ISA bridges: 78 * 79 * Callbacks are used to configure these devices so that ISA/EISA bridges 80 * can attach their child busses after PCI configuration is done. 81 * 82 * This works because: 83 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 84 * (2) any ISA/EISA bridges must be attached to primary PCI 85 * busses (i.e. bus zero). 86 * 87 * That boils down to: there can only be one of these outstanding 88 * at a time, it is cleared when configuring PCI bus 0 before any 89 * subdevices have been found, and it is run after all subdevices 90 * of PCI bus 0 have been found. 91 * 92 * This is needed because there are some (legacy) PCI devices which 93 * can show up as ISA/EISA devices as well (the prime example of which 94 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 95 * and the bridge is seen before the video board is, the board can show 96 * up as an ISA device, and that can (bogusly) complicate the PCI device's 97 * attach code, or make the PCI device not be properly attached at all. 98 * 99 * We use the generic config_defer() facility to achieve this. 100 */ 101 102 int 103 pcirescan(device_t self, const char *ifattr, const int *locators) 104 { 105 struct pci_softc *sc = device_private(self); 106 107 KASSERT(ifattr && !strcmp(ifattr, "pci")); 108 KASSERT(locators); 109 110 pci_enumerate_bus(sc, locators, NULL, NULL); 111 112 return 0; 113 } 114 115 int 116 pcimatch(device_t parent, cfdata_t cf, void *aux) 117 { 118 struct pcibus_attach_args *pba = aux; 119 120 /* Check the locators */ 121 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 122 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 123 return 0; 124 125 /* sanity */ 126 if (pba->pba_bus < 0 || pba->pba_bus > 255) 127 return 0; 128 129 /* 130 * XXX check other (hardware?) indicators 131 */ 132 133 return 1; 134 } 135 136 void 137 pciattach(device_t parent, device_t self, void *aux) 138 { 139 struct pcibus_attach_args *pba = aux; 140 struct pci_softc *sc = device_private(self); 141 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 142 const char *sep = ""; 143 static const int wildcard[PCICF_NLOCS] = { 144 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 145 }; 146 147 sc->sc_dev = self; 148 149 pci_attach_hook(parent, self, pba); 150 151 aprint_naive("\n"); 152 aprint_normal("\n"); 153 154 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_OKAY); 155 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_OKAY); 156 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 157 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 158 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 159 160 if (io_enabled == 0 && mem_enabled == 0) { 161 aprint_error_dev(self, "no spaces enabled!\n"); 162 goto fail; 163 } 164 165 #define PRINT(str) \ 166 do { \ 167 aprint_verbose("%s%s", sep, str); \ 168 sep = ", "; \ 169 } while (/*CONSTCOND*/0) 170 171 aprint_verbose_dev(self, ""); 172 173 if (io_enabled) 174 PRINT("i/o space"); 175 if (mem_enabled) 176 PRINT("memory space"); 177 aprint_verbose(" enabled"); 178 179 if (mrl_enabled || mrm_enabled || mwi_enabled) { 180 if (mrl_enabled) 181 PRINT("rd/line"); 182 if (mrm_enabled) 183 PRINT("rd/mult"); 184 if (mwi_enabled) 185 PRINT("wr/inv"); 186 aprint_verbose(" ok"); 187 } 188 189 aprint_verbose("\n"); 190 191 #undef PRINT 192 193 sc->sc_iot = pba->pba_iot; 194 sc->sc_memt = pba->pba_memt; 195 sc->sc_dmat = pba->pba_dmat; 196 sc->sc_dmat64 = pba->pba_dmat64; 197 sc->sc_pc = pba->pba_pc; 198 sc->sc_bus = pba->pba_bus; 199 sc->sc_bridgetag = pba->pba_bridgetag; 200 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 201 sc->sc_intrswiz = pba->pba_intrswiz; 202 sc->sc_intrtag = pba->pba_intrtag; 203 sc->sc_flags = pba->pba_flags; 204 205 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 206 207 pcirescan(sc->sc_dev, "pci", wildcard); 208 209 fail: 210 if (!pmf_device_register(self, NULL, NULL)) 211 aprint_error_dev(self, "couldn't establish power handler\n"); 212 } 213 214 int 215 pcidetach(device_t self, int flags) 216 { 217 int rc; 218 219 if ((rc = config_detach_children(self, flags)) != 0) 220 return rc; 221 pmf_device_deregister(self); 222 return 0; 223 } 224 225 int 226 pciprint(void *aux, const char *pnp) 227 { 228 struct pci_attach_args *pa = aux; 229 char devinfo[256]; 230 const struct pci_quirkdata *qd; 231 232 if (pnp) { 233 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 234 aprint_normal("%s at %s", devinfo, pnp); 235 } 236 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 237 if (pci_config_dump) { 238 printf(": "); 239 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 240 if (!pnp) 241 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 242 printf("%s at %s", devinfo, pnp ? pnp : "?"); 243 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 244 #ifdef __i386__ 245 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 246 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 247 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 248 #else 249 printf("intrswiz %#lx, intrpin %#lx", 250 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 251 #endif 252 printf(", i/o %s, mem %s,", 253 pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off", 254 pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off"); 255 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 256 PCI_PRODUCT(pa->pa_id)); 257 if (qd == NULL) { 258 printf(" no quirks"); 259 } else { 260 snprintb(devinfo, sizeof (devinfo), 261 "\002\001multifn\002singlefn\003skipfunc0" 262 "\004skipfunc1\005skipfunc2\006skipfunc3" 263 "\007skipfunc4\010skipfunc5\011skipfunc6" 264 "\012skipfunc7", qd->quirks); 265 printf(" quirks %s", devinfo); 266 } 267 printf(")"); 268 } 269 return UNCONF; 270 } 271 272 static devhandle_t 273 pci_bus_get_child_devhandle(struct pci_softc *sc, pcitag_t tag) 274 { 275 struct pci_bus_get_child_devhandle_args args = { 276 .pc = sc->sc_pc, 277 .tag = tag, 278 }; 279 280 if (device_call(sc->sc_dev, PCI_BUS_GET_CHILD_DEVHANDLE(&args)) != 0) { 281 /* 282 * The call is either not supported or the requested 283 * device was not found in the platform device tree. 284 * Return an invalid handle. 285 */ 286 return devhandle_invalid(); 287 } 288 289 return args.devhandle; 290 } 291 292 int 293 pci_probe_device1(struct pci_softc *sc, pcitag_t tag, 294 int (*match)(void *, const struct pci_attach_args *), void *cookie, 295 struct pci_attach_args *pap) 296 { 297 pci_chipset_tag_t pc = sc->sc_pc; 298 struct pci_attach_args pa; 299 pcireg_t id, /* csr, */ pciclass, intr, bhlcr, bar, endbar; 300 #ifdef __HAVE_PCI_MSI_MSIX 301 pcireg_t cap; 302 int off; 303 #endif 304 int ret, pin, bus, device, function, i, width; 305 int locs[PCICF_NLOCS]; 306 307 pci_decompose_tag(pc, tag, &bus, &device, &function); 308 309 /* a driver already attached? */ 310 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 311 return 0; 312 313 id = pci_conf_read(pc, tag, PCI_ID_REG); 314 315 /* Invalid vendor ID value? */ 316 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 317 return 0; 318 /* XXX Not invalid, but we've done this ~forever. */ 319 if (PCI_VENDOR(id) == 0) 320 return 0; 321 322 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 323 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 324 return 0; 325 326 /* csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); */ 327 pciclass = pci_conf_read(pc, tag, PCI_CLASS_REG); 328 329 /* Collect memory range info */ 330 memset(sc->PCI_SC_DEVICESC(device, function).c_range, 0, 331 sizeof(sc->PCI_SC_DEVICESC(device, function).c_range)); 332 i = 0; 333 switch (PCI_HDRTYPE_TYPE(bhlcr)) { 334 case PCI_HDRTYPE_PPB: 335 endbar = PCI_MAPREG_PPB_END; 336 break; 337 case PCI_HDRTYPE_PCB: 338 endbar = PCI_MAPREG_PCB_END; 339 break; 340 default: 341 endbar = PCI_MAPREG_END; 342 break; 343 } 344 for (bar = PCI_MAPREG_START; bar < endbar; bar += width) { 345 struct pci_range *r; 346 pcireg_t type; 347 348 width = 4; 349 if (pci_mapreg_probe(pc, tag, bar, &type) == 0) 350 continue; 351 352 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_MEM) { 353 if (PCI_MAPREG_MEM_TYPE(type) == 354 PCI_MAPREG_MEM_TYPE_64BIT) 355 width = 8; 356 357 r = &sc->PCI_SC_DEVICESC(device, function).c_range[i++]; 358 if (pci_mapreg_info(pc, tag, bar, type, 359 &r->r_offset, &r->r_size, &r->r_flags) != 0) 360 break; 361 if ((PCI_VENDOR(id) == PCI_VENDOR_ATI) && (bar == 0x10) 362 && (r->r_size == 0x1000000)) { 363 struct pci_range *nr; 364 /* 365 * this has to be a mach64 366 * split things up so each half-aperture can 367 * be mapped PREFETCHABLE except the last page 368 * which may contain registers 369 */ 370 r->r_size = 0x7ff000; 371 r->r_flags = BUS_SPACE_MAP_LINEAR | 372 BUS_SPACE_MAP_PREFETCHABLE; 373 nr = &sc->PCI_SC_DEVICESC(device, 374 function).c_range[i++]; 375 nr->r_offset = r->r_offset + 0x800000; 376 nr->r_size = 0x7ff000; 377 nr->r_flags = BUS_SPACE_MAP_LINEAR | 378 BUS_SPACE_MAP_PREFETCHABLE; 379 } else if ((PCI_VENDOR(id) == PCI_VENDOR_SILMOTION) && 380 (PCI_PRODUCT(id) == PCI_PRODUCT_SILMOTION_SM502) && 381 (bar == 0x10)) { 382 r->r_flags = BUS_SPACE_MAP_LINEAR | 383 BUS_SPACE_MAP_PREFETCHABLE; 384 } 385 } 386 } 387 388 pa.pa_iot = sc->sc_iot; 389 pa.pa_memt = sc->sc_memt; 390 pa.pa_dmat = sc->sc_dmat; 391 pa.pa_dmat64 = sc->sc_dmat64; 392 pa.pa_pc = pc; 393 pa.pa_bus = bus; 394 pa.pa_device = device; 395 pa.pa_function = function; 396 pa.pa_tag = tag; 397 pa.pa_id = id; 398 pa.pa_class = pciclass; 399 400 /* 401 * Set up memory, I/O enable, and PCI command flags 402 * as appropriate. 403 */ 404 pa.pa_flags = sc->sc_flags; 405 406 /* 407 * If the cache line size is not configured, then 408 * clear the MRL/MRM/MWI command-ok flags. 409 */ 410 if (PCI_CACHELINE(bhlcr) == 0) { 411 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 412 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 413 } 414 415 if (sc->sc_bridgetag == NULL) { 416 pa.pa_intrswiz = 0; 417 pa.pa_intrtag = tag; 418 } else { 419 pa.pa_intrswiz = sc->sc_intrswiz + device; 420 pa.pa_intrtag = sc->sc_intrtag; 421 } 422 423 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 424 425 pin = PCI_INTERRUPT_PIN(intr); 426 pa.pa_rawintrpin = pin; 427 if (pin == PCI_INTERRUPT_PIN_NONE) { 428 /* no interrupt */ 429 pa.pa_intrpin = 0; 430 } else { 431 /* 432 * swizzle it based on the number of busses we're 433 * behind and our device number. 434 */ 435 pa.pa_intrpin = /* XXX */ 436 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 437 } 438 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 439 440 devhandle_t devhandle = pci_bus_get_child_devhandle(sc, pa.pa_tag); 441 442 #ifdef __HAVE_PCI_MSI_MSIX 443 if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSIMAP, &off, &cap)) { 444 /* 445 * XXX Should we enable MSI mapping ourselves on 446 * systems that have it disabled? 447 */ 448 if (cap & PCI_HT_MSI_ENABLED) { 449 uint64_t addr; 450 if ((cap & PCI_HT_MSI_FIXED) == 0) { 451 addr = pci_conf_read(pc, tag, 452 off + PCI_HT_MSI_ADDR_LO); 453 addr |= (uint64_t)pci_conf_read(pc, tag, 454 off + PCI_HT_MSI_ADDR_HI) << 32; 455 } else 456 addr = PCI_HT_MSI_FIXED_ADDR; 457 458 /* 459 * XXX This will fail to enable MSI on systems 460 * that don't use the canonical address. 461 */ 462 if (addr == PCI_HT_MSI_FIXED_ADDR) { 463 pa.pa_flags |= PCI_FLAGS_MSI_OKAY; 464 pa.pa_flags |= PCI_FLAGS_MSIX_OKAY; 465 } else 466 aprint_verbose_dev(sc->sc_dev, 467 "HyperTransport MSI mapping is not supported yet. Disable MSI/MSI-X.\n"); 468 } 469 } 470 #endif 471 472 if (match != NULL) { 473 ret = (*match)(cookie, &pa); 474 if (ret != 0 && pap != NULL) 475 *pap = pa; 476 } else { 477 struct pci_child *c; 478 locs[PCICF_DEV] = device; 479 locs[PCICF_FUNCTION] = function; 480 481 c = &sc->PCI_SC_DEVICESC(device, function); 482 pci_conf_capture(pc, tag, &c->c_conf); 483 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 484 c->c_psok = true; 485 else 486 c->c_psok = false; 487 488 c->c_dev = config_found(sc->sc_dev, &pa, pciprint, 489 CFARGS(.submatch = config_stdsubmatch, 490 .locators = locs, 491 .devhandle = devhandle)); 492 493 ret = (c->c_dev != NULL); 494 } 495 496 return ret; 497 } 498 499 void 500 pcidevdetached(device_t self, device_t child) 501 { 502 struct pci_softc *sc = device_private(self); 503 int d, f; 504 pcitag_t tag; 505 struct pci_child *c; 506 507 d = device_locator(child, PCICF_DEV); 508 f = device_locator(child, PCICF_FUNCTION); 509 510 c = &sc->PCI_SC_DEVICESC(d, f); 511 512 KASSERT(c->c_dev == child); 513 514 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 515 if (c->c_psok) 516 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 517 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 518 c->c_dev = NULL; 519 } 520 521 CFATTACH_DECL3_NEW(pci, sizeof(struct pci_softc), 522 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached, 523 DVF_DETACH_SHUTDOWN); 524 525 int 526 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 527 int *offset, pcireg_t *value) 528 { 529 pcireg_t reg; 530 unsigned int ofs; 531 532 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 533 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 534 return 0; 535 536 /* Determine the Capability List Pointer register to start with. */ 537 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 538 switch (PCI_HDRTYPE_TYPE(reg)) { 539 case 0: /* standard device header */ 540 case 1: /* PCI-PCI bridge header */ 541 ofs = PCI_CAPLISTPTR_REG; 542 break; 543 case 2: /* PCI-CardBus Bridge header */ 544 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 545 break; 546 default: 547 return 0; 548 } 549 550 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 551 while (ofs != 0) { 552 if ((ofs & 3) || (ofs < 0x40)) { 553 int bus, device, function; 554 555 pci_decompose_tag(pc, tag, &bus, &device, &function); 556 557 printf("Skipping broken PCI header on %d:%d:%d\n", 558 bus, device, function); 559 break; 560 } 561 reg = pci_conf_read(pc, tag, ofs); 562 if (PCI_CAPLIST_CAP(reg) == capid) { 563 if (offset) 564 *offset = ofs; 565 if (value) 566 *value = reg; 567 return 1; 568 } 569 ofs = PCI_CAPLIST_NEXT(reg); 570 } 571 572 return 0; 573 } 574 575 int 576 pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 577 int *offset, pcireg_t *value) 578 { 579 pcireg_t reg; 580 unsigned int ofs; 581 582 if (pci_get_capability(pc, tag, PCI_CAP_LDT, &ofs, NULL) == 0) 583 return 0; 584 585 while (ofs != 0) { 586 #ifdef DIAGNOSTIC 587 if ((ofs & 3) || (ofs < 0x40)) 588 panic("pci_get_ht_capability"); 589 #endif 590 reg = pci_conf_read(pc, tag, ofs); 591 if (PCI_HT_CAP(reg) == capid) { 592 if (offset) 593 *offset = ofs; 594 if (value) 595 *value = reg; 596 return 1; 597 } 598 ofs = PCI_CAPLIST_NEXT(reg); 599 } 600 601 return 0; 602 } 603 604 /* 605 * return number of the devices's MSI vectors 606 * return 0 if the device does not support MSI 607 */ 608 int 609 pci_msi_count(pci_chipset_tag_t pc, pcitag_t tag) 610 { 611 pcireg_t reg; 612 uint32_t mmc; 613 int count, offset; 614 615 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &offset, NULL) == 0) 616 return 0; 617 618 reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL); 619 mmc = PCI_MSI_CTL_MMC(reg); 620 count = 1 << mmc; 621 if (count > PCI_MSI_MAX_VECTORS) { 622 aprint_error("detect an illegal device! The device use reserved MMC values.\n"); 623 return 0; 624 } 625 626 return count; 627 } 628 629 /* 630 * return number of the devices's MSI-X vectors 631 * return 0 if the device does not support MSI-X 632 */ 633 int 634 pci_msix_count(pci_chipset_tag_t pc, pcitag_t tag) 635 { 636 pcireg_t reg; 637 int offset; 638 639 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &offset, NULL) == 0) 640 return 0; 641 642 reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL); 643 644 return PCI_MSIX_CTL_TBLSIZE(reg); 645 } 646 647 int 648 pci_get_ext_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 649 int *offset, pcireg_t *value) 650 { 651 pcireg_t reg; 652 unsigned int ofs; 653 654 /* Only supported for PCI-express devices */ 655 if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, NULL, NULL)) 656 return 0; 657 658 ofs = PCI_EXTCAPLIST_BASE; 659 reg = pci_conf_read(pc, tag, ofs); 660 if (reg == 0xffffffff || reg == 0) 661 return 0; 662 663 for (;;) { 664 #ifdef DIAGNOSTIC 665 if ((ofs & 3) || ofs < PCI_EXTCAPLIST_BASE) 666 panic("%s: invalid offset %u", __func__, ofs); 667 #endif 668 if (PCI_EXTCAPLIST_CAP(reg) == capid) { 669 if (offset != NULL) 670 *offset = ofs; 671 if (value != NULL) 672 *value = reg; 673 return 1; 674 } 675 ofs = PCI_EXTCAPLIST_NEXT(reg); 676 if (ofs == 0) 677 break; 678 reg = pci_conf_read(pc, tag, ofs); 679 } 680 681 return 0; 682 } 683 684 static int 685 pci_match_cookieless(void *cookie, const struct pci_attach_args *pa) 686 { 687 int (*match)(const struct pci_attach_args *) = cookie; 688 689 return (*match)(pa); 690 } 691 692 int 693 pci_find_device(struct pci_attach_args *pa, 694 int (*match)(const struct pci_attach_args *)) 695 { 696 void *cookie = match; 697 698 return (match == NULL 699 ? pci_find_device1(pa, NULL, NULL) 700 : pci_find_device1(pa, &pci_match_cookieless, cookie)); 701 } 702 703 int 704 pci_find_device1(struct pci_attach_args *pa, 705 int (*match)(void *, const struct pci_attach_args *), void *cookie) 706 { 707 extern struct cfdriver pci_cd; 708 device_t pcidev; 709 int i; 710 static const int wildcard[2] = { 711 PCICF_DEV_DEFAULT, 712 PCICF_FUNCTION_DEFAULT 713 }; 714 715 for (i = 0; i < pci_cd.cd_ndevs; i++) { 716 pcidev = device_lookup(&pci_cd, i); 717 if (pcidev != NULL && 718 pci_enumerate_bus1(device_private(pcidev), wildcard, 719 match, cookie, pa) != 0) 720 return 1; 721 } 722 return 0; 723 } 724 725 int 726 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 727 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 728 { 729 void *cookie = match; 730 731 return (match == NULL 732 ? pci_enumerate_bus1(sc, locators, NULL, NULL, pap) 733 : pci_enumerate_bus1(sc, locators, &pci_match_cookieless, cookie, 734 pap)); 735 } 736 737 #ifndef PCI_MACHDEP_ENUMERATE_BUS1 738 /* 739 * Generic PCI bus enumeration routine. Used unless machine-dependent 740 * code needs to provide something else. 741 */ 742 int 743 pci_enumerate_bus1(struct pci_softc *sc, const int *locators, 744 int (*match)(void *, const struct pci_attach_args *), void *cookie, 745 struct pci_attach_args *pap) 746 { 747 pci_chipset_tag_t pc = sc->sc_pc; 748 int device, function, nfunctions, ret; 749 const struct pci_quirkdata *qd; 750 pcireg_t id, bhlcr; 751 pcitag_t tag; 752 uint8_t devs[32]; 753 int i, n; 754 755 device_t bridgedev; 756 bool arien = false; 757 bool downstream_port = false; 758 759 /* Check PCIe ARI and port type */ 760 bridgedev = device_parent(sc->sc_dev); 761 if (device_is_a(bridgedev, "ppb")) { 762 struct ppb_softc *ppbsc = device_private(bridgedev); 763 pci_chipset_tag_t ppbpc = ppbsc->sc_pc; 764 pcitag_t ppbtag = ppbsc->sc_tag; 765 pcireg_t pciecap, capreg, reg; 766 767 if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS, 768 &pciecap, &capreg) != 0) { 769 switch (PCIE_XCAP_TYPE(capreg)) { 770 case PCIE_XCAP_TYPE_RP: 771 case PCIE_XCAP_TYPE_DOWN: 772 case PCIE_XCAP_TYPE_PCI2PCIE: 773 downstream_port = true; 774 break; 775 } 776 777 reg = pci_conf_read(ppbpc, ppbtag, pciecap 778 + PCIE_DCSR2); 779 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 780 arien = true; 781 } 782 } 783 784 n = pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs, __arraycount(devs)); 785 if (downstream_port) { 786 /* PCIe downstream ports only have a single child device */ 787 n = 1; 788 } 789 790 for (i = 0; i < n; i++) { 791 device = devs[i]; 792 793 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 794 (locators[PCICF_DEV] != device)) 795 continue; 796 797 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 798 799 id = pci_conf_read(pc, tag, PCI_ID_REG); 800 801 /* Invalid vendor ID value? */ 802 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 803 continue; 804 /* XXX Not invalid, but we've done this ~forever. */ 805 if (PCI_VENDOR(id) == 0) 806 continue; 807 808 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 809 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 810 continue; 811 812 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 813 814 if (qd != NULL && 815 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 816 nfunctions = 8; 817 else if (qd != NULL && 818 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 819 nfunctions = 1; 820 else if (arien) 821 nfunctions = 8; /* Scan all if ARI is enabled */ 822 else 823 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 824 825 #ifdef __PCI_DEV_FUNCORDER 826 char funcs[8]; 827 int j; 828 for (j = 0; j < nfunctions; j++) { 829 funcs[j] = j; 830 } 831 if (j < __arraycount(funcs)) 832 funcs[j] = -1; 833 if (nfunctions > 1) { 834 pci_dev_funcorder(sc->sc_pc, sc->sc_bus, device, 835 nfunctions, funcs); 836 } 837 for (j = 0; 838 j < 8 && (function = funcs[j]) < 8 && function >= 0; 839 j++) { 840 #else 841 for (function = 0; function < nfunctions; function++) { 842 #endif 843 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 844 && (locators[PCICF_FUNCTION] != function)) 845 continue; 846 847 if (qd != NULL && 848 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 849 continue; 850 tag = pci_make_tag(pc, sc->sc_bus, device, function); 851 ret = pci_probe_device1(sc, tag, match, cookie, pap); 852 if (match != NULL && ret != 0) 853 return ret; 854 } 855 } 856 return 0; 857 } 858 #endif /* PCI_MACHDEP_ENUMERATE_BUS1 */ 859 860 861 /* 862 * Vital Product Data (PCI 2.2) 863 */ 864 865 int 866 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 867 pcireg_t *data) 868 { 869 uint32_t reg; 870 int ofs, i, j; 871 872 KASSERT(data != NULL); 873 KASSERT((offset + count) < 0x7fff); 874 875 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 876 return 1; 877 878 for (i = 0; i < count; offset += sizeof(*data), i++) { 879 reg &= 0x0000ffff; 880 reg &= ~PCI_VPD_OPFLAG; 881 reg |= PCI_VPD_ADDRESS(offset); 882 pci_conf_write(pc, tag, ofs, reg); 883 884 /* 885 * PCI 2.2 does not specify how long we should poll 886 * for completion nor whether the operation can fail. 887 */ 888 j = 0; 889 do { 890 if (j++ == 20) 891 return 1; 892 delay(4); 893 reg = pci_conf_read(pc, tag, ofs); 894 } while ((reg & PCI_VPD_OPFLAG) == 0); 895 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 896 } 897 898 return 0; 899 } 900 901 int 902 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 903 pcireg_t *data) 904 { 905 pcireg_t reg; 906 int ofs, i, j; 907 908 KASSERT(data != NULL); 909 KASSERT((offset + count) < 0x7fff); 910 911 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 912 return 1; 913 914 for (i = 0; i < count; offset += sizeof(*data), i++) { 915 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 916 917 reg &= 0x0000ffff; 918 reg |= PCI_VPD_OPFLAG; 919 reg |= PCI_VPD_ADDRESS(offset); 920 pci_conf_write(pc, tag, ofs, reg); 921 922 /* 923 * PCI 2.2 does not specify how long we should poll 924 * for completion nor whether the operation can fail. 925 */ 926 j = 0; 927 do { 928 if (j++ == 20) 929 return 1; 930 delay(1); 931 reg = pci_conf_read(pc, tag, ofs); 932 } while (reg & PCI_VPD_OPFLAG); 933 } 934 935 return 0; 936 } 937 938 int 939 pci_dma64_available(const struct pci_attach_args *pa) 940 { 941 #ifdef _PCI_HAVE_DMA64 942 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 943 return 1; 944 #endif 945 return 0; 946 } 947 948 void 949 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 950 struct pci_conf_state *pcs) 951 { 952 int off; 953 954 for (off = 0; off < 16; off++) 955 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 956 957 /* For PCI-X */ 958 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 959 pcs->x_csr = pci_conf_read(pc, tag, off + PCIX_CMD); 960 961 /* For PCIe */ 962 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 963 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 964 unsigned int devtype; 965 966 devtype = PCIE_XCAP_TYPE(xcap); 967 pcs->e_dcr = (uint16_t)pci_conf_read(pc, tag, off + PCIE_DCSR); 968 969 if (PCIE_HAS_LINKREGS(devtype)) 970 pcs->e_lcr = (uint16_t)pci_conf_read(pc, tag, 971 off + PCIE_LCSR); 972 973 if ((xcap & PCIE_XCAP_SI) != 0) 974 pcs->e_slcr = (uint16_t)pci_conf_read(pc, tag, 975 off + PCIE_SLCSR); 976 977 if (PCIE_HAS_ROOTREGS(devtype)) 978 pcs->e_rcr = (uint16_t)pci_conf_read(pc, tag, 979 off + PCIE_RCR); 980 981 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 982 pcs->e_dcr2 = (uint16_t)pci_conf_read(pc, tag, 983 off + PCIE_DCSR2); 984 985 if (PCIE_HAS_LINKREGS(devtype)) 986 pcs->e_lcr2 = (uint16_t)pci_conf_read(pc, tag, 987 off + PCIE_LCSR2); 988 989 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 990 } 991 } 992 993 /* For MSI */ 994 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 995 bool bit64, pvmask; 996 997 pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 998 999 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1000 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1001 1002 /* Address */ 1003 pcs->msi_maddr = pci_conf_read(pc, tag, off + PCI_MSI_MADDR); 1004 if (bit64) 1005 pcs->msi_maddr64_hi = pci_conf_read(pc, tag, 1006 off + PCI_MSI_MADDR64_HI); 1007 1008 /* Data */ 1009 pcs->msi_mdata = pci_conf_read(pc, tag, 1010 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA)); 1011 1012 /* Per-vector masking */ 1013 if (pvmask) 1014 pcs->msi_mask = pci_conf_read(pc, tag, 1015 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK)); 1016 } 1017 1018 /* For MSI-X */ 1019 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1020 pcs->msix_ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 1021 } 1022 1023 void 1024 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 1025 struct pci_conf_state *pcs) 1026 { 1027 int off; 1028 pcireg_t val; 1029 1030 for (off = 15; off >= 0; off--) { 1031 val = pci_conf_read(pc, tag, (off * 4)); 1032 if (val != pcs->reg[off]) 1033 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 1034 } 1035 1036 /* For PCI-X */ 1037 if (pci_get_capability(pc, tag, PCI_CAP_PCIX, &off, NULL) != 0) 1038 pci_conf_write(pc, tag, off + PCIX_CMD, pcs->x_csr); 1039 1040 /* For PCIe */ 1041 if (pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS, &off, NULL) != 0) { 1042 pcireg_t xcap = pci_conf_read(pc, tag, off + PCIE_XCAP); 1043 unsigned int devtype; 1044 1045 devtype = PCIE_XCAP_TYPE(xcap); 1046 pci_conf_write(pc, tag, off + PCIE_DCSR, pcs->e_dcr); 1047 1048 /* 1049 * PCIe capability is variable sized. To not to write the next 1050 * area, check the existence of each register. 1051 */ 1052 if (PCIE_HAS_LINKREGS(devtype)) 1053 pci_conf_write(pc, tag, off + PCIE_LCSR, pcs->e_lcr); 1054 1055 if ((xcap & PCIE_XCAP_SI) != 0) 1056 pci_conf_write(pc, tag, off + PCIE_SLCSR, pcs->e_slcr); 1057 1058 if (PCIE_HAS_ROOTREGS(devtype)) 1059 pci_conf_write(pc, tag, off + PCIE_RCR, pcs->e_rcr); 1060 1061 if (__SHIFTOUT(xcap, PCIE_XCAP_VER_MASK) >= 2) { 1062 pci_conf_write(pc, tag, off + PCIE_DCSR2, pcs->e_dcr2); 1063 1064 if (PCIE_HAS_LINKREGS(devtype)) 1065 pci_conf_write(pc, tag, off + PCIE_LCSR2, 1066 pcs->e_lcr2); 1067 1068 /* XXX PCIE_SLCSR2 (It's reserved by the PCIe spec) */ 1069 } 1070 } 1071 1072 /* For MSI */ 1073 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) { 1074 pcireg_t reg; 1075 bool bit64, pvmask; 1076 1077 /* First, drop Enable bit in case it's already set. */ 1078 reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 1079 pci_conf_write(pc, tag, off + PCI_MSI_CTL, 1080 reg & ~PCI_MSI_CTL_MSI_ENABLE); 1081 1082 bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR; 1083 pvmask = pcs->msi_ctl & PCI_MSI_CTL_PERVEC_MASK; 1084 1085 /* Address */ 1086 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, pcs->msi_maddr); 1087 1088 if (bit64) 1089 pci_conf_write(pc, tag, 1090 off + PCI_MSI_MADDR64_HI, pcs->msi_maddr64_hi); 1091 1092 /* Data */ 1093 pci_conf_write(pc, tag, 1094 off + (bit64 ? PCI_MSI_MDATA64 : PCI_MSI_MDATA), 1095 pcs->msi_mdata); 1096 1097 /* Per-vector masking */ 1098 if (pvmask) 1099 pci_conf_write(pc, tag, 1100 off + (bit64 ? PCI_MSI_MASK64 : PCI_MSI_MASK), 1101 pcs->msi_mask); 1102 1103 /* Write CTRL register in the end */ 1104 pci_conf_write(pc, tag, off + PCI_MSI_CTL, pcs->msi_ctl); 1105 } 1106 1107 /* For MSI-X */ 1108 if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL) != 0) 1109 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, pcs->msix_ctl); 1110 } 1111 1112 /* 1113 * Power Management Capability (Rev 2.2) 1114 */ 1115 static int 1116 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 1117 int offset) 1118 { 1119 pcireg_t value, now; 1120 1121 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1122 now = value & PCI_PMCSR_STATE_MASK; 1123 switch (now) { 1124 case PCI_PMCSR_STATE_D0: 1125 case PCI_PMCSR_STATE_D1: 1126 case PCI_PMCSR_STATE_D2: 1127 case PCI_PMCSR_STATE_D3: 1128 *state = now; 1129 return 0; 1130 default: 1131 return EINVAL; 1132 } 1133 } 1134 1135 int 1136 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 1137 { 1138 int offset; 1139 pcireg_t value; 1140 1141 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 1142 return EOPNOTSUPP; 1143 1144 return pci_get_powerstate_int(pc, tag, state, offset); 1145 } 1146 1147 static int 1148 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 1149 int offset, pcireg_t cap_reg) 1150 { 1151 pcireg_t value, cap, now; 1152 1153 cap = cap_reg >> PCI_PMCR_SHIFT; 1154 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 1155 now = value & PCI_PMCSR_STATE_MASK; 1156 value &= ~PCI_PMCSR_STATE_MASK; 1157 1158 if (now == state) 1159 return 0; 1160 switch (state) { 1161 case PCI_PMCSR_STATE_D0: 1162 break; 1163 case PCI_PMCSR_STATE_D1: 1164 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1165 printf("invalid transition from %d to D1\n", (int)now); 1166 return EINVAL; 1167 } 1168 if (!(cap & PCI_PMCR_D1SUPP)) { 1169 printf("D1 not supported\n"); 1170 return EOPNOTSUPP; 1171 } 1172 break; 1173 case PCI_PMCSR_STATE_D2: 1174 if (now == PCI_PMCSR_STATE_D3) { 1175 printf("invalid transition from %d to D2\n", (int)now); 1176 return EINVAL; 1177 } 1178 if (!(cap & PCI_PMCR_D2SUPP)) { 1179 printf("D2 not supported\n"); 1180 return EOPNOTSUPP; 1181 } 1182 break; 1183 case PCI_PMCSR_STATE_D3: 1184 break; 1185 default: 1186 return EINVAL; 1187 } 1188 value |= state; 1189 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 1190 /* delay according to pcipm1.2, ch. 5.6.1 */ 1191 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1192 DELAY(10000); 1193 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1194 DELAY(200); 1195 1196 return 0; 1197 } 1198 1199 int 1200 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 1201 { 1202 int offset; 1203 pcireg_t value; 1204 1205 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 1206 printf("pci_set_powerstate not supported\n"); 1207 return EOPNOTSUPP; 1208 } 1209 1210 return pci_set_powerstate_int(pc, tag, state, offset, value); 1211 } 1212 1213 int 1214 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 1215 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 1216 { 1217 pcireg_t pmode; 1218 int error; 1219 1220 if ((error = pci_get_powerstate(pc, tag, &pmode))) 1221 return error; 1222 1223 switch (pmode) { 1224 case PCI_PMCSR_STATE_D0: 1225 break; 1226 case PCI_PMCSR_STATE_D3: 1227 if (wakefun == NULL) { 1228 /* 1229 * The card has lost all configuration data in 1230 * this state, so punt. 1231 */ 1232 aprint_error_dev(dev, 1233 "unable to wake up from power state D3\n"); 1234 return EOPNOTSUPP; 1235 } 1236 /*FALLTHROUGH*/ 1237 default: 1238 if (wakefun) { 1239 error = (*wakefun)(pc, tag, dev, pmode); 1240 if (error) 1241 return error; 1242 } 1243 aprint_normal_dev(dev, "waking up from power state D%d\n", 1244 pmode); 1245 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1246 return error; 1247 } 1248 return 0; 1249 } 1250 1251 int 1252 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 1253 device_t dev, pcireg_t state) 1254 { 1255 return 0; 1256 } 1257 1258 struct pci_child_power { 1259 struct pci_conf_state p_pciconf; 1260 pci_chipset_tag_t p_pc; 1261 pcitag_t p_tag; 1262 bool p_has_pm; 1263 int p_pm_offset; 1264 pcireg_t p_pm_cap; 1265 pcireg_t p_class; 1266 pcireg_t p_csr; 1267 }; 1268 1269 static bool 1270 pci_child_suspend(device_t dv, const pmf_qual_t *qual) 1271 { 1272 struct pci_child_power *priv = device_pmf_bus_private(dv); 1273 pcireg_t ocsr, csr; 1274 1275 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1276 1277 if (!priv->p_has_pm) 1278 return true; /* ??? hopefully handled by ACPI */ 1279 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 1280 return true; /* XXX */ 1281 1282 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 1283 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1284 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 1285 | PCI_COMMAND_MASTER_ENABLE); 1286 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1287 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1288 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1289 pci_conf_write(priv->p_pc, priv->p_tag, 1290 PCI_COMMAND_STATUS_REG, ocsr); 1291 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1292 return false; 1293 } 1294 return true; 1295 } 1296 1297 static void 1298 pci_pme_check_and_clear(device_t dv, pci_chipset_tag_t pc, pcitag_t tag, 1299 int off) 1300 { 1301 pcireg_t pmcsr; 1302 1303 pmcsr = pci_conf_read(pc, tag, off + PCI_PMCSR); 1304 1305 if (pmcsr & PCI_PMCSR_PME_STS) { 1306 /* Clear W1C bit */ 1307 pmcsr |= PCI_PMCSR_PME_STS; 1308 pci_conf_write(pc, tag, off + PCI_PMCSR, pmcsr); 1309 aprint_verbose_dev(dv, "Clear PME# now\n"); 1310 } 1311 } 1312 1313 static bool 1314 pci_child_resume(device_t dv, const pmf_qual_t *qual) 1315 { 1316 struct pci_child_power *priv = device_pmf_bus_private(dv); 1317 1318 if (priv->p_has_pm) { 1319 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 1320 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1321 aprint_error_dev(dv, 1322 "unsupported state, continuing.\n"); 1323 return false; 1324 } 1325 pci_pme_check_and_clear(dv, priv->p_pc, priv->p_tag, 1326 priv->p_pm_offset); 1327 } 1328 1329 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 1330 1331 return true; 1332 } 1333 1334 static bool 1335 pci_child_shutdown(device_t dv, int how) 1336 { 1337 struct pci_child_power *priv = device_pmf_bus_private(dv); 1338 pcireg_t csr; 1339 1340 /* restore original bus-mastering state */ 1341 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 1342 csr &= ~PCI_COMMAND_MASTER_ENABLE; 1343 csr |= priv->p_csr & PCI_COMMAND_MASTER_ENABLE; 1344 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 1345 return true; 1346 } 1347 1348 static void 1349 pci_child_deregister(device_t dv) 1350 { 1351 struct pci_child_power *priv = device_pmf_bus_private(dv); 1352 1353 free(priv, M_DEVBUF); 1354 } 1355 1356 static void 1357 pci_child_register(device_t child) 1358 { 1359 device_t self = device_parent(child); 1360 struct pci_softc *sc = device_private(self); 1361 struct pci_child_power *priv; 1362 int device, function, off; 1363 pcireg_t reg; 1364 1365 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1366 1367 device = device_locator(child, PCICF_DEV); 1368 function = device_locator(child, PCICF_FUNCTION); 1369 1370 priv->p_pc = sc->sc_pc; 1371 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 1372 function); 1373 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 1374 priv->p_csr = pci_conf_read(priv->p_pc, priv->p_tag, 1375 PCI_COMMAND_STATUS_REG); 1376 1377 if (pci_get_capability(priv->p_pc, priv->p_tag, 1378 PCI_CAP_PWRMGMT, &off, ®)) { 1379 priv->p_has_pm = true; 1380 priv->p_pm_offset = off; 1381 priv->p_pm_cap = reg; 1382 pci_pme_check_and_clear(child, priv->p_pc, priv->p_tag, off); 1383 } else { 1384 priv->p_has_pm = false; 1385 priv->p_pm_offset = -1; 1386 } 1387 1388 device_pmf_bus_register(child, priv, pci_child_suspend, 1389 pci_child_resume, pci_child_shutdown, pci_child_deregister); 1390 } 1391 1392 MODULE(MODULE_CLASS_DRIVER, pci, NULL); 1393 1394 static int 1395 pci_modcmd(modcmd_t cmd, void *priv) 1396 { 1397 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI) 1398 return 0; 1399 return ENOTTY; 1400 } 1401
Indexes created Sat Sep 20 22:09:52 GMT 2025