1 /* $NetBSD: machdep.c,v 1.49 2022/07/22 20:09:47 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.49 2022/07/22 20:09:47 thorpej Exp $"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_multiprocessor.h" 45 #include "opt_pci.h" 46 #include "gpio.h" 47 #include "pci.h" 48 49 #define DDRC_PRIVATE 50 #define GLOBAL_PRIVATE 51 #define L2CACHE_PRIVATE 52 #define _POWERPC_BUS_DMA_PRIVATE 53 54 #include <sys/param.h> 55 #include <sys/cpu.h> 56 #include <sys/intr.h> 57 #include <sys/msgbuf.h> 58 #include <sys/tty.h> 59 #include <sys/kcore.h> 60 #include <sys/bitops.h> 61 #include <sys/bus.h> 62 #include <sys/extent.h> 63 #include <sys/reboot.h> 64 #include <sys/module.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <prop/proplib.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/comreg.h> 73 #include <dev/ic/comvar.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 #include <dev/mii/miivar.h> 78 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 struct uboot_bdinfo { 96 uint32_t bd_memstart; 97 uint32_t bd_memsize; 98 uint32_t bd_flashstart; 99 uint32_t bd_flashsize; 100 /*10*/ uint32_t bd_flashoffset; 101 uint32_t bd_sramstart; 102 uint32_t bd_sramsize; 103 uint32_t bd_immrbase; 104 /*20*/ uint32_t bd_bootflags; 105 uint32_t bd_ipaddr; 106 uint8_t bd_etheraddr[6]; 107 uint16_t bd_ethspeed; 108 /*30*/ uint32_t bd_intfreq; 109 uint32_t bd_cpufreq; 110 uint32_t bd_baudrate; 111 /*3c*/ uint8_t bd_etheraddr1[6]; 112 /*42*/ uint8_t bd_etheraddr2[6]; 113 /*48*/ uint8_t bd_etheraddr3[6]; 114 /*4e*/ uint16_t bd_pad; 115 }; 116 117 char root_string[16]; 118 119 /* 120 * booke kernels need to set module_machine to this for modules to work. 121 */ 122 char module_machine_booke[] = "powerpc-booke"; 123 124 void initppc(vaddr_t, vaddr_t, void *, void *, char *, char *); 125 126 #define MEMREGIONS 4 127 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 128 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 129 static u_int nmemr; 130 131 #ifndef CONSFREQ 132 # define CONSFREQ -1 /* inherit from firmware */ 133 #endif 134 #ifndef CONSPEED 135 # define CONSPEED 115200 136 #endif 137 #ifndef CONMODE 138 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 139 #endif 140 #ifndef CONSADDR 141 # define CONSADDR DUART2_BASE 142 #endif 143 144 int comcnfreq = CONSFREQ; 145 int comcnspeed = CONSPEED; 146 tcflag_t comcnmode = CONMODE; 147 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 148 149 #if NPCI > 0 150 struct extent *pcimem_ex; 151 struct extent *pciio_ex; 152 #endif 153 154 struct powerpc_bus_space gur_bst = { 155 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 156 .pbs_offset = GUR_BASE, 157 .pbs_limit = GUR_SIZE, 158 }; 159 160 struct powerpc_bus_space gur_le_bst = { 161 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 162 .pbs_offset = GUR_BASE, 163 .pbs_limit = GUR_SIZE, 164 }; 165 166 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 167 168 #if defined(SYS_CLK) 169 static uint64_t e500_sys_clk = SYS_CLK; 170 #endif 171 #ifdef CADMUS 172 static uint8_t cadmus_pci; 173 static uint8_t cadmus_csr; 174 #ifndef SYS_CLK 175 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 176 #endif 177 #elif defined(PIXIS) 178 static const uint32_t pixis_spd_map[8] = { 179 [PX_SPD_33MHZ] = 33333333, 180 [PX_SPD_40MHZ] = 40000000, 181 [PX_SPD_50MHZ] = 50000000, 182 [PX_SPD_66MHZ] = 66666666, 183 [PX_SPD_83MHZ] = 83333333, 184 [PX_SPD_100MHZ] = 100000000, 185 [PX_SPD_133MHZ] = 133333333, 186 [PX_SPD_166MHZ] = 166666667, 187 }; 188 static uint8_t pixis_spd; 189 #ifndef SYS_CLK 190 static uint64_t e500_sys_clk; 191 #endif 192 #elif !defined(SYS_CLK) 193 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 194 #endif 195 196 static int e500_cngetc(dev_t); 197 static void e500_cnputc(dev_t, int); 198 199 static struct consdev e500_earlycons = { 200 .cn_getc = e500_cngetc, 201 .cn_putc = e500_cnputc, 202 .cn_pollc = nullcnpollc, 203 }; 204 205 /* 206 * List of port-specific devices to attach to the processor local bus. 207 */ 208 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 209 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 210 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 211 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 212 #if defined(MPC8572) || defined(P2020) || defined(P1025) \ 213 || defined(P1023) 214 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 215 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 216 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 217 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 218 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 219 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 220 #endif 221 { "wdog" }, /* not a real device */ 222 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 223 1, { ISOURCE_DUART }, 224 1 + ilog2(DEVDISR_DUART) }, 225 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 226 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 227 1 + ilog2(DEVDISR_TSEC1), 228 { 0xffff, SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 229 #if defined(P1025) 230 { "mdio", ETSEC1_BASE, ETSEC_SIZE, 1, 231 0, { }, 232 1 + ilog2(DEVDISR_TSEC1), 233 { SVR_P1025v1 >> 16 } }, 234 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 235 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 236 1 + ilog2(DEVDISR_TSEC1), 237 { SVR_P1025v1 >> 16 } }, 238 #if 0 239 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 240 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 241 ISOURCE_ETSEC1_G1_ERR }, 242 1 + ilog2(DEVDISR_TSEC1), 243 { SVR_P1025v1 >> 16 } }, 244 #endif 245 #endif 246 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 247 || defined(P2020) 248 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 249 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 250 1 + ilog2(DEVDISR_TSEC2), 251 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 252 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 253 SVR_P1025v1 >> 16 } }, 254 #endif 255 #if defined(P1025) 256 { "mdio", ETSEC2_BASE, ETSEC_SIZE, 2, 257 0, { }, 258 1 + ilog2(DEVDISR_TSEC2), 259 { SVR_P1025v1 >> 16 } }, 260 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 261 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 262 1 + ilog2(DEVDISR_TSEC2), 263 { SVR_P1025v1 >> 16 } }, 264 #if 0 265 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 266 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 267 ISOURCE_ETSEC2_G1_ERR }, 268 1 + ilog2(DEVDISR_TSEC2), 269 { SVR_P1025v1 >> 16 } }, 270 #endif 271 #endif 272 #if defined(MPC8544) || defined(MPC8536) 273 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 274 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 275 1 + ilog2(DEVDISR_TSEC3), 276 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 277 #endif 278 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 279 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 280 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 281 1 + ilog2(DEVDISR_TSEC3), 282 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 283 SVR_P2020v2 >> 16 } }, 284 #endif 285 #if defined(P1025) 286 { "mdio", ETSEC3_BASE, ETSEC_SIZE, 3, 287 0, { }, 288 1 + ilog2(DEVDISR_TSEC3), 289 { SVR_P1025v1 >> 16 } }, 290 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 291 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 292 1 + ilog2(DEVDISR_TSEC3), 293 { SVR_P1025v1 >> 16 } }, 294 #if 0 295 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 296 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 297 ISOURCE_ETSEC3_G1_ERR }, 298 1 + ilog2(DEVDISR_TSEC3), 299 { SVR_P1025v1 >> 16 } }, 300 #endif 301 #endif 302 #if defined(MPC8548) || defined(MPC8572) 303 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 304 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 305 1 + ilog2(DEVDISR_TSEC4), 306 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 307 #endif 308 { "diic", I2C1_BASE, I2C_SIZE, 0, 309 1, { ISOURCE_I2C }, 310 1 + ilog2(DEVDISR_I2C) }, 311 { "diic", I2C2_BASE, I2C_SIZE, 1, 312 1, { ISOURCE_I2C }, 313 1 + ilog2(DEVDISR_I2C) }, 314 /* MPC8572 doesn't have any GPIO */ 315 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 316 1, { ISOURCE_GPIO }, 317 0, 318 { 0xffff, SVR_MPC8572v1 >> 16 } }, 319 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 320 1, { ISOURCE_DDR }, 321 1 + ilog2(DEVDISR_DDR_15), 322 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 323 #if defined(MPC8536) 324 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 325 1, { ISOURCE_DDR }, 326 1 + ilog2(DEVDISR_DDR_16), 327 { SVR_MPC8536v1 >> 16 } }, 328 #endif 329 #if defined(MPC8572) 330 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 331 1, { ISOURCE_DDR }, 332 1 + ilog2(DEVDISR_DDR_15), 333 { SVR_MPC8572v1 >> 16 } }, 334 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 335 1, { ISOURCE_DDR }, 336 1 + ilog2(DEVDISR_DDR2_14), 337 { SVR_MPC8572v1 >> 16 } }, 338 #endif 339 { "lbc", LBC_BASE, LBC_SIZE, 0, 340 1, { ISOURCE_LBC }, 341 1 + ilog2(DEVDISR_LBC) }, 342 #if defined(MPC8544) || defined(MPC8536) 343 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 344 1, { ISOURCE_PCIEX }, 345 1 + ilog2(DEVDISR_PCIE), 346 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 347 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 348 1, { ISOURCE_PCIEX2 }, 349 1 + ilog2(DEVDISR_PCIE2), 350 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 351 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 352 1, { ISOURCE_PCIEX3 }, 353 1 + ilog2(DEVDISR_PCIE3), 354 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 355 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 356 1, { ISOURCE_PCI1 }, 357 1 + ilog2(DEVDISR_PCI1), 358 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 359 #endif 360 #ifdef MPC8548 361 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 362 1, { ISOURCE_PCIEX }, 363 1 + ilog2(DEVDISR_PCIE), 364 { SVR_MPC8548v1 >> 16 }, }, 365 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 366 1, { ISOURCE_PCI1 }, 367 1 + ilog2(DEVDISR_PCI1), 368 { SVR_MPC8548v1 >> 16 }, }, 369 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 370 1, { ISOURCE_PCI2 }, 371 1 + ilog2(DEVDISR_PCI2), 372 { SVR_MPC8548v1 >> 16 }, }, 373 #endif 374 #if defined(MPC8572) || defined(P1025) || defined(P2020) \ 375 || defined(P1023) 376 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 377 1, { ISOURCE_PCIEX }, 378 1 + ilog2(DEVDISR_PCIE), 379 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 380 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 381 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 382 1, { ISOURCE_PCIEX2 }, 383 1 + ilog2(DEVDISR_PCIE2), 384 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 385 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 386 #endif 387 #if defined(MPC8572) || defined(P2020) || defined(_P1023) 388 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 389 1, { ISOURCE_PCIEX3_MPC8572 }, 390 1 + ilog2(DEVDISR_PCIE3), 391 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 392 SVR_P1023v1 >> 16 } }, 393 #endif 394 #if defined(MPC8536) || defined(P1025) || defined(P2020) \ 395 || defined(P1023) 396 { "ehci", USB1_BASE, USB_SIZE, 1, 397 1, { ISOURCE_USB1 }, 398 1 + ilog2(DEVDISR_USB1), 399 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 400 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 401 #endif 402 #ifdef MPC8536 403 { "ehci", USB2_BASE, USB_SIZE, 2, 404 1, { ISOURCE_USB2 }, 405 1 + ilog2(DEVDISR_USB2), 406 { SVR_MPC8536v1 >> 16 }, }, 407 { "ehci", USB3_BASE, USB_SIZE, 3, 408 1, { ISOURCE_USB3 }, 409 1 + ilog2(DEVDISR_USB3), 410 { SVR_MPC8536v1 >> 16 }, }, 411 { "sata", SATA1_BASE, SATA_SIZE, 1, 412 1, { ISOURCE_SATA1 }, 413 1 + ilog2(DEVDISR_SATA1), 414 { SVR_MPC8536v1 >> 16 }, }, 415 { "sata", SATA2_BASE, SATA_SIZE, 2, 416 1, { ISOURCE_SATA2 }, 417 1 + ilog2(DEVDISR_SATA2), 418 { SVR_MPC8536v1 >> 16 }, }, 419 { "spi", SPI_BASE, SPI_SIZE, 0, 420 1, { ISOURCE_SPI }, 421 1 + ilog2(DEVDISR_SPI_15), 422 { SVR_MPC8536v1 >> 16 }, }, 423 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 424 1, { ISOURCE_ESDHC }, 425 1 + ilog2(DEVDISR_ESDHC_12), 426 { SVR_MPC8536v1 >> 16 }, }, 427 #endif 428 #if defined(P1025) || defined(P2020) || defined(P1023) 429 { "spi", SPI_BASE, SPI_SIZE, 0, 430 1, { ISOURCE_SPI }, 431 1 + ilog2(DEVDISR_SPI_28), 432 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16, 433 SVR_P1023v1 >> 16 }, }, 434 #endif 435 #if defined(P1025) || defined(P2020) 436 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 437 1, { ISOURCE_ESDHC }, 438 1 + ilog2(DEVDISR_ESDHC_10), 439 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 440 #endif 441 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 442 { NULL } 443 }; 444 445 static int 446 e500_cngetc(dev_t dv) 447 { 448 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 449 450 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 451 return -1; 452 453 return com0addr[com_data] & 0xff; 454 } 455 456 static void 457 e500_cnputc(dev_t dv, int c) 458 { 459 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 460 int timo = 150000; 461 462 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 463 ; 464 465 com0addr[com_data] = c; 466 __asm("mbar"); 467 468 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 469 ; 470 } 471 472 static void * 473 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 474 { 475 if (prefetchable) 476 return NULL; 477 if (pa < gur_bst.pbs_offset) 478 return NULL; 479 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 480 return NULL; 481 return (void *)pa; 482 } 483 484 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 485 486 static void 487 e500_cpu_reset(void) 488 { 489 __asm volatile("sync"); 490 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 491 __asm volatile("msync;isync"); 492 } 493 494 static psize_t 495 memprobe(vaddr_t endkernel) 496 { 497 phys_ram_seg_t *mr; 498 paddr_t boot_page = cpu_read_4(GUR_BPTR); 499 printf(" bptr=%"PRIxPADDR, boot_page); 500 if (boot_page & BPTR_EN) { 501 /* 502 * shift it to an address 503 */ 504 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 505 } else { 506 boot_page = ~(paddr_t)0; 507 } 508 509 /* 510 * First we need to find out how much physical memory we have. 511 * We could let our bootloader tell us, but it's almost as easy 512 * to ask the DDR memory controller. 513 */ 514 mr = physmemr; 515 for (u_int i = 0; i < 4; i++) { 516 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 517 if (v & CS_CONFIG_EN) { 518 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 519 if (v == 0) 520 continue; 521 mr->start = BNDS_SA_GET(v); 522 mr->size = BNDS_SIZE_GET(v); 523 #ifdef MEMSIZE 524 if (mr->start >= MEMSIZE) 525 continue; 526 if (mr->start + mr->size > MEMSIZE) 527 mr->size = MEMSIZE - mr->start; 528 #endif 529 #if 0 530 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 531 mr - physmemr, mr->size, mr->start); 532 #endif 533 mr++; 534 } 535 } 536 537 if (mr == physmemr) 538 panic("no memory configured!"); 539 540 /* 541 * Sort memory regions from low to high and coalesce adjacent regions 542 */ 543 u_int cnt = mr - physmemr; 544 if (cnt > 1) { 545 for (u_int i = 0; i < cnt - 1; i++) { 546 for (u_int j = i + 1; j < cnt; j++) { 547 if (physmemr[j].start < physmemr[i].start) { 548 phys_ram_seg_t tmp = physmemr[i]; 549 physmemr[i] = physmemr[j]; 550 physmemr[j] = tmp; 551 } 552 } 553 } 554 mr = physmemr; 555 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 556 if (mr->start + mr->size == mr[1].start) { 557 mr->size += mr[1].size; 558 for (u_int j = 1; i + j + 1 < cnt; j++) 559 mr[j] = mr[j+1]; 560 cnt--; 561 } 562 } 563 } else if (cnt == 0) { 564 panic("%s: no memory found", __func__); 565 } 566 567 /* 568 * Copy physical memory to available memory. 569 */ 570 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 571 572 /* 573 * Adjust available memory to skip kernel at start of memory. 574 */ 575 availmemr[0].size -= endkernel - availmemr[0].start; 576 availmemr[0].start = endkernel; 577 578 mr = availmemr; 579 for (u_int i = 0; i < cnt; i++, mr++) { 580 /* 581 * U-boot reserves a boot-page on multi-core chips. 582 * We need to make sure that we never disturb it. 583 */ 584 const paddr_t mr_end = mr->start + mr->size; 585 if (mr_end > boot_page && boot_page >= mr->start) { 586 /* 587 * Normally u-boot will put in at the end 588 * of memory. But in case it doesn't, deal 589 * with all possibilities. 590 */ 591 if (boot_page + PAGE_SIZE == mr_end) { 592 mr->size -= PAGE_SIZE; 593 } else if (boot_page == mr->start) { 594 mr->start += PAGE_SIZE; 595 mr->size -= PAGE_SIZE; 596 } else { 597 mr->size = boot_page - mr->start; 598 mr++; 599 for (u_int j = cnt; j > i + 1; j--) { 600 availmemr[j] = availmemr[j-1]; 601 } 602 cnt++; 603 mr->start = boot_page + PAGE_SIZE; 604 mr->size = mr_end - mr->start; 605 } 606 break; 607 } 608 } 609 610 /* 611 * Steal pages at the end of memory for the kernel message buffer. 612 */ 613 mr = availmemr + cnt - 1; 614 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 615 mr->size -= round_page(MSGBUFSIZE); 616 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 617 618 /* 619 * Calculate physmem. 620 */ 621 for (u_int i = 0; i < cnt; i++) 622 physmem += atop(physmemr[i].size); 623 624 nmemr = cnt; 625 return physmemr[cnt-1].start + physmemr[cnt-1].size; 626 } 627 628 void 629 consinit(void) 630 { 631 static bool attached = false; 632 633 if (attached) 634 return; 635 attached = true; 636 637 if (comcnfreq == -1) { 638 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 639 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 640 comcnfreq = e500_sys_clk * plat_ratio; 641 printf(" comcnfreq=%u", comcnfreq); 642 } 643 644 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 645 COM_TYPE_NORMAL, comcnmode); 646 } 647 648 void 649 cpu_probe_cache(void) 650 { 651 struct cpu_info * const ci = curcpu(); 652 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 653 const int dcache_assoc = L1CFG_CNWAY_GET(l1cfg0); 654 655 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 656 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 657 658 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 659 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 660 661 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 662 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 663 } else { 664 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 665 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 666 } 667 668 /* 669 * Possibly recolor. 670 */ 671 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / dcache_assoc)); 672 673 #ifdef DEBUG 674 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 675 if ((L1CSR_CE & l1csr0) == 0) 676 printf(" DC=off"); 677 678 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 679 if ((L1CSR_CE & l1csr1) == 0) 680 printf(" IC=off"); 681 #endif 682 } 683 684 static uint16_t 685 getsvr(void) 686 { 687 uint16_t svr = mfspr(SPR_SVR) >> 16; 688 689 svr &= ~0x8; /* clear security bit */ 690 switch (svr) { 691 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 692 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 693 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 694 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 695 case SVR_P1017v1 >> 16: return SVR_P1023v1 >> 16; 696 default: return svr; 697 } 698 } 699 700 static const char * 701 socname(uint32_t svr) 702 { 703 svr &= ~0x80000; /* clear security bit */ 704 switch (svr >> 8) { 705 case SVR_MPC8533 >> 8: return "MPC8533"; 706 case SVR_MPC8536v1 >> 8: return "MPC8536"; 707 case SVR_MPC8541v1 >> 8: return "MPC8541"; 708 case SVR_MPC8543v2 >> 8: return "MPC8543"; 709 case SVR_MPC8544v1 >> 8: return "MPC8544"; 710 case SVR_MPC8545v2 >> 8: return "MPC8545"; 711 case SVR_MPC8547v2 >> 8: return "MPC8547"; 712 case SVR_MPC8548v2 >> 8: return "MPC8548"; 713 case SVR_MPC8555v1 >> 8: return "MPC8555"; 714 case SVR_MPC8568v1 >> 8: return "MPC8568"; 715 case SVR_MPC8567v1 >> 8: return "MPC8567"; 716 case SVR_MPC8572v1 >> 8: return "MPC8572"; 717 case SVR_P2020v2 >> 8: return "P2020"; 718 case SVR_P2010v2 >> 8: return "P2010"; 719 case SVR_P1016v1 >> 8: return "P1016"; 720 case SVR_P1017v1 >> 8: return "P1017"; 721 case SVR_P1023v1 >> 8: return "P1023"; 722 case SVR_P1025v1 >> 8: return "P1025"; 723 default: 724 panic("%s: unknown SVR %#x", __func__, svr); 725 } 726 } 727 728 static void 729 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 730 { 731 static const char units[16] = "KKKKKMMMMMGGGGGT"; 732 733 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 734 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 735 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 736 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 737 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 738 739 aprint_normal_dev(self, "%s:", name); 740 741 aprint_normal(" %u", nentries); 742 if (TLBCFG_AVAIL_P(tlbcfg)) { 743 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 744 minsize, maxsize, units[maxsize_log4k]); 745 } else { 746 aprint_normal(" fixed-size (%uKB)", minsize); 747 } 748 if (assoc == 0 || assoc == nentries) 749 aprint_normal(" fully"); 750 else 751 aprint_normal(" %u-way set", assoc); 752 aprint_normal(" associative entries\n"); 753 } 754 755 static void 756 cpu_print_info(struct cpu_info *ci) 757 { 758 uint64_t freq = board_info_get_number("processor-frequency"); 759 device_t self = ci->ci_dev; 760 761 char freqbuf[10]; 762 if (freq >= 999500000) { 763 const uint32_t freq32 = (freq + 500000) / 10000000; 764 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 765 freq32 / 100, freq32 % 100); 766 } else { 767 const uint32_t freq32 = (freq + 500000) / 1000000; 768 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 769 } 770 771 const uint32_t pvr = mfpvr(); 772 const uint32_t svr = mfspr(SPR_SVR); 773 const uint32_t pir = mfspr(SPR_PIR); 774 775 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 776 "ID %u%s\n", 777 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 778 (svr >> 4) & 15, svr & 15, 779 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 780 (pvr >> 4) & 15, pvr & 15, 781 pir, (pir == 0 ? " (Primary)" : "")); 782 783 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 784 aprint_normal_dev(self, 785 "%uKB/%uB %u-way L1 %s cache\n", 786 L1CFG_CSIZE_GET(l1cfg0) >> 10, 787 32 << L1CFG_CBSIZE_GET(l1cfg0), 788 L1CFG_CNWAY_GET(l1cfg0), 789 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 790 ? "data" : "unified"); 791 792 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 793 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 794 aprint_normal_dev(self, 795 "%uKB/%uB %u-way L1 %s cache\n", 796 L1CFG_CSIZE_GET(l1cfg1) >> 10, 797 32 << L1CFG_CBSIZE_GET(l1cfg1), 798 L1CFG_CNWAY_GET(l1cfg1), 799 "instruction"); 800 } 801 802 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 803 aprint_normal_dev(self, 804 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 805 MMUCFG_NTLBS_GET(mmucfg) + 1, 806 MMUCFG_NPIDS_GET(mmucfg), 807 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 808 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 809 810 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 811 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 812 } 813 814 #ifdef MULTIPROCESSOR 815 static void 816 e500_cpu_spinup(device_t self, struct cpu_info *ci) 817 { 818 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 819 struct pglist splist; 820 821 if (spinup_table_addr == 0) { 822 aprint_error_dev(self, "hatch failed (no spin-up table)"); 823 return; 824 } 825 826 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 827 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 828 const size_t id = cpu_index(ci); 829 kcpuset_t * const hatchlings = cpuset_info.cpus_hatched; 830 831 if (h->hatch_sp == 0) { 832 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 833 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 834 if (error) { 835 aprint_error_dev(self, 836 "unable to allocate hatch stack\n"); 837 return; 838 } 839 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 840 + PAGE_SIZE - CALLFRAMELEN; 841 } 842 843 844 for (size_t i = 1; e[i].entry_pir != 0; i++) { 845 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 846 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 847 if (e[i].entry_pir == ci->ci_cpuid) { 848 849 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 850 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 851 ci->ci_curpm = pmap_kernel(); 852 ci->ci_lasttb = cpu_info[0].ci_lasttb; 853 ci->ci_data.cpu_cc_freq = 854 cpu_info[0].ci_data.cpu_cc_freq; 855 856 h->hatch_self = self; 857 h->hatch_ci = ci; 858 h->hatch_running = -1; 859 h->hatch_pir = e[i].entry_pir; 860 h->hatch_hid0 = mfspr(SPR_HID0); 861 u_int tlbidx; 862 e500_tlb_lookup_xtlb(0, &tlbidx); 863 h->hatch_tlbidx = tlbidx; 864 KASSERT(h->hatch_sp != 0); 865 /* 866 * Get new timebase. We don't want to deal with 867 * timebase crossing a 32-bit boundary so make sure 868 * that we have enough headroom to do the timebase 869 * synchronization. 870 */ 871 #define TBSYNC_SLOP 2000 872 uint32_t tbl; 873 uint32_t tbu; 874 do { 875 tbu = mfspr(SPR_RTBU); 876 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 877 } while (tbl < TBSYNC_SLOP); 878 879 h->hatch_tbu = tbu; 880 h->hatch_tbl = tbl; 881 __asm("sync;isync"); 882 dcache_wbinv((vaddr_t)h, sizeof(*h)); 883 884 /* 885 * And here we go... 886 */ 887 e[i].entry_addr_lower = 888 (uint32_t)e500_spinup_trampoline; 889 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 890 __asm __volatile("sync;isync"); 891 __insn_barrier(); 892 893 for (u_int timo = 0; timo++ < 10000; ) { 894 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 895 if (e[i].entry_addr_lower == 3) { 896 #if 0 897 printf( 898 "%s: cpu%u started in %u spins\n", 899 __func__, cpu_index(ci), timo); 900 #endif 901 break; 902 } 903 } 904 for (u_int timo = 0; timo++ < 10000; ) { 905 dcache_inv((vaddr_t)h, sizeof(*h)); 906 if (h->hatch_running == 0) { 907 #if 0 908 printf( 909 "%s: cpu%u cracked in %u spins: (running=%d)\n", 910 __func__, cpu_index(ci), 911 timo, h->hatch_running); 912 #endif 913 break; 914 } 915 } 916 if (h->hatch_running == -1) { 917 aprint_error_dev(self, 918 "hatch failed (timeout): running=%d" 919 ", entry=%#x\n", 920 h->hatch_running, e[i].entry_addr_lower); 921 goto out; 922 } 923 924 /* 925 * First then we do is to synchronize timebases. 926 * TBSYNC_SLOP*16 should be more than enough 927 * instructions. 928 */ 929 while (tbl != mftbl()) 930 continue; 931 h->hatch_running = 1; 932 dcache_wbinv((vaddr_t)h, sizeof(*h)); 933 __asm("sync;isync"); 934 __insn_barrier(); 935 printf("%s: cpu%u set to running\n", 936 __func__, cpu_index(ci)); 937 938 for (u_int timo = 10000; timo-- > 0; ) { 939 dcache_inv((vaddr_t)h, sizeof(*h)); 940 if (h->hatch_running > 1) 941 break; 942 } 943 if (h->hatch_running == 1) { 944 printf( 945 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 946 __func__, 947 ((int64_t)tbu << 32) + tbl, 948 (int64_t) 949 (((uint64_t)h->hatch_tbu << 32) 950 + (uint64_t)h->hatch_tbl), 951 h->hatch_running); 952 goto out; 953 } 954 printf( 955 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 956 __func__, 957 (int64_t) 958 (((uint64_t)h->hatch_tbu << 32) 959 + (uint64_t)h->hatch_tbl), 960 h->hatch_running); 961 /* 962 * Now we wait for the hatching to complete. 30ms 963 * should be long enough. 964 */ 965 for (u_int timo = 30000; timo-- > 0; ) { 966 if (kcpuset_isset(hatchlings, id)) { 967 aprint_normal_dev(self, 968 "hatch successful (%u spins, " 969 "timebase adjusted by %"PRId64")\n", 970 30000 - timo, 971 (int64_t) 972 (((uint64_t)h->hatch_tbu << 32) 973 + (uint64_t)h->hatch_tbl)); 974 goto out; 975 } 976 DELAY(1); 977 } 978 979 aprint_error_dev(self, 980 "hatch failed (timeout): running=%u\n", 981 h->hatch_running); 982 goto out; 983 } 984 } 985 986 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 987 ci->ci_cpuid); 988 out: 989 if (h->hatch_sp == 0) 990 uvm_pglistfree(&splist); 991 } 992 #endif 993 994 void 995 e500_cpu_hatch(struct cpu_info *ci) 996 { 997 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 998 999 /* 1000 * Make sure interrupts are blocked. 1001 */ 1002 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1003 1004 /* Set the MAS4 defaults */ 1005 mtspr(SPR_MAS4, MAS4_TSIZED_4KB | MAS4_MD); 1006 tlb_invalidate_all(); 1007 1008 intr_cpu_hatch(ci); 1009 1010 cpu_probe_cache(); 1011 cpu_print_info(ci); 1012 1013 /* 1014 */ 1015 } 1016 1017 static void 1018 e500_cpu_attach(device_t self, u_int instance) 1019 { 1020 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 1021 1022 if (instance > 1) { 1023 #if defined(MULTIPROCESSOR) 1024 ci->ci_idepth = -1; 1025 device_set_private(self, ci); 1026 1027 ci->ci_cpuid = instance - (instance > 0); 1028 ci->ci_dev = self; 1029 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 1030 1031 mi_cpu_attach(ci); 1032 1033 intr_cpu_attach(ci); 1034 cpu_evcnt_attach(ci); 1035 1036 e500_cpu_spinup(self, ci); 1037 return; 1038 #else 1039 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 1040 return; 1041 #endif 1042 } 1043 1044 device_set_private(self, ci); 1045 1046 ci->ci_cpuid = instance - (instance > 0); 1047 ci->ci_dev = self; 1048 1049 intr_cpu_attach(ci); 1050 cpu_evcnt_attach(ci); 1051 1052 KASSERT(ci == curcpu()); 1053 intr_cpu_hatch(ci); 1054 1055 cpu_print_info(ci); 1056 } 1057 1058 void 1059 e500_ipi_halt(void) 1060 { 1061 #ifdef MULTIPROCESSOR 1062 struct cpuset_info * const csi = &cpuset_info; 1063 const cpuid_t index = cpu_index(curcpu()); 1064 1065 printf("cpu%lu: shutting down\n", index); 1066 kcpuset_set(csi->cpus_halted, index); 1067 #endif 1068 register_t msr, hid0; 1069 1070 msr = wrtee(0); 1071 1072 hid0 = mfspr(SPR_HID0); 1073 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1074 mtspr(SPR_HID0, hid0); 1075 1076 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1077 mtmsr(msr); 1078 for (;;); /* loop forever */ 1079 } 1080 1081 1082 static void 1083 calltozero(void) 1084 { 1085 panic("call to 0 from %p", __builtin_return_address(0)); 1086 } 1087 1088 #if !defined(ROUTERBOOT) 1089 static void 1090 parse_cmdline(char *cp) 1091 { 1092 int ourhowto = 0; 1093 char c; 1094 bool opt = false; 1095 for (; (c = *cp) != '\0'; cp++) { 1096 if (c == '-') { 1097 opt = true; 1098 continue; 1099 } 1100 if (c == ' ') { 1101 opt = false; 1102 continue; 1103 } 1104 if (opt) { 1105 switch (c) { 1106 case 'a': ourhowto |= RB_ASKNAME; break; 1107 case 'd': ourhowto |= AB_DEBUG; break; 1108 case 'q': ourhowto |= AB_QUIET; break; 1109 case 's': ourhowto |= RB_SINGLE; break; 1110 case 'v': ourhowto |= AB_VERBOSE; break; 1111 } 1112 continue; 1113 } 1114 strlcpy(root_string, cp, sizeof(root_string)); 1115 break; 1116 } 1117 if (ourhowto) { 1118 boothowto |= ourhowto; 1119 printf(" boothowto=%#x(%#x)", boothowto, ourhowto); 1120 } 1121 if (root_string[0]) 1122 printf(" root=%s", root_string); 1123 } 1124 #endif /* !ROUTERBOOT */ 1125 1126 void 1127 initppc(vaddr_t startkernel, vaddr_t endkernel, 1128 void *a0, void *a1, char *a2, char *a3) 1129 { 1130 struct cpu_info * const ci = curcpu(); 1131 struct cpu_softc * const cpu = ci->ci_softc; 1132 1133 cn_tab = &e500_earlycons; 1134 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1135 startkernel, endkernel, a0, a1, a2, a3); 1136 1137 #if !defined(ROUTERBOOT) 1138 if (a2[0] != '\0') 1139 printf(" consdev=<%s>", a2); 1140 if (a3[0] != '\0') { 1141 printf(" cmdline=<%s>", a3); 1142 parse_cmdline(a3); 1143 } 1144 #endif /* !ROUTERBOOT */ 1145 1146 /* 1147 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1148 * DOZE is ok. 1149 */ 1150 const register_t hid0 = mfspr(SPR_HID0); 1151 mtspr(SPR_HID0, 1152 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1153 #ifdef CADMUS 1154 /* 1155 * Need to cache this from cadmus since we need to unmap cadmus since 1156 * it falls in the middle of kernel address space. 1157 */ 1158 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1159 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1160 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1161 printf(" cadmus_pci=%#x", cadmus_pci); 1162 printf(" cadmus_csr=%#x", cadmus_csr); 1163 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1164 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1165 e500_sys_clk *= 2; 1166 } 1167 #endif 1168 #ifdef PIXIS 1169 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1170 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1171 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1172 #ifndef SYS_CLK 1173 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1174 #else 1175 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1176 #endif 1177 #endif 1178 printf(" porpllsr=0x%08x", 1179 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1180 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1181 1182 /* 1183 * Make sure arguments are page aligned. 1184 */ 1185 startkernel = trunc_page(startkernel); 1186 endkernel = round_page(endkernel); 1187 1188 /* 1189 * Initialize the bus space tag used to access the 85xx general 1190 * utility registers. It doesn't need to be extent protected. 1191 * We know the GUR is mapped via a TLB1 entry so we add a limited 1192 * mapiodev which allows mappings in GUR space. 1193 */ 1194 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1195 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1196 bus_space_init(&gur_bst, NULL, NULL, 0); 1197 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1198 cpu->cpu_bst = &gur_bst; 1199 cpu->cpu_le_bst = &gur_le_bst; 1200 cpu->cpu_bsh = gur_bsh; 1201 1202 /* 1203 * Attach the console early, really early. 1204 */ 1205 consinit(); 1206 1207 /* 1208 * Reset the PIC to a known state. 1209 */ 1210 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1211 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1212 ; 1213 #if 0 1214 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1215 #endif 1216 printf(" openpic-reset(ctpr=%u)", 1217 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1218 1219 /* 1220 * fill in with an absolute branch to a routine that will panic. 1221 */ 1222 *(volatile int *)0 = 0x48000002 | (int) calltozero; 1223 1224 /* 1225 * Get the cache sizes. 1226 */ 1227 cpu_probe_cache(); 1228 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1229 ci->ci_ci.dcache_size >> 10, 1230 ci->ci_ci.dcache_line_size, 1231 ci->ci_ci.icache_size >> 10, 1232 ci->ci_ci.icache_line_size); 1233 1234 /* 1235 * Now find out how much memory is attached 1236 */ 1237 pmemsize = memprobe(endkernel); 1238 cpu->cpu_highmem = pmemsize; 1239 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1240 1241 /* 1242 * Now we need cleanout the TLB of stuff that we don't need. 1243 */ 1244 e500_tlb_init(endkernel, pmemsize); 1245 printf(" e500_tlbinit(%#lx,%zuMB)", 1246 endkernel, (size_t) (pmemsize >> 20)); 1247 1248 /* 1249 * 1250 */ 1251 printf(" hid0=%#lx/%#jx", hid0, (uintmax_t)mfspr(SPR_HID0)); 1252 printf(" hid1=%#jx", (uintmax_t)mfspr(SPR_HID1)); 1253 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1254 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1255 1256 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1257 1258 /* 1259 * Initialize the message buffer. 1260 */ 1261 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1262 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1263 1264 /* 1265 * Initialize exception vectors and interrupts 1266 */ 1267 exception_init(&e500_intrsw); 1268 1269 printf(" exception_init=%p", &e500_intrsw); 1270 1271 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1272 1273 uvm_md_init(); 1274 1275 /* 1276 * Initialize the pmap. 1277 */ 1278 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1279 1280 /* 1281 * Let's take all the indirect calls via our stubs and patch 1282 * them to be direct calls. 1283 */ 1284 cpu_fixup_stubs(); 1285 1286 /* 1287 * As a debug measure we can change the TLB entry that maps all of 1288 * memory to one that encompasses the 64KB with the kernel vectors. 1289 * All other pages will be soft faulted into the TLB as needed. 1290 */ 1291 e500_tlb_minimize(endkernel); 1292 1293 /* 1294 * Set some more MD helpers 1295 */ 1296 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1297 cpu_md_ops.md_device_register = e500_device_register; 1298 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1299 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1300 #if NGPIO > 0 1301 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1302 #endif 1303 1304 printf(" initppc done!\n"); 1305 1306 /* 1307 * Look for the Book-E modules in the right place. 1308 */ 1309 module_machine = module_machine_booke; 1310 } 1311 1312 #ifdef MPC8548 1313 static const char * const mpc8548cds_extirq_names[] = { 1314 [0] = "pci inta", 1315 [1] = "pci intb", 1316 [2] = "pci intc", 1317 [3] = "pci intd", 1318 [4] = "irq4", 1319 [5] = "gige phy", 1320 [6] = "atm phy", 1321 [7] = "cpld", 1322 [8] = "irq8", 1323 [9] = "nvram", 1324 [10] = "debug", 1325 [11] = "pci2 inta", 1326 }; 1327 #endif 1328 1329 #ifndef MPC8548 1330 static const char * const mpc85xx_extirq_names[] = { 1331 [0] = "extirq 0", 1332 [1] = "extirq 1", 1333 [2] = "extirq 2", 1334 [3] = "extirq 3", 1335 [4] = "extirq 4", 1336 [5] = "extirq 5", 1337 [6] = "extirq 6", 1338 [7] = "extirq 7", 1339 [8] = "extirq 8", 1340 [9] = "extirq 9", 1341 [10] = "extirq 10", 1342 [11] = "extirq 11", 1343 }; 1344 #endif 1345 1346 static void 1347 mpc85xx_extirq_setup(void) 1348 { 1349 #ifdef MPC8548 1350 const char * const * names = mpc8548cds_extirq_names; 1351 const size_t n = __arraycount(mpc8548cds_extirq_names); 1352 #else 1353 const char * const * names = mpc85xx_extirq_names; 1354 const size_t n = __arraycount(mpc85xx_extirq_names); 1355 #endif 1356 prop_array_t extirqs = prop_array_create_with_capacity(n); 1357 for (u_int i = 0; i < n; i++) { 1358 prop_string_t ps = prop_string_create_nocopy(names[i]); 1359 prop_array_set(extirqs, i, ps); 1360 prop_object_release(ps); 1361 } 1362 board_info_add_object("external-irqs", extirqs); 1363 prop_object_release(extirqs); 1364 } 1365 1366 static void 1367 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1368 { 1369 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1370 KASSERT(pci_intmap != NULL); 1371 prop_number_t mask = prop_number_create_unsigned(intmask); 1372 KASSERT(mask != NULL); 1373 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1374 prop_object_release(mask); 1375 prop_number_t pn_ist = prop_number_create_unsigned(ist); 1376 KASSERT(pn_ist != NULL); 1377 prop_number_t pn_intr = prop_number_create_unsigned(inta); 1378 KASSERT(pn_intr != NULL); 1379 prop_dictionary_t entry = prop_dictionary_create(); 1380 KASSERT(entry != NULL); 1381 prop_dictionary_set(entry, "interrupt", pn_intr); 1382 prop_dictionary_set(entry, "type", pn_ist); 1383 prop_dictionary_set(pci_intmap, "000000", entry); 1384 prop_object_release(pn_intr); 1385 prop_object_release(entry); 1386 va_list ap; 1387 va_start(ap, inta); 1388 u_int intrinc = __LOWEST_SET_BIT(intmask); 1389 for (u_int i = 0; i < intmask; i += intrinc) { 1390 char prop_name[12]; 1391 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1392 entry = prop_dictionary_create(); 1393 KASSERT(entry != NULL); 1394 pn_intr = prop_number_create_unsigned(va_arg(ap, u_int)); 1395 KASSERT(pn_intr != NULL); 1396 prop_dictionary_set(entry, "interrupt", pn_intr); 1397 prop_dictionary_set(entry, "type", pn_ist); 1398 prop_dictionary_set(pci_intmap, prop_name, entry); 1399 prop_object_release(pn_intr); 1400 prop_object_release(entry); 1401 } 1402 va_end(ap); 1403 prop_object_release(pn_ist); 1404 board_info_add_object(name, pci_intmap); 1405 prop_object_release(pci_intmap); 1406 } 1407 1408 void 1409 cpu_startup(void) 1410 { 1411 struct cpu_info * const ci = curcpu(); 1412 const uint16_t svr = getsvr(); 1413 1414 powersave = 0; /* we can do it but turn it on by default */ 1415 1416 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1417 1418 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1419 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1420 uint32_t e500_ratio = E500_RATIO_GET(v); 1421 1422 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1423 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1424 1425 ci->ci_khz = (cpu_freq + 500) / 1000; 1426 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1427 1428 board_info_add_number("my-id", svr); 1429 board_info_add_bool("pq3"); 1430 board_info_add_number("mem-size", pmemsize); 1431 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1432 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1433 uint32_t l2banks = l2siz >> 16; 1434 #ifdef MPC85555 1435 if (svr == (MPC8555v1 >> 16)) { 1436 l2siz >>= 1; 1437 l2banks >>= 1; 1438 } 1439 #endif 1440 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1441 if (boot_page & BPTR_EN) { 1442 bool found = false; 1443 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1444 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1445 * const bp = (void *)boot_page; 1446 bp <= dp; dp--) { 1447 if (*dp == boot_page) { 1448 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1449 spinup_table_addr = 1450 roundup2(spinup_table_addr, 32); 1451 board_info_add_number("mp-boot-page", 1452 boot_page); 1453 board_info_add_number("mp-spin-up-table", 1454 spinup_table_addr); 1455 printf("Found MP boot page @ %#"PRIxPADDR". " 1456 "Spin-up table @ %#"PRIxPTR"\n", 1457 boot_page, spinup_table_addr); 1458 found = true; 1459 break; 1460 } 1461 } 1462 if (!found) { 1463 printf("Found MP boot page @ %#"PRIxPADDR 1464 " with missing U-boot signature!\n", boot_page); 1465 board_info_add_number("mp-spin-up-table", 0); 1466 } 1467 } 1468 board_info_add_number("l2-cache-size", l2siz); 1469 board_info_add_number("l2-cache-line-size", 32); 1470 board_info_add_number("l2-cache-banks", l2banks); 1471 board_info_add_number("l2-cache-ways", 8); 1472 1473 board_info_add_number("processor-frequency", cpu_freq); 1474 board_info_add_number("bus-frequency", ccb_freq); 1475 board_info_add_number("pci-frequency", e500_sys_clk); 1476 board_info_add_number("timebase-frequency", ccb_freq / 8); 1477 1478 #ifdef CADMUS 1479 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1480 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1481 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1482 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1483 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1484 #else 1485 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1486 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1487 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1488 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1489 #endif 1490 1491 uint64_t macstnaddr = 1492 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1493 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1494 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1495 1496 #if NPCI > 0 && defined(PCI_MEMBASE) 1497 pcimem_ex = extent_create("pcimem", 1498 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1499 NULL, 0, EX_WAITOK); 1500 #endif 1501 #if NPCI > 0 && defined(PCI_IOBASE) 1502 pciio_ex = extent_create("pciio", 1503 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1504 NULL, 0, EX_WAITOK); 1505 #endif 1506 mpc85xx_extirq_setup(); 1507 /* 1508 * PCI-Express virtual wire interrupts on combined with 1509 * External IRQ0/1/2/3. 1510 */ 1511 switch (svr) { 1512 #if defined(MPC8548) 1513 case SVR_MPC8548v1 >> 16: 1514 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1515 IST_LEVEL, 0, 1, 2, 3); 1516 break; 1517 #endif 1518 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1519 || defined(P1025) || defined(P2020) || defined(P1023) 1520 case SVR_MPC8536v1 >> 16: 1521 case SVR_MPC8544v1 >> 16: 1522 case SVR_MPC8572v1 >> 16: 1523 case SVR_P1016v1 >> 16: 1524 case SVR_P1017v1 >> 16: 1525 case SVR_P1023v1 >> 16: 1526 case SVR_P2010v2 >> 16: 1527 case SVR_P2020v2 >> 16: 1528 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1529 8, 9, 10, 11); 1530 /* FALLTHROUGH */ 1531 case SVR_P1025v1 >> 16: 1532 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1533 4, 5, 6, 7); 1534 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1535 0, 1, 2, 3); 1536 break; 1537 #endif 1538 } 1539 switch (svr) { 1540 #if defined(MPC8536) 1541 case SVR_MPC8536v1 >> 16: 1542 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1543 1, 2, 3, 4); 1544 break; 1545 #endif 1546 #if defined(MPC8544) 1547 case SVR_MPC8544v1 >> 16: 1548 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1549 0, 1, 2, 3); 1550 break; 1551 #endif 1552 #if defined(MPC8548) 1553 case SVR_MPC8548v1 >> 16: 1554 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1555 0, 1, 2, 3); 1556 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1557 11, 1, 2, 3); 1558 break; 1559 #endif 1560 } 1561 } 1562
Indexes created Sat Sep 20 22:09:52 GMT 2025