1 /* $NetBSD: if_ixlvar.h,v 1.8 2022/03/16 05:26:37 yamaguchi Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_PCI_IF_IXLVAR_H_ 30 #define _DEV_PCI_IF_IXLVAR_H_ 31 32 enum i40e_filter_pctype { 33 /* Note: Values 0-28 are reserved for future use. 34 * Value 29, 30, 32 are not supported on XL710 and X710. 35 */ 36 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 37 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 38 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 39 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 40 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 41 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 42 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 43 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 44 /* Note: Values 37-38 are reserved for future use. 45 * Value 39, 40, 42 are not supported on XL710 and X710. 46 */ 47 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 48 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 49 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 50 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 51 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 52 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 53 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 54 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 55 /* Note: Value 47 is reserved for future use */ 56 I40E_FILTER_PCTYPE_FCOE_OX = 48, 57 I40E_FILTER_PCTYPE_FCOE_RX = 49, 58 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 59 /* Note: Values 51-62 are reserved for future use */ 60 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 61 }; 62 63 #define IXL_BIT_ULL(a) (1ULL << (a)) 64 #define IXL_RSS_HENA_DEFAULT_BASE \ 65 (IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 66 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 67 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 68 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 69 IXL_BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 70 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 71 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 72 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 73 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 74 IXL_BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 75 IXL_BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 76 #define IXL_RSS_HENA_DEFAULT_XL710 IXL_RSS_HENA_DEFAULT_BASE 77 #define IXL_RSS_HENA_DEFAULT_X722 (IXL_RSS_HENA_DEFAULT_XL710 | \ 78 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 79 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 80 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 81 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 82 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 83 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK)) 84 85 #define IXL_RSS_VSI_LUT_SIZE 64 86 #define IXL_RSS_KEY_SIZE_REG 13 87 #define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * sizeof(uint32_t)) 88 89 enum i40e_reset_type { 90 I40E_RESET_POR = 0, 91 I40E_RESET_CORER = 1, 92 I40E_RESET_GLOBR = 2, 93 I40E_RESET_EMPR = 3, 94 }; 95 96 struct ixl_aq_desc { 97 uint16_t iaq_flags; 98 #define IXL_AQ_DD (1U << 0) 99 #define IXL_AQ_CMP (1U << 1) 100 #define IXL_AQ_ERR (1U << 2) 101 #define IXL_AQ_VFE (1U << 3) 102 #define IXL_AQ_LB (1U << 9) 103 #define IXL_AQ_RD (1U << 10) 104 #define IXL_AQ_VFC (1U << 11) 105 #define IXL_AQ_BUF (1U << 12) 106 #define IXL_AQ_SI (1U << 13) 107 #define IXL_AQ_EI (1U << 14) 108 #define IXL_AQ_FE (1U << 15) 109 110 #define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 111 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 112 "\003ERR" "\002CMP" "\001DD" 113 114 uint16_t iaq_opcode; 115 116 uint16_t iaq_datalen; 117 uint16_t iaq_retval; 118 119 uint64_t iaq_cookie; 120 121 uint32_t iaq_param[4]; 122 /* iaq_data_hi iaq_param[2] */ 123 /* iaq_data_lo iaq_param[3] */ 124 } __packed __aligned(16); 125 126 /* aq commands */ 127 #define IXL_AQ_OP_GET_VERSION 0x0001 128 #define IXL_AQ_OP_DRIVER_VERSION 0x0002 129 #define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 130 #define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 131 #define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 132 #define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 133 #define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 134 #define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 135 #define IXL_AQ_OP_LIST_DEV_CAP 0x000b 136 #define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 137 #define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 138 #define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 139 #define IXL_AQ_OP_RX_CTL_REG_READ 0x0206 140 #define IXL_AQ_OP_RX_CTL_REG_WRITE 0x0207 141 #define IXL_AQ_OP_ADD_VSI 0x0210 142 #define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 143 #define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 144 #define IXL_AQ_OP_ADD_VEB 0x0230 145 #define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 146 #define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 147 #define IXL_AQ_OP_ADD_MACVLAN 0x0250 148 #define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 149 #define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 150 #define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 151 #define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 152 #define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 153 #define IXL_AQ_OP_PHY_RESTART_AN 0x0605 154 #define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 155 #define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 156 #define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 157 #define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 158 #define IXL_AQ_OP_NVM_READ 0x0701 159 #define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 160 #define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 161 #define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 162 #define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 163 #define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 164 #define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 165 #define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 166 #define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 167 #define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 168 #define IXL_AQ_OP_RSS_SET_KEY 0x0b02 169 #define IXL_AQ_OP_RSS_SET_LUT 0x0b03 170 #define IXL_AQ_OP_RSS_GET_KEY 0x0b04 171 #define IXL_AQ_OP_RSS_GET_LUT 0x0b05 172 173 static inline void 174 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 175 { 176 uint64_t val; 177 178 if (sizeof(addr) > 4) { 179 val = (intptr_t)addr; 180 iaq->iaq_param[2] = htole32(val >> 32); 181 } else { 182 iaq->iaq_param[2] = htole32(0); 183 } 184 185 iaq->iaq_param[3] = htole32(addr); 186 } 187 188 static inline bool 189 ixl_aq_has_dva(struct ixl_aq_desc *iaq) 190 { 191 uint64_t val; 192 193 if (sizeof(bus_addr_t) > 4) { 194 val = le32toh(iaq->iaq_param[2]); 195 val = val << 32; 196 } else { 197 val = 0; 198 } 199 val |= htole32(iaq->iaq_param[3]); 200 201 return !(val == 0); 202 } 203 204 struct ixl_aq_mac_addresses { 205 uint8_t pf_lan[ETHER_ADDR_LEN]; 206 uint8_t pf_san[ETHER_ADDR_LEN]; 207 uint8_t port[ETHER_ADDR_LEN]; 208 uint8_t pf_wol[ETHER_ADDR_LEN]; 209 } __packed; 210 211 #define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 212 #define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 213 #define IXL_AQ_MAC_PORT_VALID (1U << 6) 214 #define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 215 216 struct ixl_aq_capability { 217 uint16_t cap_id; 218 #define IXL_AQ_CAP_SWITCH_MODE 0x0001 219 #define IXL_AQ_CAP_MNG_MODE 0x0002 220 #define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 221 #define IXL_AQ_CAP_OS2BMC_CAP 0x0004 222 #define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 223 #define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 224 #define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 225 #define IXL_AQ_CAP_SRIOV 0x0012 226 #define IXL_AQ_CAP_VF 0x0013 227 #define IXL_AQ_CAP_VMDQ 0x0014 228 #define IXL_AQ_CAP_8021QBG 0x0015 229 #define IXL_AQ_CAP_8021QBR 0x0016 230 #define IXL_AQ_CAP_VSI 0x0017 231 #define IXL_AQ_CAP_DCB 0x0018 232 #define IXL_AQ_CAP_FCOE 0x0021 233 #define IXL_AQ_CAP_ISCSI 0x0022 234 #define IXL_AQ_CAP_RSS 0x0040 235 #define IXL_AQ_CAP_RXQ 0x0041 236 #define IXL_AQ_CAP_TXQ 0x0042 237 #define IXL_AQ_CAP_MSIX 0x0043 238 #define IXL_AQ_CAP_VF_MSIX 0x0044 239 #define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 240 #define IXL_AQ_CAP_1588 0x0046 241 #define IXL_AQ_CAP_IWARP 0x0051 242 #define IXL_AQ_CAP_LED 0x0061 243 #define IXL_AQ_CAP_SDP 0x0062 244 #define IXL_AQ_CAP_MDIO 0x0063 245 #define IXL_AQ_CAP_WSR_PROT 0x0064 246 #define IXL_AQ_CAP_NVM_MGMT 0x0080 247 #define IXL_AQ_CAP_FLEX10 0x00F1 248 #define IXL_AQ_CAP_CEM 0x00F2 249 uint8_t major_rev; 250 uint8_t minor_rev; 251 uint32_t number; 252 uint32_t logical_id; 253 uint32_t phys_id; 254 uint8_t _reserved[16]; 255 } __packed __aligned(4); 256 257 #define IXL_LLDP_SHUTDOWN 0x1 258 259 struct ixl_aq_switch_config { 260 uint16_t num_reported; 261 uint16_t num_total; 262 uint8_t _reserved[12]; 263 } __packed __aligned(4); 264 265 struct ixl_aq_switch_config_element { 266 uint8_t type; 267 #define IXL_AQ_SW_ELEM_TYPE_MAC 1 268 #define IXL_AQ_SW_ELEM_TYPE_PF 2 269 #define IXL_AQ_SW_ELEM_TYPE_VF 3 270 #define IXL_AQ_SW_ELEM_TYPE_EMP 4 271 #define IXL_AQ_SW_ELEM_TYPE_BMC 5 272 #define IXL_AQ_SW_ELEM_TYPE_PV 16 273 #define IXL_AQ_SW_ELEM_TYPE_VEB 17 274 #define IXL_AQ_SW_ELEM_TYPE_PA 18 275 #define IXL_AQ_SW_ELEM_TYPE_VSI 19 276 uint8_t revision; 277 #define IXL_AQ_SW_ELEM_REV_1 1 278 uint16_t seid; 279 280 uint16_t uplink_seid; 281 uint16_t downlink_seid; 282 283 uint8_t _reserved[3]; 284 uint8_t connection_type; 285 #define IXL_AQ_CONN_TYPE_REGULAR 0x1 286 #define IXL_AQ_CONN_TYPE_DEFAULT 0x2 287 #define IXL_AQ_CONN_TYPE_CASCADED 0x3 288 289 uint16_t scheduler_id; 290 uint16_t element_info; 291 } __packed __aligned(4); 292 293 #define IXL_PHY_TYPE_SGMII 0x00 294 #define IXL_PHY_TYPE_1000BASE_KX 0x01 295 #define IXL_PHY_TYPE_10GBASE_KX4 0x02 296 #define IXL_PHY_TYPE_10GBASE_KR 0x03 297 #define IXL_PHY_TYPE_40GBASE_KR4 0x04 298 #define IXL_PHY_TYPE_XAUI 0x05 299 #define IXL_PHY_TYPE_XFI 0x06 300 #define IXL_PHY_TYPE_SFI 0x07 301 #define IXL_PHY_TYPE_XLAUI 0x08 302 #define IXL_PHY_TYPE_XLPPI 0x09 303 #define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 304 #define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 305 #define IXL_PHY_TYPE_10GBASE_AOC 0x0c 306 #define IXL_PHY_TYPE_40GBASE_AOC 0x0d 307 #define IXL_PHY_TYPE_100BASE_TX 0x11 308 #define IXL_PHY_TYPE_1000BASE_T 0x12 309 #define IXL_PHY_TYPE_10GBASE_T 0x13 310 #define IXL_PHY_TYPE_10GBASE_SR 0x14 311 #define IXL_PHY_TYPE_10GBASE_LR 0x15 312 #define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 313 #define IXL_PHY_TYPE_10GBASE_CR1 0x17 314 #define IXL_PHY_TYPE_40GBASE_CR4 0x18 315 #define IXL_PHY_TYPE_40GBASE_SR4 0x19 316 #define IXL_PHY_TYPE_40GBASE_LR4 0x1a 317 #define IXL_PHY_TYPE_1000BASE_SX 0x1b 318 #define IXL_PHY_TYPE_1000BASE_LX 0x1c 319 #define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 320 #define IXL_PHY_TYPE_20GBASE_KR2 0x1e 321 322 #define IXL_PHY_TYPE_25GBASE_KR 0x1f 323 #define IXL_PHY_TYPE_25GBASE_CR 0x20 324 #define IXL_PHY_TYPE_25GBASE_SR 0x21 325 #define IXL_PHY_TYPE_25GBASE_LR 0x22 326 #define IXL_PHY_TYPE_25GBASE_AOC 0x23 327 #define IXL_PHY_TYPE_25GBASE_ACC 0x24 328 329 #define IXL_PHY_TYPE_2500BASE_T_1 0x26 330 #define IXL_PHY_TYPE_5000BASE_T_1 0x27 331 332 #define IXL_PHY_TYPE_2500BASE_T_2 0x30 333 #define IXL_PHY_TYPE_5000BASE_T_2 0x31 334 335 #define IXL_PHY_LINK_SPEED_2500MB (1 << 0) 336 #define IXL_PHY_LINK_SPEED_100MB (1 << 1) 337 #define IXL_PHY_LINK_SPEED_1000MB (1 << 2) 338 #define IXL_PHY_LINK_SPEED_10GB (1 << 3) 339 #define IXL_PHY_LINK_SPEED_40GB (1 << 4) 340 #define IXL_PHY_LINK_SPEED_20GB (1 << 5) 341 #define IXL_PHY_LINK_SPEED_25GB (1 << 6) 342 #define IXL_PHY_LINK_SPEED_5000MB (1 << 7) 343 344 #define IXL_PHY_ABILITY_PAUSE_TX (1 << 0) 345 #define IXL_PHY_ABILITY_PAUSE_RX (1 << 1) 346 #define IXL_PHY_ABILITY_LOWPOW (1 << 2) 347 #define IXL_PHY_ABILITY_LINKUP (1 << 3) 348 #define IXL_PHY_ABILITY_AUTONEGO (1 << 4) 349 #define IXL_PHY_ABILITY_MODQUAL (1 << 5) 350 351 struct ixl_aq_module_desc { 352 uint8_t oui[3]; 353 uint8_t _reserved1; 354 uint8_t part_number[16]; 355 uint8_t revision[4]; 356 uint8_t _reserved2[8]; 357 } __packed __aligned(4); 358 359 struct ixl_aq_phy_abilities { 360 uint32_t phy_type; 361 362 uint8_t link_speed; 363 uint8_t abilities; 364 uint16_t eee_capability; 365 366 uint32_t eeer_val; 367 368 uint8_t d3_lpan; 369 uint8_t phy_type_ext; 370 #define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 371 #define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 372 #define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 373 #define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 374 #define IXL_AQ_PHY_TYPE_EXT_25G_AOC 0x10 375 #define IXL_AQ_PHY_TYPE_EXT_25G_ACC 0x20 376 #define IXL_AQ_PHY_TYPE_EXT_2500_T 0x40 377 #define IXL_AQ_PHY_TYPE_EXT_5000_T 0x80 378 uint8_t fec_cfg_curr_mod_ext_info; 379 #define IXL_AQ_ENABLE_FEC_KR 0x01 380 #define IXL_AQ_ENABLE_FEC_RS 0x02 381 #define IXL_AQ_REQUEST_FEC_KR 0x04 382 #define IXL_AQ_REQUEST_FEC_RS 0x08 383 #define IXL_AQ_ENABLE_FEC_AUTO 0x10 384 #define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 385 #define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 386 uint8_t ext_comp_code; 387 388 uint8_t phy_id[4]; 389 390 uint8_t module_type[3]; 391 #define IXL_SFF8024_ID_SFP 0x03 392 #define IXL_SFF8024_ID_QSFP 0x0c 393 #define IXL_SFF8024_ID_QSFP_PLUS 0x0d 394 #define IXL_SFF8024_ID_QSFP28 0x11 395 uint8_t qualified_module_count; 396 #define IXL_AQ_PHY_MAX_QMS 16 397 struct ixl_aq_module_desc 398 qualified_module[IXL_AQ_PHY_MAX_QMS]; 399 } __packed __aligned(4); 400 401 struct ixl_aq_phy_param { 402 uint32_t phy_types; 403 uint8_t link_speed; 404 uint8_t abilities; 405 #define IXL_AQ_PHY_ABILITY_AUTO_LINK (1 << 5) 406 uint16_t eee_capability; 407 uint32_t eeer_val; 408 uint8_t d3_lpan; 409 uint8_t phy_type_ext; 410 uint8_t fec_cfg; 411 uint8_t config; 412 } __packed __aligned(4); 413 414 struct ixl_aq_link_param { 415 uint8_t notify; 416 #define IXL_AQ_LINK_NOTIFY 0x03 417 uint8_t _reserved1; 418 uint8_t phy; 419 uint8_t speed; 420 uint8_t status; 421 uint8_t _reserved2[11]; 422 } __packed __aligned(4); 423 424 struct ixl_aq_vsi_param { 425 uint16_t uplink_seid; 426 uint8_t connect_type; 427 #define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 428 #define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 429 #define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 430 uint8_t _reserved1; 431 432 uint8_t vf_id; 433 uint8_t _reserved2; 434 uint16_t vsi_flags; 435 #define IXL_AQ_VSI_TYPE_SHIFT 0x0 436 #define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 437 #define IXL_AQ_VSI_TYPE_VF 0x0 438 #define IXL_AQ_VSI_TYPE_VMDQ2 0x1 439 #define IXL_AQ_VSI_TYPE_PF 0x2 440 #define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 441 #define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 442 443 uint32_t addr_hi; 444 uint32_t addr_lo; 445 } __packed __aligned(16); 446 447 struct ixl_aq_add_macvlan { 448 uint16_t num_addrs; 449 uint16_t seid0; 450 uint16_t seid1; 451 uint16_t seid2; 452 uint32_t addr_hi; 453 uint32_t addr_lo; 454 } __packed __aligned(16); 455 456 struct ixl_aq_add_macvlan_elem { 457 uint8_t macaddr[6]; 458 uint16_t vlan; 459 uint16_t flags; 460 #define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 461 #define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 462 uint16_t queue; 463 uint32_t _reserved; 464 } __packed __aligned(16); 465 466 struct ixl_aq_remove_macvlan { 467 uint16_t num_addrs; 468 uint16_t seid0; 469 uint16_t seid1; 470 uint16_t seid2; 471 uint32_t addr_hi; 472 uint32_t addr_lo; 473 } __packed __aligned(16); 474 475 struct ixl_aq_remove_macvlan_elem { 476 uint8_t macaddr[6]; 477 uint16_t vlan; 478 uint8_t flags; 479 #define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 480 #define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 481 uint8_t _reserved[7]; 482 } __packed __aligned(16); 483 484 struct ixl_aq_vsi_reply { 485 uint16_t seid; 486 uint16_t vsi_number; 487 488 uint16_t vsis_used; 489 uint16_t vsis_free; 490 491 uint32_t addr_hi; 492 uint32_t addr_lo; 493 } __packed __aligned(16); 494 495 struct ixl_aq_vsi_data { 496 /* first 96 byte are written by SW */ 497 uint16_t valid_sections; 498 #define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 499 #define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 500 #define IXL_AQ_VSI_VALID_VLAN (1 << 2) 501 #define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 502 #define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 503 #define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 504 #define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 505 #define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 506 #define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 507 #define IXL_AQ_VSI_VALID_SCHED (1 << 9) 508 /* switch section */ 509 uint16_t switch_id; 510 #define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 511 #define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 512 #define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 513 #define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 514 515 uint8_t _reserved1[2]; 516 /* security section */ 517 uint8_t sec_flags; 518 #define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 519 #define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 520 #define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 521 uint8_t _reserved2; 522 523 /* vlan section */ 524 uint16_t pvid; 525 uint16_t fcoe_pvid; 526 527 uint8_t port_vlan_flags; 528 #define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 529 #define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 530 #define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 531 #define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 532 #define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 533 #define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 534 #define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 535 #define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 536 #define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 537 #define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 538 #define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 539 #define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 540 uint8_t _reserved3[3]; 541 542 /* ingress egress up section */ 543 uint32_t ingress_table; 544 #define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 545 #define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 546 uint32_t egress_table; 547 548 /* cascaded pv section */ 549 uint16_t cas_pv_tag; 550 uint8_t cas_pv_flags; 551 #define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 552 #define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 553 #define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 554 #define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 555 #define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 556 #define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 557 #define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 558 #define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 559 (1 << 6) 560 uint8_t _reserved4; 561 562 /* queue mapping section */ 563 uint16_t mapping_flags; 564 #define IXL_AQ_VSI_QUE_MAP_MASK 0x1 565 #define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 566 #define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 567 uint16_t queue_mapping[16]; 568 #define IXL_AQ_VSI_QUEUE_SHIFT 0x0 569 #define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 570 uint16_t tc_mapping[8]; 571 #define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 572 #define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 573 #define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 574 #define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 575 576 /* queueing option section */ 577 uint8_t queueing_opt_flags; 578 #define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 579 #define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 580 #define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 581 #define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 582 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 583 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 584 uint8_t _reserved5[3]; 585 586 /* scheduler section */ 587 uint8_t up_enable_bits; 588 uint8_t _reserved6; 589 590 /* outer up section */ 591 uint32_t outer_up_table; /* same as ingress/egress tables */ 592 uint8_t _reserved7[8]; 593 594 /* last 32 bytes are written by FW */ 595 uint16_t qs_handle[8]; 596 #define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 597 uint16_t stat_counter_idx; 598 uint16_t sched_id; 599 600 uint8_t _reserved8[12]; 601 } __packed __aligned(8); 602 603 CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 604 605 struct ixl_aq_vsi_promisc_param { 606 uint16_t flags; 607 uint16_t valid_flags; 608 #define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 609 #define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 610 #define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 611 #define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 612 #define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 613 #define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 614 615 uint16_t seid; 616 #define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 617 uint16_t vlan; 618 #define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 619 uint32_t reserved[2]; 620 } __packed __aligned(8); 621 622 struct ixl_aq_veb_param { 623 uint16_t uplink_seid; 624 uint16_t downlink_seid; 625 uint16_t veb_flags; 626 #define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 627 #define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 628 #define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 629 #define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 630 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 631 #define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 632 #define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 633 #define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 634 uint8_t enable_tcs; 635 uint8_t _reserved[9]; 636 } __packed __aligned(16); 637 638 struct ixl_aq_veb_reply { 639 uint16_t _reserved1; 640 uint16_t _reserved2; 641 uint16_t _reserved3; 642 uint16_t switch_seid; 643 uint16_t veb_seid; 644 #define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 645 #define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 646 #define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 647 #define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 648 uint16_t statistic_index; 649 uint16_t vebs_used; 650 uint16_t vebs_free; 651 } __packed __aligned(16); 652 653 /* GET PHY ABILITIES param[0] */ 654 #define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 655 #define IXL_AQ_PHY_REPORT_INIT (1 << 1) 656 657 struct ixl_aq_phy_reg_access { 658 uint8_t phy_iface; 659 #define IXL_AQ_PHY_IF_INTERNAL 0 660 #define IXL_AQ_PHY_IF_EXTERNAL 1 661 #define IXL_AQ_PHY_IF_MODULE 2 662 uint8_t dev_addr; 663 uint16_t recall; 664 #define IXL_AQ_PHY_QSFP_DEV_ADDR 0 665 #define IXL_AQ_PHY_QSFP_LAST 1 666 uint32_t reg; 667 uint32_t val; 668 uint32_t _reserved2; 669 } __packed __aligned(16); 670 671 /* RESTART_AN param[0] */ 672 #define IXL_AQ_PHY_RESTART_AN (1 << 1) 673 #define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 674 675 struct ixl_aq_link_status { /* this occupies the iaq_param space */ 676 uint16_t command_flags; /* only field set on command */ 677 #define IXL_AQ_LSE_MASK 0x3 678 #define IXL_AQ_LSE_NOP 0x0 679 #define IXL_AQ_LSE_DISABLE 0x2 680 #define IXL_AQ_LSE_ENABLE 0x3 681 #define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 682 uint8_t phy_type; 683 uint8_t link_speed; 684 #define IXL_AQ_LINK_SPEED_2500MB (1 << 0) 685 #define IXL_AQ_LINK_SPEED_100MB (1 << 1) 686 #define IXL_AQ_LINK_SPEED_1000MB (1 << 2) 687 #define IXL_AQ_LINK_SPEED_10GB (1 << 3) 688 #define IXL_AQ_LINK_SPEED_40GB (1 << 4) 689 #define IXL_AQ_LINK_SPEED_25GB (1 << 6) 690 #define IXL_AQ_LINK_SPEED_5000MB (1 << 7) 691 uint8_t link_info; 692 #define IXL_AQ_LINK_UP_FUNCTION 0x01 693 #define IXL_AQ_LINK_FAULT 0x02 694 #define IXL_AQ_LINK_FAULT_TX 0x04 695 #define IXL_AQ_LINK_FAULT_RX 0x08 696 #define IXL_AQ_LINK_FAULT_REMOTE 0x10 697 #define IXL_AQ_LINK_UP_PORT 0x20 698 #define IXL_AQ_MEDIA_AVAILABLE 0x40 699 #define IXL_AQ_SIGNAL_DETECT 0x80 700 uint8_t an_info; 701 #define IXL_AQ_AN_COMPLETED 0x01 702 #define IXL_AQ_LP_AN_ABILITY 0x02 703 #define IXL_AQ_PD_FAULT 0x04 704 #define IXL_AQ_FEC_EN 0x08 705 #define IXL_AQ_PHY_LOW_POWER 0x10 706 #define IXL_AQ_LINK_PAUSE_TX 0x20 707 #define IXL_AQ_LINK_PAUSE_RX 0x40 708 #define IXL_AQ_QUALIFIED_MODULE 0x80 709 710 uint8_t ext_info; 711 #define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 712 #define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 713 #define IXL_AQ_LINK_TX_SHIFT 0x02 714 #define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 715 #define IXL_AQ_LINK_TX_ACTIVE 0x00 716 #define IXL_AQ_LINK_TX_DRAINED 0x01 717 #define IXL_AQ_LINK_TX_FLUSHED 0x03 718 #define IXL_AQ_LINK_FORCED_40G 0x10 719 /* 25G Error Codes */ 720 #define IXL_AQ_25G_NO_ERR 0X00 721 #define IXL_AQ_25G_NOT_PRESENT 0X01 722 #define IXL_AQ_25G_NVM_CRC_ERR 0X02 723 #define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 724 #define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 725 #define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 726 uint8_t loopback; 727 uint16_t max_frame_size; 728 729 uint8_t config; 730 #define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 731 #define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 732 #define IXL_AQ_CONFIG_CRC_ENA 0x04 733 #define IXL_AQ_CONFIG_PACING_MASK 0x78 734 uint8_t power_desc; 735 #define IXL_AQ_LINK_POWER_CLASS_1 0x00 736 #define IXL_AQ_LINK_POWER_CLASS_2 0x01 737 #define IXL_AQ_LINK_POWER_CLASS_3 0x02 738 #define IXL_AQ_LINK_POWER_CLASS_4 0x03 739 #define IXL_AQ_PWR_CLASS_MASK 0x03 740 741 uint8_t reserved[4]; 742 } __packed __aligned(4); 743 744 /* event mask command flags for param[2] */ 745 #define IXL_AQ_PHY_EV_MASK 0x3ff 746 #define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 747 #define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 748 #define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 749 #define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 750 #define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 751 #define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 752 #define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 753 #define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 754 #define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 755 756 struct ixl_aq_req_resource_param { 757 uint16_t resource_id; 758 #define IXL_AQ_RESOURCE_ID_NVM 0x0001 759 #define IXL_AQ_RESOURCE_ID_SDP 0x0002 760 761 uint16_t access_type; 762 #define IXL_AQ_RESOURCE_ACCES_READ 0x01 763 #define IXL_AQ_RESOURCE_ACCES_WRITE 0x02 764 765 uint16_t timeout; 766 uint32_t resource_num; 767 uint32_t reserved; 768 } __packed __aligned(8); 769 770 struct ixl_aq_rel_resource_param { 771 uint16_t resource_id; 772 /* defined in ixl_aq_req_resource_param */ 773 uint16_t _reserved1[3]; 774 uint32_t resource_num; 775 uint32_t _reserved2; 776 } __packed __aligned(8); 777 778 struct ixl_aq_nvm_param { 779 uint8_t command_flags; 780 #define IXL_AQ_NVM_LAST_CMD (1 << 0) 781 #define IXL_AQ_NVM_FLASH_ONLY (1 << 7) 782 uint8_t module_pointer; 783 uint16_t length; 784 uint32_t offset; 785 uint32_t addr_hi; 786 uint32_t addr_lo; 787 } __packed __aligned(4); 788 789 struct ixl_aq_rss_key_param { 790 uint16_t vsi_id; 791 #define IXL_AQ_RSSKEY_VSI_VALID (0x01 << 15) 792 #define IXL_AQ_RSSKEY_VSI_ID_SHIFT 0 793 #define IXL_AQ_RSSKEY_VSI_ID_MASK (0x3FF << IXL_RSSKEY_VSI_ID_SHIFT) 794 795 uint8_t reserved[6]; 796 uint32_t addr_hi; 797 uint32_t addr_lo; 798 } __packed __aligned(8); 799 800 struct ixl_aq_rss_key_data { 801 uint8_t standard_rss_key[0x28]; 802 uint8_t extended_hash_key[0xc]; 803 } __packed __aligned(8); 804 805 struct ixl_aq_rss_lut_param { 806 uint16_t vsi_id; 807 #define IXL_AQ_RSSLUT_VSI_VALID (0x01 << 15) 808 #define IXL_AQ_RSSLUT_VSI_ID_SHIFT 0 809 #define IXL_AQ_RSSLUT_VSI_ID_MASK (0x03FF << IXL_AQ_RSSLUT_VSI_ID_SHIFT) 810 811 uint16_t flags; 812 #define IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT 0 813 #define IXL_AQ_RSSLUT_TABLE_TYPE_MASK (0x01 << IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT) 814 #define IXL_AQ_RSSLUT_TABLE_TYPE_VSI 0 815 #define IXL_AQ_RSSLUT_TABLE_TYPE_PF 1 816 uint8_t reserved[4]; 817 uint32_t addr_hi; 818 uint32_t addr_lo; 819 } __packed __aligned(8); 820 821 /* aq response codes */ 822 #define IXL_AQ_RC_OK 0 /* success */ 823 #define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 824 #define IXL_AQ_RC_ENOENT 2 /* No such element */ 825 #define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 826 #define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 827 #define IXL_AQ_RC_EIO 5 /* I/O error */ 828 #define IXL_AQ_RC_ENXIO 6 /* No such resource */ 829 #define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 830 #define IXL_AQ_RC_EAGAIN 8 /* Try again */ 831 #define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 832 #define IXL_AQ_RC_EACCES 10 /* Permission denied */ 833 #define IXL_AQ_RC_EFAULT 11 /* Bad address */ 834 #define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 835 #define IXL_AQ_RC_EEXIST 13 /* object already exists */ 836 #define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 837 #define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 838 #define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 839 #define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 840 #define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 841 #define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 842 #define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 843 #define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 844 #define IXL_AQ_RC_EFBIG 22 /* file too large */ 845 846 struct ixl_tx_desc { 847 uint64_t addr; 848 uint64_t cmd; 849 #define IXL_TX_DESC_DTYPE_SHIFT 0 850 #define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 851 #define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 852 #define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 853 #define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 854 #define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 855 #define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 856 #define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 857 #define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 858 #define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 859 #define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 860 #define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 861 862 #define IXL_TX_DESC_CMD_SHIFT 4 863 #define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 864 #define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 865 #define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 866 #define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 867 #define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 868 #define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 869 #define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 870 #define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 871 #define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 872 #define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 873 #define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 874 #define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 875 #define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 876 #define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 877 #define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 878 #define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 879 #define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 880 881 #define IXL_TX_DESC_MACLEN_SHIFT 16 882 #define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 883 #define IXL_TX_DESC_IPLEN_SHIFT 23 884 #define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 885 #define IXL_TX_DESC_L4LEN_SHIFT 30 886 #define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 887 #define IXL_TX_DESC_FCLEN_SHIFT 30 888 #define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 889 890 #define IXL_TX_DESC_BSIZE_SHIFT 34 891 #define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 892 #define IXL_TX_DESC_BSIZE_MASK \ 893 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 894 #define IXL_TX_DESC_L2TAG1_SHIFT 48 895 } __packed __aligned(16); 896 897 struct ixl_rx_rd_desc_16 { 898 uint64_t paddr; /* packet addr */ 899 uint64_t haddr; /* header addr */ 900 } __packed __aligned(16); 901 902 struct ixl_rx_rd_desc_32 { 903 uint64_t paddr; /* packet addr */ 904 uint64_t haddr; /* header addr */ 905 uint64_t _reserved1; 906 uint64_t _reserved2; 907 } __packed __aligned(16); 908 909 struct ixl_rx_wb_desc_16 { 910 uint64_t qword0; 911 #define IXL_RX_DESC_L2TAG1_SHIFT 16 912 #define IXL_RX_DESC_L2TAG1_MASK (0xffffULL << IXL_RX_DESC_L2TAG1_SHIFT) 913 uint64_t qword1; 914 #define IXL_RX_DESC_DD (1 << 0) 915 #define IXL_RX_DESC_EOP (1 << 1) 916 #define IXL_RX_DESC_L2TAG1P (1 << 2) 917 #define IXL_RX_DESC_L3L4P (1 << 3) 918 #define IXL_RX_DESC_CRCP (1 << 4) 919 #define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 920 #define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 921 #define IXL_RX_DESC_UMB_SHIFT 9 922 #define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 923 #define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 924 #define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 925 #define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 926 #define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 927 #define IXL_RX_DESC_FLM (1 << 11) 928 #define IXL_RX_DESC_FLTSTAT_SHIFT 12 929 #define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 930 #define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 931 #define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 932 #define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 933 #define IXL_RX_DESC_LPBK (1 << 14) 934 #define IXL_RX_DESC_IPV6EXTADD (1 << 15) 935 #define IXL_RX_DESC_INT_UDP_0 (1 << 18) 936 937 #define IXL_RX_DESC_RXE (1 << 19) 938 #define IXL_RX_DESC_HBO (1 << 21) 939 #define IXL_RX_DESC_IPE (1 << 22) 940 #define IXL_RX_DESC_L4E (1 << 23) 941 #define IXL_RX_DESC_EIPE (1 << 24) 942 #define IXL_RX_DESC_OVERSIZE (1 << 25) 943 944 #define IXL_RX_DESC_PTYPE_SHIFT 30 945 #define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 946 947 #define IXL_RX_DESC_PLEN_SHIFT 38 948 #define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 949 #define IXL_RX_DESC_HLEN_SHIFT 42 950 #define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 951 } __packed __aligned(16); 952 953 enum ixl_rx_desc_ptype { 954 IXL_RX_DESC_PTYPE_IPV4FRAG = 22, 955 IXL_RX_DESC_PTYPE_IPV4 = 23, 956 IXL_RX_DESC_PTYPE_UDPV4 = 24, 957 IXL_RX_DESC_PTYPE_TCPV4 = 26, 958 IXL_RX_DESC_PTYPE_SCTPV4 = 27, 959 IXL_RX_DESC_PTYPE_ICMPV4 = 28, 960 961 IXL_RX_DESC_PTYPE_IPV6FRAG = 88, 962 IXL_RX_DESC_PTYPE_IPV6 = 89, 963 IXL_RX_DESC_PTYPE_UDPV6 = 90, 964 IXL_RX_DESC_PTYPE_TCPV6 = 92, 965 IXL_RX_DESC_PTYPE_SCTPV6 = 93, 966 IXL_RX_DESC_PTYPE_ICMPV6 = 94, 967 }; 968 969 struct ixl_rx_wb_desc_32 { 970 uint64_t qword0; 971 uint64_t qword1; 972 uint64_t qword2; 973 uint64_t qword3; 974 } __packed __aligned(16); 975 976 enum i40e_mac_type { 977 I40E_MAC_XL710, 978 I40E_MAC_X722, 979 I40E_MAC_X722_VF, 980 I40E_MAC_VF, 981 I40E_MAC_GENERIC 982 }; 983 984 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 985 #define I40E_SR_BOOT_CONFIG_PTR 0x17 986 #define I40E_NVM_OEM_VER_OFF 0x83 987 #define I40E_SR_NVM_EETRACK_LO 0x2D 988 #define I40E_SR_NVM_EETRACK_HI 0x2E 989 990 #define IXL_NVM_VERSION_LO_SHIFT 0 991 #define IXL_NVM_VERSION_LO_MASK (0xffUL << IXL_NVM_VERSION_LO_SHIFT) 992 #define IXL_NVM_VERSION_HI_SHIFT 12 993 #define IXL_NVM_VERSION_HI_MASK (0xfUL << IXL_NVM_VERSION_HI_SHIFT) 994 #define IXL_NVM_OEMVERSION_SHIFT 24 995 #define IXL_NVM_OEMVERSION_MASK (0xffUL << IXL_NVM_OEMVERSION_SHIFT) 996 #define IXL_NVM_OEMBUILD_SHIFT 8 997 #define IXL_NVM_OEMBUILD_MASK (0xffffUL << IXL_NVM_OEMBUILD_SHIFT) 998 #define IXL_NVM_OEMPATCH_SHIFT 0 999 #define IXL_NVM_OEMPATCH_MASK (0xff << IXL_NVM_OEMPATCH_SHIFT) 1000 1001 struct ixl_aq_buf { 1002 SIMPLEQ_ENTRY(ixl_aq_buf) 1003 aqb_entry; 1004 void *aqb_data; 1005 bus_dmamap_t aqb_map; 1006 bus_dma_segment_t aqb_seg; 1007 size_t aqb_size; 1008 int aqb_nsegs; 1009 }; 1010 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 1011 1012 #define IXL_AQB_MAP(_aqb) ((_aqb)->aqb_map) 1013 #define IXL_AQB_DVA(_aqb) ((_aqb)->aqb_map->dm_segs[0].ds_addr) 1014 #define IXL_AQB_KVA(_aqb) ((void *)(_aqb)->aqb_data) 1015 #define IXL_AQB_LEN(_aqb) ((_aqb)->aqb_size) 1016 1017 static inline unsigned int 1018 ixl_rxr_unrefreshed(unsigned int prod, unsigned int cons, unsigned int ndescs) 1019 { 1020 unsigned int num; 1021 1022 if (prod < cons) 1023 num = cons - prod; 1024 else 1025 num = (ndescs - prod) + cons; 1026 1027 if (__predict_true(num > 0)) { 1028 /* device cannot receive packets if all descripter is filled */ 1029 num -= 1; 1030 } 1031 1032 return num; 1033 } 1034 1035 struct ixl_dmamem { 1036 bus_dmamap_t ixm_map; 1037 bus_dma_segment_t ixm_seg; 1038 int ixm_nsegs; 1039 size_t ixm_size; 1040 void *ixm_kva; 1041 }; 1042 1043 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 1044 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 1045 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 1046 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 1047 1048 static inline uint32_t 1049 ixl_dmamem_hi(struct ixl_dmamem *ixm) 1050 { 1051 uint32_t retval; 1052 uint64_t val; 1053 1054 if (sizeof(IXL_DMA_DVA(ixm)) > 4) { 1055 val = (intptr_t)IXL_DMA_DVA(ixm); 1056 retval = val >> 32; 1057 } else { 1058 retval = 0; 1059 } 1060 1061 return retval; 1062 } 1063 1064 static inline uint32_t 1065 ixl_dmamem_lo(struct ixl_dmamem *ixm) 1066 { 1067 1068 return (uint32_t)IXL_DMA_DVA(ixm); 1069 } 1070 1071 struct i40e_eth_stats { 1072 uint64_t rx_bytes; 1073 uint64_t rx_unicast; 1074 uint64_t rx_multicast; 1075 uint64_t rx_broadcast; 1076 uint64_t rx_discards; 1077 uint64_t rx_unknown_protocol; 1078 1079 uint64_t tx_bytes; 1080 uint64_t tx_unicast; 1081 uint64_t tx_multicast; 1082 uint64_t tx_broadcast; 1083 uint64_t tx_discards; 1084 uint64_t tx_errors; 1085 } __packed; 1086 #endif 1087
Indexes created Sat Sep 20 22:09:52 GMT 2025