| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 324 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local in function:context_timing_trace
328 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
331 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
336 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i] local in function:context_timing_trace
[all...] |
| amdgpu_dc_surface.c | 161 struct pipe_ctx *pipe_ctx = local in function:dc_plane_get_status
162 &dc->current_state->res_ctx.pipe_ctx[i];
164 if (pipe_ctx->plane_state != plane_state)
167 pipe_ctx->plane_state->status.is_flip_pending = false;
173 struct pipe_ctx *pipe_ctx = local in function:dc_plane_get_status
174 &dc->current_state->res_ctx.pipe_ctx[i];
176 if (pipe_ctx->plane_state != plane_state)
179 dc->hwss.update_pending_status(pipe_ctx);
[all...] |
| amdgpu_dc_stream.c | 239 static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
244 struct dc_stream_state *stream = pipe_ctx->stream;
250 vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
278 struct pipe_ctx *pipe_to_program = NULL;
299 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local in function:dc_stream_set_cursor_attributes
301 if (pipe_ctx->stream != stream)
305 pipe_to_program = pipe_ctx;
346 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local in function:dc_stream_set_cursor_position
544 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local in function:dc_stream_send_dp_sdp
617 struct pipe_ctx *pipe_ctx = NULL; local in function:dc_stream_set_dynamic_metadata
[all...] |
| amdgpu_dc.c | 126 * struct pipe_ctx - A member of struct resource_context. Represents the
292 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
319 struct pipe_ctx *pipe =
320 &dc->current_state->res_ctx.pipe_ctx[i];
348 struct pipe_ctx *pipe;
353 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
398 struct pipe_ctx *pipe;
402 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
423 struct pipe_ctx *pipe_ctx local in function:dc_stream_set_dyn_expansion
1486 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local in function:is_surface_in_context
2054 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local in function:commit_planes_do_stream_update
2205 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local in function:commit_planes_for_stream
2224 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local in function:commit_planes_for_stream
2289 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local in function:commit_planes_for_stream
2307 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local in function:commit_planes_for_stream
2331 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; local in function:commit_planes_for_stream
2414 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dc_commit_updates_for_stream
[all...] |
| amdgpu_dc_link.c | 1467 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1469 struct dc_stream_state *stream = pipe_ctx->stream;
1490 struct pipe_ctx *pipe_ctx)
1492 struct dc_stream_state *stream = pipe_ctx->stream;
1512 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1518 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1532 pipe_ctx,
1533 pipe_ctx->stream->signal))
2878 struct pipe_ctx *pipe_ctx; local in function:dc_link_reallocate_mst_payload
[all...] |
| amdgpu_dc_resource.c | 421 const struct pipe_ctx *pipe_with_clk_src,
422 const struct pipe_ctx *pipe)
453 struct pipe_ctx *pipe_ctx)
458 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
459 return res_ctx->pipe_ctx[i].clock_source;
540 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
542 const struct dc_plane_state *plane_state = pipe_ctx->plane_state
1361 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dc_remove_plane_from_context
1644 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; local in function:acquire_first_free_pipe
1915 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; local in function:acquire_resource_from_hw_enabled_state
1962 struct pipe_ctx *pipe_ctx = NULL; local in function:resource_map_pool_resources
2111 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; local in function:dc_validate_global_state
2594 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( local in function:resource_map_clock_resources
[all...] |
| amdgpu_dc_link_dp.c | 1507 struct pipe_ctx *pipe_ctx,
1512 struct dc_stream_state *stream = pipe_ctx->stream;
1521 pipe_ctx->clock_source->id,
1536 pipe_ctx->stream_res.stream_enc->id, true);
2682 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2683 struct pipe_ctx *pipe_ctx = &pipes[0]; local in function:dp_test_get_audio_test_data
2755 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++)
2816 struct pipe_ctx *pipe_ctx; local in function:dc_link_handle_hpd_rx_irq
3796 struct pipe_ctx *pipe_ctx = &pipes[0]; local in function:dc_link_dp_set_test_pattern
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dmub_psr.c | 107 struct pipe_ctx *pipe_ctx = NULL; local in function:dmub_setup_psr
112 res_ctx->pipe_ctx[i].stream &&
113 res_ctx->pipe_ctx[i].stream->link &&
114 res_ctx->pipe_ctx[i].stream->link == link &&
115 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
116 pipe_ctx = &res_ctx->pipe_ctx[i];
121 if (!pipe_ctx ||
122 !&pipe_ctx->plane_res |
[all...] |
| dce_clk_mgr.c | 195 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:get_max_pixel_clock_for_all_paths
197 if (pipe_ctx->stream == NULL)
201 if (pipe_ctx->top_pipe)
204 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
205 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
210 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
211 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
212 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk
509 const struct pipe_ctx *pipe_ctx = NULL; local in function:dce110_fill_display_configs
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr.c | 107 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; local in function:ramp_up_dispclk_with_dpp
109 if (!pipe_ctx->plane_state)
112 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
113 pipe_ctx->plane_res.dpp,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 137 const struct pipe_ctx *pipe_ctx = NULL; local in function:dce110_fill_display_configs
140 if (stream == context->res_ctx.pipe_ctx[k].stream) {
141 pipe_ctx = &context->res_ctx.pipe_ctx[k];
145 ASSERT(pipe_ctx != NULL);
152 cfg->signal = pipe_ctx->stream->signal;
153 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 176 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce_get_max_pixel_clock_for_all_paths
178 if (pipe_ctx->stream == NULL)
182 if (pipe_ctx->top_pipe)
185 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
186 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
191 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
192 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
193 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 804 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); local in function:build_mapped_resource
806 if (!pipe_ctx)
809 dce110_resource_build_pipe_hw_param(pipe_ctx);
811 resource_build_info_frame(pipe_ctx);
825 if (context->res_ctx.pipe_ctx[i].stream)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 850 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); local in function:build_mapped_resource
852 if (!pipe_ctx)
855 dce110_resource_build_pipe_hw_param(pipe_ctx);
857 resource_build_info_frame(pipe_ctx);
877 context->res_ctx.pipe_ctx,
941 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( local in function:resource_map_phy_clock_resources
944 if (!pipe_ctx)
947 if (dc_is_dp_signal(pipe_ctx->stream->signal
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 93 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
98 struct pipe_ctx *pipe_ctx,
110 if (pipe_ctx->stream_res.gsl_group > 0)
115 pipe_ctx->stream_res.gsl_group = group_idx;
137 group_idx = pipe_ctx->stream_res.gsl_group;
141 pipe_ctx->stream_res.gsl_group = 0;
165 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
167 pipe_ctx->stream_res.tg->funcs->set_gsl
1578 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn20_program_front_end_for_ctx
1627 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn20_program_front_end_for_ctx
1716 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn20_update_bandwidth
2095 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn20_reset_hw_ctx_wrap
2352 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn20_fpga_init_hw
2389 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn20_fpga_init_hw
[all...] |
| amdgpu_dcn20_resource.c | 1445 struct pipe_ctx *pipe_ctx,
1448 const struct dc_stream_state *stream = pipe_ctx->stream;
1449 struct pipe_ctx *odm_pipe;
1452 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1457 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1458 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1488 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1491 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params)
1510 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); local in function:dcn20_build_mapped_resource
1591 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; local in function:dcn20_add_dsc_to_stream_resource
1617 struct pipe_ctx *pipe_ctx = NULL; local in function:remove_dsc_from_stream_resource
2291 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; local in function:dcn20_validate_dsc
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 278 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
281 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
606 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
609 struct transform *xfm = pipe_ctx->plane_res.xfm;
631 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
636 ASSERT(pipe_ctx->stream);
638 if (pipe_ctx->stream_res.stream_enc == NULL
1643 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_set_displaymarks
1787 struct pipe_ctx *pipe_ctx = NULL; local in function:should_enable_fbc
1856 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; local in function:enable_fbc
1881 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_reset_hw_ctx_wrap
1966 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_setup_audio_dto
1994 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_setup_audio_dto
2045 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_apply_ctx_to_hw
2070 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_apply_ctx_to_hw
2583 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_apply_ctx_for_surface
2594 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_apply_ctx_for_surface
2616 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dce110_apply_ctx_for_surface
[all...] |
| amdgpu_dce110_resource.c | 861 const struct pipe_ctx *pipe_ctx,
864 const struct dc_stream_state *stream = pipe_ctx->stream;
872 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
873 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
895 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
897 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
898 pipe_ctx->clock_source->funcs->get_pix_clk_dividers
923 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); local in function:build_mapped_resource
1108 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; local in function:dce110_acquire_underlay
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 94 struct pipe_ctx *pipe_ctx; local in function:dcn10_lock_all_pipes
99 pipe_ctx = &context->res_ctx.pipe_ctx[i];
100 tg = pipe_ctx->stream_res.tg;
105 if (pipe_ctx->top_pipe ||
106 !pipe_ctx->stream || !pipe_ctx->plane_state ||
466 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
938 struct pipe_ctx *pipe_ctx = local in function:dcn10_hw_wa_force_recovery
963 struct pipe_ctx *pipe_ctx = local in function:dcn10_hw_wa_force_recovery
976 struct pipe_ctx *pipe_ctx = local in function:dcn10_hw_wa_force_recovery
986 struct pipe_ctx *pipe_ctx = local in function:dcn10_hw_wa_force_recovery
998 struct pipe_ctx *pipe_ctx = local in function:dcn10_hw_wa_force_recovery
1147 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn10_init_pipes
1173 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn10_init_pipes
1187 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn10_init_pipes
1382 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn10_reset_hw_ctx_wrap
2494 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn10_find_top_pipe_for_stream
2557 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn10_apply_ctx_for_surface
2594 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; local in function:dcn10_apply_ctx_for_surface
[all...] |
| amdgpu_dcn10_resource.c | 1030 const struct pipe_ctx *pipe_ctx,
1033 const struct dc_stream_state *stream = pipe_ctx->stream;
1036 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1037 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1064 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1067 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1069 pipe_ctx->clock_source->funcs->get_pix_clk_dividers
1086 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); local in function:build_mapped_resource
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 80 struct pipe_ctx *pipe_ctx);
82 void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
84 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
113 struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
278 struct pipe_ctx { struct
291 struct pipe_ctx *top_pipe;
292 struct pipe_ctx *bottom_pipe
308 struct pipe_ctx pipe_ctx[MAX_PIPES]; member in struct:resource_context
[all...] |
