| /src/tests/fs/common/ |
| fstest_nfs.c | 84 int pipes[2]; local in function:donewfs
109 if (pipe(pipes) == -1)
116 close(pipes[0]);
117 if (dup2(pipes[1], 3) == -1)
124 close(pipes[1]);
135 if (read(pipes[0], &devnull, 4) == -1)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_hwss.c | 106 struct pipe_ctx *pipes = local in function:dp_enable_link_phy
116 if (pipes[i].stream != NULL &&
117 pipes[i].stream->link == link) {
118 if (pipes[i].clock_source != NULL &&
119 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
120 pipes[i].clock_source = dp_cs;
121 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
122 pipes[i].stream->timing.pix_clk_100hz;
123 pipes[i].clock_source->funcs->program_pix_clk(
124 pipes[i].clock_source
315 struct pipe_ctx *pipes = local in function:dp_retrain_link_dp_test
[all...] |
| amdgpu_dc.c | 444 struct pipe_ctx *pipes = NULL; local in function:dc_stream_set_dither_option
450 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
455 if (!pipes)
466 if (pipes->plane_res.xfm &&
467 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
468 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
469 pipes->plane_res.xfm,
470 pipes->plane_res.scl_data.lb_params.depth,
474 pipes->stream_res.opp->funcs->
475 opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms)
482 struct pipe_ctx *pipes; local in function:dc_stream_set_gamut_remap
499 struct pipe_ctx *pipes; local in function:dc_stream_program_csc_matrix
[all...] |
| amdgpu_dc_link_dp.c | 2682 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; local in function:dp_test_get_audio_test_data
2683 struct pipe_ctx *pipe_ctx = &pipes[0];
3795 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; local in function:dc_link_dp_set_test_pattern
3796 struct pipe_ctx *pipe_ctx = &pipes[0];
3806 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3807 pipe_ctx = &pipes[i];
3853 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_mode_vba.c | 51 const display_e2e_pipe_params_st *pipes,
58 const display_e2e_pipe_params_st *pipes,
64 || memcmp(pipes, mode_lib->vba.cache_pipes,
69 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes);
72 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0)
85 #define dml_get_attr_func(attr, var) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) \
87 recalculate_params(mode_lib, pipes, num_pipes); \
115 #define dml_get_pipe_attr_func(attr, var) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
118 recalculate_params(mode_lib, pipes, num_pipes);
360 display_e2e_pipe_params_st *pipes = mode_lib->vba.cache_pipes; local in function:fetch_pipe_params
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| fb_decoder.h | 163 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES]; member in struct:intel_vgpu_fb_format
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 673 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
983 display_e2e_pipe_params_st *pipes,
990 pipes[0].clks_cfg.voltage = vlevel;
991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
992 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
998 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
999 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1000 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1001 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1002 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000
1139 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe local in function:dcn21_validate_bandwidth
[all...] |
| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_drm.h | 258 int pipes; member in struct:drm_i915_flip
350 /* Allow X server to configure which pipes to monitor for vblank signals
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 1601 /* The number of DSCs can be less than the number of pipes */
1833 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1844 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1845 pipes[pipe_cnt].dout.num_active_wb++;
1846 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1847 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1848 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1849 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1850 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1851 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1
2889 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe local in function:dcn20_validate_bandwidth_internal
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp.c | 835 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); local in function:vlv_find_free_pps
849 pipes &= ~(1 << intel_dp->pps_pipe);
854 pipes &= ~(1 << intel_dp->active_pipe);
858 if (pipes == 0)
861 return ffs(pipes) - 1;
1902 /* On TGL, FEC is supported on all Pipes */
|
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeTILEGX-encoder.c | 630 /* A bit mask of which of the five pipes this instruction
637 unsigned char pipes; member in struct:tilegx_opcode
|
