1 /* $NetBSD: cpufunc_asm_pj4b.S,v 1.14 2022/10/20 06:58:38 skrll Exp $ */ 2 3 /******************************************************************************* 4 Copyright (C) Marvell International Ltd. and its affiliates 5 6 Developed by Semihalf 7 8 ******************************************************************************** 9 Marvell BSD License 10 11 If you received this File from Marvell, you may opt to use, redistribute and/or 12 modify this File under the following licensing terms. 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in the 21 documentation and/or other materials provided with the distribution. 22 23 * Neither the name of Marvell nor the names of its contributors may be 24 used to endorse or promote products derived from this software without 25 specific prior written permission. 26 27 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 28 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 31 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 33 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 34 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 38 *******************************************************************************/ 39 40 #include "assym.h" 41 #include <arm/asm.h> 42 #include <arm/locore.h> 43 44 #define MV_FMC0_SMP (1 << 1) /* SMP/nAMP enable */ 45 #define MV_FMC0_PARITY (1 << 2) /* Enable L1 Cache Parity */ 46 #define MV_FMC0_LFDIS (1 << 7) /* Disable DC Speculative linefill */ 47 #define MV_FMC0_FW (1 << 8) /* Cache & TLB maintenance broadcast */ 48 49 #define MPIDR_CPUID_MASK (0x3 << 0) /* CPUID */ 50 #define MPIDR_CLUSTERID_MASK (0xf << 8) /* CLUSTERID */ 51 #define MPIDR_UNI_PROCESSOR (1 << 30) /* Uni-Processor System */ 52 #define MPIDR_MPCORE (1 << 31) /* New Style MPCore like CortexA9 */ 53 54 /* LINTSTUB: void pj4b_cpu_sleep(int); */ 55 ENTRY(pj4b_cpu_sleep) 56 dsb 57 wfi @ wait for an interrupt 58 dsb @ Erratum#ARM-CPU-4742 59 b irq_idle_entry @ assume we got an interrupt 60 END(pj4b_cpu_sleep) 61 62 /* LINTSTUB: void pj4b_config(void); */ 63 ENTRY(pj4b_config) 64 /* Set Marvell Auxiliary Debug Modes Control 0 register */ 65 mrc p15, 1, r0, c15, c1, 0 66 bic r0, r0, #(1 << 12) @ Erratum#ARM-CPU-6136 67 @ LDSTM 1st issue is single word 68 orr r0, r0, #(1 << 22) @ DVM_WAKEUP enable 69 mcr p15, 1, r0, c15, c1, 0 70 71 /* Set Marvell Auxiliary Debug Modes Control 1 register */ 72 mrc p15, 1, r0, c15, c1, 1 73 bic r0, r0, #(1 << 2) @ Erratum#ARM-CPU-6409 74 @ Disable static branch prediction 75 orr r0, r0, #(1 << 5) @ STREX backoff disable 76 mcr p15, 1, r0, c15, c1, 1 77 78 /* Set Marvell Auxiliary Debug Modes Control 2 register */ 79 mrc p15, 1, r0, c15, c1, 2 80 bic r0, r0, #(1 << 23) @ Enable fast LDR 81 orr r0, r0, #(1 << 25) @ Intervention Interleave disable 82 orr r0, r0, #(1 << 27) @ Critical word 1st sequencing dis. 83 orr r0, r0, #(1 << 29) @ Disable MO device R/W 84 orr r0, r0, #(1 << 30) @ L1 cache strict round-robin 85 orr r0, r0, #(1 << 31) @ Enable write evict 86 mcr p15, 1, r0, c15, c1, 2 87 88 /* Set Marvell Auxiliary Function Modes Control 0 register */ 89 mrc p15, 1, r0, c15, c2, 0 @ get FMC0 90 mrc p15, 0, ip, c0, c0, 5 @ get MPIDR 91 tst ip, #PJ4B_MPIDR_MP 92 beq 1f @ if not set, not a MPCORE 93 tst ip, #PJ4B_MPIDR_U 94 bne 1f @ if set, uni-processor system 95 orr r0, r0, #(PJ4B_AUXFMC0_SMPNAMP) @ enable SMP/nAMP 96 orr r0, r0, #(PJ4B_AUXFMC0_FW) @ enable maintenance bcast 97 1: 98 bic r0, r0, #(PJ4B_AUXFMC0_DCSLFD) @ enable speculative linefill 99 orr r0, r0, #(PJ4B_AUXFMC0_L1PARITY) @ enable L1 parity 100 mcr p15, 1, r0, c15, c2, 0 101 102 RET 103 END(pj4b_config) 104 105 #ifdef AURORA_IO_CACHE_COHERENCY 106 /* LINTSTUB: void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t); */ 107 ENTRY_NP(pj4b_io_coherency_barrier) 108 movw r0, #:lower16:_C_LABEL(armadaxp_l2_barrier_reg) 109 movt r0, #:upper16:_C_LABEL(armadaxp_l2_barrier_reg) 110 ldr r0, [r0] @ MVSOC_MLMB_CIB_BARRIER 111 mov r1, #1 @ MVSOC_MLMB_CIB_BARRIER_TRIGGER 112 str r1, [r0] 113 1: 114 ldr r1, [r0] 115 tst r1, #1 116 bne 1b @ if set, CIB is busy. 117 dsb 118 RET 119 END(pj4b_io_coherency_barrier) 120 121 STRONG_ALIAS(pj4b_dcache_cfu_wbinv_range, pj4b_io_coherency_barrier) 122 STRONG_ALIAS(pj4b_dcache_cfu_inv_range, pj4b_io_coherency_barrier) 123 STRONG_ALIAS(pj4b_dcache_cfu_wb_range, pj4b_io_coherency_barrier) 124 #endif 125
Indexes created Sat Sep 20 22:09:52 GMT 2025