1 /* $NetBSD: p_dti_tyne.c,v 1.20 2020/06/13 20:01:27 ad Exp $ */ 2 /* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */ 3 4 /* 5 * Copyright (c) 1988 University of Utah. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department, The Mach Operating System project at 12 * Carnegie-Mellon University and Ralph Campbell. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94 39 */ 40 41 #define __INTR_PRIVATE 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: p_dti_tyne.c,v 1.20 2020/06/13 20:01:27 ad Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/bus.h> 49 #include <sys/intr.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/autoconf.h> 54 #include <machine/pio.h> 55 #include <machine/platform.h> 56 #include <machine/wired_map.h> 57 #include <mips/pte.h> 58 59 #include <dev/isa/isareg.h> 60 #include <dev/isa/isavar.h> 61 #include <dev/ic/i8042reg.h> 62 63 #include <arc/dti/desktech.h> 64 65 void arc_sysreset(bus_addr_t, bus_size_t); 66 67 #include "pc.h" 68 #if NPC_ISA > 0 || NOPMS_ISA > 0 69 #include <arc/dev/pcconsvar.h> 70 #include <arc/isa/pccons_isavar.h> 71 #endif 72 73 #include "btl.h" 74 #if NBTL > 0 75 #include <arc/dti/btlvar.h> 76 #endif 77 78 const char *p_dti_tyne_mainbusdevs[] = { 79 "tyneisabr", 80 NULL 81 }; 82 83 void p_dti_tyne_init(void); 84 void p_dti_tyne_cons_init(void); 85 void p_dti_tyne_reset(void); 86 87 struct platform platform_desktech_tyne = { 88 "DESKTECH-TYNE", 89 "DESKTECH", 90 "", 91 "DeskStation Tyne", 92 "DESKTECH", 93 133, /* MHz */ 94 p_dti_tyne_mainbusdevs, 95 platform_generic_match, 96 p_dti_tyne_init, 97 c_isa_cons_init, 98 p_dti_tyne_reset, 99 arc_set_intr, 100 }; 101 102 /* 103 * This is a mask of bits to clear in the SR when we go to a 104 * given interrupt priority level. 105 */ 106 /* XXX see comments in p_dti_tyne_init() */ 107 static const struct ipl_sr_map dti_tyne_ipl_sr_map = { 108 .sr_bits = { 109 [IPL_NONE] = 0, 110 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 111 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0, 112 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, 113 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK, 114 [IPL_VM] = MIPS_INT_MASK, /* XXX */ 115 [IPL_SCHED] = MIPS_INT_MASK, 116 [IPL_DDB] = MIPS_INT_MASK, 117 [IPL_HIGH] = MIPS_INT_MASK, 118 }, 119 }; 120 121 #if NPC_ISA > 0 || NOPMS_ISA > 0 122 /* 123 * platform-dependent pccons configuration 124 */ 125 126 void pccons_dti_tyne_init(void); 127 128 struct pccons_config pccons_dti_tyne_conf = { 129 0x3b4, 0xb0000, /* mono: iobase, memaddr */ 130 0x3d4, 0xb8000, /* cga: iobase, memaddr */ 131 0x64, 0x60, /* kbdc: cmdport, dataport */ 132 pccons_dti_tyne_init, 133 }; 134 135 void 136 pccons_dti_tyne_init(void) 137 { 138 139 outb(arc_bus_io.bs_vbase + 0x3ce, 6); /* Correct video mode */ 140 outb(arc_bus_io.bs_vbase + 0x3cf, 141 inb(arc_bus_io.bs_vbase + 0x3cf) | 0xc); 142 kbc_put8042cmd(CMDBYTE); /* Want XT codes.. */ 143 } 144 145 #endif /* NPC_ISA > 0 || NOPMS_ISA > 0 */ 146 147 #if NBTL > 0 148 /* 149 * platform-dependent btl configuration 150 */ 151 152 void btl_dti_tyne_bouncemem(u_int *, u_int *); 153 uint32_t btl_dti_tyne_kvtophys(uint32_t); 154 uint32_t btl_dti_tyne_phystokv(uint32_t); 155 156 struct btl_config btl_dti_tyne_conf = { 157 btl_dti_tyne_bouncemem, 158 btl_dti_tyne_kvtophys, 159 btl_dti_tyne_phystokv, 160 }; 161 162 void 163 btl_dti_tyne_bouncemem(u_int *basep, u_int*sizep) 164 { 165 166 *basep = TYNE_V_BOUNCE; 167 *sizep = TYNE_S_BOUNCE; 168 } 169 170 uint32_t 171 btl_dti_tyne_kvtophys(uint32_t v) 172 { 173 return (v & 0x7fffff) | 0x800000; 174 } 175 176 uint32_t 177 btl_dti_tyne_phystokv(uint32_t p) 178 { 179 180 return (p & 0x7fffff) | TYNE_V_BOUNCE; 181 } 182 #endif /* NBTL > 0 */ 183 184 /* 185 * critial i/o space, interrupt, and other chipset related initialization. 186 */ 187 void 188 p_dti_tyne_init(void) 189 { 190 191 /* 192 * Initialize interrupt priority 193 */ 194 /* 195 * XXX 196 * - rewrite spl handling to allow ISA clock > bio|tty|net 197 * or 198 * - use MIP3_INTERNAL_TIMER_INTERRUPT for clock 199 */ 200 ipl_sr_map = dti_tyne_ipl_sr_map; 201 202 /* 203 * Initialize I/O address offset 204 */ 205 arc_bus_space_init(&arc_bus_io, "tyneisaio", 206 TYNE_P_ISA_IO, TYNE_V_ISA_IO, 0, TYNE_S_ISA_IO); 207 arc_bus_space_init(&arc_bus_mem, "tyneisamem", 208 TYNE_P_ISA_MEM, TYNE_V_ISA_MEM, 0, TYNE_S_ISA_MEM); 209 210 /* 211 * Initialize wired TLB for I/O space which is used on early stage 212 */ 213 arc_init_wired_map(); 214 arc_wired_enter_page(TYNE_V_BOUNCE, TYNE_P_BOUNCE, 215 MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_256K)); 216 217 arc_wired_enter_page(TYNE_V_ISA_IO, TYNE_P_ISA_IO, TYNE_S_ISA_IO); 218 arc_wired_enter_page(TYNE_V_ISA_MEM, TYNE_P_ISA_MEM, TYNE_S_ISA_MEM); 219 220 arc_wired_enter_page(0xe3000000, 0xfff00000, 221 MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_4K)); 222 223 /* 224 * common configuration for DTI platforms 225 */ 226 c_isa_init(); 227 228 #if NPC_ISA > 0 || NOPMS_ISA > 0 229 /* platform-dependent pccons configuration */ 230 pccons_isa_conf = &pccons_dti_tyne_conf; 231 #endif 232 233 #if NBTL > 0 234 /* platform-dependent btl configuration */ 235 btl_conf = &btl_dti_tyne_conf; 236 #endif 237 } 238 239 void 240 p_dti_tyne_reset(void) 241 { 242 243 arc_sysreset(TYNE_V_ISA_IO + IO_KBD, KBCMDP); 244 } 245
Indexes created Tue Sep 30 11:09:46 GMT 2025