1 /* $NetBSD: pmap.c,v 1.443 2024/04/13 12:28:01 skrll Exp $ */ 2 3 /* 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 1999, 2020 The NetBSD Foundation, Inc. 68 * All rights reserved. 69 * 70 * This code is derived from software contributed to The NetBSD Foundation 71 * by Charles M. Hannum. 72 * 73 * Redistribution and use in source and binary forms, with or without 74 * modification, are permitted provided that the following conditions 75 * are met: 76 * 1. Redistributions of source code must retain the above copyright 77 * notice, this list of conditions and the following disclaimer. 78 * 2. Redistributions in binary form must reproduce the above copyright 79 * notice, this list of conditions and the following disclaimer in the 80 * documentation and/or other materials provided with the distribution. 81 * 82 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 83 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 84 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 85 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 86 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 87 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 88 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 89 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 90 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 91 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 92 * POSSIBILITY OF SUCH DAMAGE. 93 */ 94 95 /* 96 * Copyright (c) 1994-1998 Mark Brinicombe. 97 * Copyright (c) 1994 Brini. 98 * All rights reserved. 99 * 100 * This code is derived from software written for Brini by Mark Brinicombe 101 * 102 * Redistribution and use in source and binary forms, with or without 103 * modification, are permitted provided that the following conditions 104 * are met: 105 * 1. Redistributions of source code must retain the above copyright 106 * notice, this list of conditions and the following disclaimer. 107 * 2. Redistributions in binary form must reproduce the above copyright 108 * notice, this list of conditions and the following disclaimer in the 109 * documentation and/or other materials provided with the distribution. 110 * 3. All advertising materials mentioning features or use of this software 111 * must display the following acknowledgement: 112 * This product includes software developed by Mark Brinicombe. 113 * 4. The name of the author may not be used to endorse or promote products 114 * derived from this software without specific prior written permission. 115 * 116 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 117 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 118 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 119 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 120 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 121 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 122 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 123 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 124 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 125 * 126 * RiscBSD kernel project 127 * 128 * pmap.c 129 * 130 * Machine dependent vm stuff 131 * 132 * Created : 20/09/94 133 */ 134 135 /* 136 * armv6 and VIPT cache support by 3am Software Foundry, 137 * Copyright (c) 2007 Microsoft 138 */ 139 140 /* 141 * Performance improvements, UVM changes, overhauls and part-rewrites 142 * were contributed by Neil A. Carson <neil (at) causality.com>. 143 */ 144 145 /* 146 * Overhauled again to speedup the pmap, use MMU Domains so that L1 tables 147 * can be shared, and re-work the KVM layout, by Steve Woodford of Wasabi 148 * Systems, Inc. 149 * 150 * There are still a few things outstanding at this time: 151 * 152 * - There are some unresolved issues for MP systems: 153 * 154 * o The L1 metadata needs a lock, or more specifically, some places 155 * need to acquire an exclusive lock when modifying L1 translation 156 * table entries. 157 * 158 * o When one cpu modifies an L1 entry, and that L1 table is also 159 * being used by another cpu, then the latter will need to be told 160 * that a tlb invalidation may be necessary. (But only if the old 161 * domain number in the L1 entry being over-written is currently 162 * the active domain on that cpu). I guess there are lots more tlb 163 * shootdown issues too... 164 * 165 * o If the vector_page is at 0x00000000 instead of in kernel VA space, 166 * then MP systems will lose big-time because of the MMU domain hack. 167 * The only way this can be solved (apart from moving the vector 168 * page to 0xffff0000) is to reserve the first 1MB of user address 169 * space for kernel use only. This would require re-linking all 170 * applications so that the text section starts above this 1MB 171 * boundary. 172 * 173 * o Tracking which VM space is resident in the cache/tlb has not yet 174 * been implemented for MP systems. 175 * 176 * o Finally, there is a pathological condition where two cpus running 177 * two separate processes (not lwps) which happen to share an L1 178 * can get into a fight over one or more L1 entries. This will result 179 * in a significant slow-down if both processes are in tight loops. 180 */ 181 182 /* Include header files */ 183 184 #include "opt_arm_debug.h" 185 #include "opt_cpuoptions.h" 186 #include "opt_ddb.h" 187 #include "opt_efi.h" 188 #include "opt_lockdebug.h" 189 #include "opt_multiprocessor.h" 190 191 #ifdef MULTIPROCESSOR 192 #define _INTR_PRIVATE 193 #endif 194 195 #include <sys/cdefs.h> 196 __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.443 2024/04/13 12:28:01 skrll Exp $"); 197 198 #include <sys/param.h> 199 #include <sys/types.h> 200 201 #include <sys/asan.h> 202 #include <sys/atomic.h> 203 #include <sys/bus.h> 204 #include <sys/cpu.h> 205 #include <sys/intr.h> 206 #include <sys/kernel.h> 207 #include <sys/kernhist.h> 208 #include <sys/kmem.h> 209 #include <sys/pool.h> 210 #include <sys/proc.h> 211 #include <sys/sysctl.h> 212 #include <sys/systm.h> 213 214 #include <uvm/uvm.h> 215 #include <uvm/pmap/pmap_pvt.h> 216 217 #include <arm/locore.h> 218 219 #ifdef DDB 220 #include <arm/db_machdep.h> 221 #endif 222 223 #ifdef VERBOSE_INIT_ARM 224 #define VPRINTF(...) printf(__VA_ARGS__) 225 #else 226 #define VPRINTF(...) __nothing 227 #endif 228 229 #if defined(EFI_RUNTIME) 230 #if !defined(ARM_MMU_EXTENDED) 231 #error EFI_RUNTIME is only supported with ARM_MMU_EXTENDED 232 #endif 233 #endif 234 235 /* 236 * pmap_kernel() points here 237 */ 238 static struct pmap kernel_pmap_store = { 239 #ifndef ARM_MMU_EXTENDED 240 .pm_activated = true, 241 .pm_domain = PMAP_DOMAIN_KERNEL, 242 .pm_cstate.cs_all = PMAP_CACHE_STATE_ALL, 243 #endif 244 }; 245 struct pmap * const kernel_pmap_ptr = &kernel_pmap_store; 246 #undef pmap_kernel 247 #define pmap_kernel() (&kernel_pmap_store) 248 249 #if defined(EFI_RUNTIME) 250 static struct pmap efirt_pmap; 251 252 struct pmap * 253 pmap_efirt(void) 254 { 255 return &efirt_pmap; 256 } 257 #endif 258 259 #ifdef PMAP_NEED_ALLOC_POOLPAGE 260 int arm_poolpage_vmfreelist = VM_FREELIST_DEFAULT; 261 #endif 262 263 /* 264 * Pool and cache that pmap structures are allocated from. 265 * We use a cache to avoid clearing the pm_l2[] array (1KB) 266 * in pmap_create(). 267 */ 268 static struct pool_cache pmap_cache; 269 270 /* 271 * Pool of PV structures 272 */ 273 static struct pool pmap_pv_pool; 274 static void *pmap_bootstrap_pv_page_alloc(struct pool *, int); 275 static void pmap_bootstrap_pv_page_free(struct pool *, void *); 276 static struct pool_allocator pmap_bootstrap_pv_allocator = { 277 pmap_bootstrap_pv_page_alloc, pmap_bootstrap_pv_page_free 278 }; 279 280 /* 281 * Pool and cache of l2_dtable structures. 282 * We use a cache to avoid clearing the structures when they're 283 * allocated. (196 bytes) 284 */ 285 static struct pool_cache pmap_l2dtable_cache; 286 static vaddr_t pmap_kernel_l2dtable_kva; 287 288 /* 289 * Pool and cache of L2 page descriptors. 290 * We use a cache to avoid clearing the descriptor table 291 * when they're allocated. (1KB) 292 */ 293 static struct pool_cache pmap_l2ptp_cache; 294 static vaddr_t pmap_kernel_l2ptp_kva; 295 static paddr_t pmap_kernel_l2ptp_phys; 296 297 #ifdef PMAPCOUNTERS 298 #define PMAP_EVCNT_INITIALIZER(name) \ 299 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap", name) 300 301 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 302 static struct evcnt pmap_ev_vac_clean_one = 303 PMAP_EVCNT_INITIALIZER("clean page (1 color)"); 304 static struct evcnt pmap_ev_vac_flush_one = 305 PMAP_EVCNT_INITIALIZER("flush page (1 color)"); 306 static struct evcnt pmap_ev_vac_flush_lots = 307 PMAP_EVCNT_INITIALIZER("flush page (2+ colors)"); 308 static struct evcnt pmap_ev_vac_flush_lots2 = 309 PMAP_EVCNT_INITIALIZER("flush page (2+ colors, kmpage)"); 310 EVCNT_ATTACH_STATIC(pmap_ev_vac_clean_one); 311 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_one); 312 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots); 313 EVCNT_ATTACH_STATIC(pmap_ev_vac_flush_lots2); 314 315 static struct evcnt pmap_ev_vac_color_new = 316 PMAP_EVCNT_INITIALIZER("new page color"); 317 static struct evcnt pmap_ev_vac_color_reuse = 318 PMAP_EVCNT_INITIALIZER("ok first page color"); 319 static struct evcnt pmap_ev_vac_color_ok = 320 PMAP_EVCNT_INITIALIZER("ok page color"); 321 static struct evcnt pmap_ev_vac_color_blind = 322 PMAP_EVCNT_INITIALIZER("blind page color"); 323 static struct evcnt pmap_ev_vac_color_change = 324 PMAP_EVCNT_INITIALIZER("change page color"); 325 static struct evcnt pmap_ev_vac_color_erase = 326 PMAP_EVCNT_INITIALIZER("erase page color"); 327 static struct evcnt pmap_ev_vac_color_none = 328 PMAP_EVCNT_INITIALIZER("no page color"); 329 static struct evcnt pmap_ev_vac_color_restore = 330 PMAP_EVCNT_INITIALIZER("restore page color"); 331 332 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_new); 333 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_reuse); 334 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_ok); 335 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_blind); 336 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_change); 337 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_erase); 338 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_none); 339 EVCNT_ATTACH_STATIC(pmap_ev_vac_color_restore); 340 #endif 341 342 static struct evcnt pmap_ev_mappings = 343 PMAP_EVCNT_INITIALIZER("pages mapped"); 344 static struct evcnt pmap_ev_unmappings = 345 PMAP_EVCNT_INITIALIZER("pages unmapped"); 346 static struct evcnt pmap_ev_remappings = 347 PMAP_EVCNT_INITIALIZER("pages remapped"); 348 349 EVCNT_ATTACH_STATIC(pmap_ev_mappings); 350 EVCNT_ATTACH_STATIC(pmap_ev_unmappings); 351 EVCNT_ATTACH_STATIC(pmap_ev_remappings); 352 353 static struct evcnt pmap_ev_kernel_mappings = 354 PMAP_EVCNT_INITIALIZER("kernel pages mapped"); 355 static struct evcnt pmap_ev_kernel_unmappings = 356 PMAP_EVCNT_INITIALIZER("kernel pages unmapped"); 357 static struct evcnt pmap_ev_kernel_remappings = 358 PMAP_EVCNT_INITIALIZER("kernel pages remapped"); 359 360 EVCNT_ATTACH_STATIC(pmap_ev_kernel_mappings); 361 EVCNT_ATTACH_STATIC(pmap_ev_kernel_unmappings); 362 EVCNT_ATTACH_STATIC(pmap_ev_kernel_remappings); 363 364 static struct evcnt pmap_ev_kenter_mappings = 365 PMAP_EVCNT_INITIALIZER("kenter pages mapped"); 366 static struct evcnt pmap_ev_kenter_unmappings = 367 PMAP_EVCNT_INITIALIZER("kenter pages unmapped"); 368 static struct evcnt pmap_ev_kenter_remappings = 369 PMAP_EVCNT_INITIALIZER("kenter pages remapped"); 370 static struct evcnt pmap_ev_pt_mappings = 371 PMAP_EVCNT_INITIALIZER("page table pages mapped"); 372 373 EVCNT_ATTACH_STATIC(pmap_ev_kenter_mappings); 374 EVCNT_ATTACH_STATIC(pmap_ev_kenter_unmappings); 375 EVCNT_ATTACH_STATIC(pmap_ev_kenter_remappings); 376 EVCNT_ATTACH_STATIC(pmap_ev_pt_mappings); 377 378 static struct evcnt pmap_ev_fixup_mod = 379 PMAP_EVCNT_INITIALIZER("page modification emulations"); 380 static struct evcnt pmap_ev_fixup_ref = 381 PMAP_EVCNT_INITIALIZER("page reference emulations"); 382 static struct evcnt pmap_ev_fixup_exec = 383 PMAP_EVCNT_INITIALIZER("exec pages fixed up"); 384 static struct evcnt pmap_ev_fixup_pdes = 385 PMAP_EVCNT_INITIALIZER("pdes fixed up"); 386 #ifndef ARM_MMU_EXTENDED 387 static struct evcnt pmap_ev_fixup_ptesync = 388 PMAP_EVCNT_INITIALIZER("ptesync fixed"); 389 #endif 390 391 EVCNT_ATTACH_STATIC(pmap_ev_fixup_mod); 392 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ref); 393 EVCNT_ATTACH_STATIC(pmap_ev_fixup_exec); 394 EVCNT_ATTACH_STATIC(pmap_ev_fixup_pdes); 395 #ifndef ARM_MMU_EXTENDED 396 EVCNT_ATTACH_STATIC(pmap_ev_fixup_ptesync); 397 #endif 398 399 #ifdef PMAP_CACHE_VIPT 400 static struct evcnt pmap_ev_exec_mappings = 401 PMAP_EVCNT_INITIALIZER("exec pages mapped"); 402 static struct evcnt pmap_ev_exec_cached = 403 PMAP_EVCNT_INITIALIZER("exec pages cached"); 404 405 EVCNT_ATTACH_STATIC(pmap_ev_exec_mappings); 406 EVCNT_ATTACH_STATIC(pmap_ev_exec_cached); 407 408 static struct evcnt pmap_ev_exec_synced = 409 PMAP_EVCNT_INITIALIZER("exec pages synced"); 410 static struct evcnt pmap_ev_exec_synced_map = 411 PMAP_EVCNT_INITIALIZER("exec pages synced (MP)"); 412 static struct evcnt pmap_ev_exec_synced_unmap = 413 PMAP_EVCNT_INITIALIZER("exec pages synced (UM)"); 414 static struct evcnt pmap_ev_exec_synced_remap = 415 PMAP_EVCNT_INITIALIZER("exec pages synced (RM)"); 416 static struct evcnt pmap_ev_exec_synced_clearbit = 417 PMAP_EVCNT_INITIALIZER("exec pages synced (DG)"); 418 #ifndef ARM_MMU_EXTENDED 419 static struct evcnt pmap_ev_exec_synced_kremove = 420 PMAP_EVCNT_INITIALIZER("exec pages synced (KU)"); 421 #endif 422 423 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced); 424 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_map); 425 #ifndef ARM_MMU_EXTENDED 426 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_unmap); 427 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_remap); 428 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_clearbit); 429 EVCNT_ATTACH_STATIC(pmap_ev_exec_synced_kremove); 430 #endif 431 432 static struct evcnt pmap_ev_exec_discarded_unmap = 433 PMAP_EVCNT_INITIALIZER("exec pages discarded (UM)"); 434 static struct evcnt pmap_ev_exec_discarded_zero = 435 PMAP_EVCNT_INITIALIZER("exec pages discarded (ZP)"); 436 static struct evcnt pmap_ev_exec_discarded_copy = 437 PMAP_EVCNT_INITIALIZER("exec pages discarded (CP)"); 438 static struct evcnt pmap_ev_exec_discarded_page_protect = 439 PMAP_EVCNT_INITIALIZER("exec pages discarded (PP)"); 440 static struct evcnt pmap_ev_exec_discarded_clearbit = 441 PMAP_EVCNT_INITIALIZER("exec pages discarded (DG)"); 442 static struct evcnt pmap_ev_exec_discarded_kremove = 443 PMAP_EVCNT_INITIALIZER("exec pages discarded (KU)"); 444 #ifdef ARM_MMU_EXTENDED 445 static struct evcnt pmap_ev_exec_discarded_modfixup = 446 PMAP_EVCNT_INITIALIZER("exec pages discarded (MF)"); 447 #endif 448 449 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_unmap); 450 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_zero); 451 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_copy); 452 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_page_protect); 453 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_clearbit); 454 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_kremove); 455 #ifdef ARM_MMU_EXTENDED 456 EVCNT_ATTACH_STATIC(pmap_ev_exec_discarded_modfixup); 457 #endif 458 #endif /* PMAP_CACHE_VIPT */ 459 460 static struct evcnt pmap_ev_updates = PMAP_EVCNT_INITIALIZER("updates"); 461 static struct evcnt pmap_ev_collects = PMAP_EVCNT_INITIALIZER("collects"); 462 static struct evcnt pmap_ev_activations = PMAP_EVCNT_INITIALIZER("activations"); 463 464 EVCNT_ATTACH_STATIC(pmap_ev_updates); 465 EVCNT_ATTACH_STATIC(pmap_ev_collects); 466 EVCNT_ATTACH_STATIC(pmap_ev_activations); 467 468 #define PMAPCOUNT(x) ((void)(pmap_ev_##x.ev_count++)) 469 #else 470 #define PMAPCOUNT(x) ((void)0) 471 #endif 472 473 #ifdef ARM_MMU_EXTENDED 474 void pmap_md_pdetab_activate(pmap_t, struct lwp *); 475 void pmap_md_pdetab_deactivate(pmap_t pm); 476 #endif 477 478 /* 479 * pmap copy/zero page, and mem(5) hook point 480 */ 481 static pt_entry_t *csrc_pte, *cdst_pte; 482 static vaddr_t csrcp, cdstp; 483 #ifdef MULTIPROCESSOR 484 static size_t cnptes; 485 #define cpu_csrc_pte(o) (csrc_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 486 #define cpu_cdst_pte(o) (cdst_pte + cnptes * cpu_number() + ((o) >> L2_S_SHIFT)) 487 #define cpu_csrcp(o) (csrcp + L2_S_SIZE * cnptes * cpu_number() + (o)) 488 #define cpu_cdstp(o) (cdstp + L2_S_SIZE * cnptes * cpu_number() + (o)) 489 #else 490 #define cpu_csrc_pte(o) (csrc_pte + ((o) >> L2_S_SHIFT)) 491 #define cpu_cdst_pte(o) (cdst_pte + ((o) >> L2_S_SHIFT)) 492 #define cpu_csrcp(o) (csrcp + (o)) 493 #define cpu_cdstp(o) (cdstp + (o)) 494 #endif 495 vaddr_t memhook; /* used by mem.c & others */ 496 kmutex_t memlock __cacheline_aligned; /* used by mem.c & others */ 497 kmutex_t pmap_lock __cacheline_aligned; 498 kmutex_t kpm_lock __cacheline_aligned; 499 extern void *msgbufaddr; 500 int pmap_kmpages; 501 /* 502 * Flag to indicate if pmap_init() has done its thing 503 */ 504 bool pmap_initialized; 505 506 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 507 /* 508 * Virtual end of direct-mapped memory 509 */ 510 vaddr_t pmap_directlimit; 511 #endif 512 513 /* 514 * Misc. locking data structures 515 */ 516 517 static inline void 518 pmap_acquire_pmap_lock(pmap_t pm) 519 { 520 #if defined(MULTIPROCESSOR) && defined(DDB) 521 if (__predict_false(db_onproc != NULL)) 522 return; 523 #endif 524 525 mutex_enter(&pm->pm_lock); 526 } 527 528 static inline void 529 pmap_release_pmap_lock(pmap_t pm) 530 { 531 #if defined(MULTIPROCESSOR) && defined(DDB) 532 if (__predict_false(db_onproc != NULL)) 533 return; 534 #endif 535 mutex_exit(&pm->pm_lock); 536 } 537 538 static inline void 539 pmap_acquire_page_lock(struct vm_page_md *md) 540 { 541 mutex_enter(&pmap_lock); 542 } 543 544 static inline void 545 pmap_release_page_lock(struct vm_page_md *md) 546 { 547 mutex_exit(&pmap_lock); 548 } 549 550 static inline int __diagused 551 pmap_page_locked_p(struct vm_page_md *md) 552 { 553 return mutex_owned(&pmap_lock); 554 } 555 556 557 /* 558 * Metadata for L1 translation tables. 559 */ 560 #ifndef ARM_MMU_EXTENDED 561 struct l1_ttable { 562 /* Entry on the L1 Table list */ 563 SLIST_ENTRY(l1_ttable) l1_link; 564 565 /* Entry on the L1 Least Recently Used list */ 566 TAILQ_ENTRY(l1_ttable) l1_lru; 567 568 /* Track how many domains are allocated from this L1 */ 569 volatile u_int l1_domain_use_count; 570 571 /* 572 * A free-list of domain numbers for this L1. 573 * We avoid using ffs() and a bitmap to track domains since ffs() 574 * is slow on ARM. 575 */ 576 uint8_t l1_domain_first; 577 uint8_t l1_domain_free[PMAP_DOMAINS]; 578 579 /* Physical address of this L1 page table */ 580 paddr_t l1_physaddr; 581 582 /* KVA of this L1 page table */ 583 pd_entry_t *l1_kva; 584 }; 585 586 /* 587 * L1 Page Tables are tracked using a Least Recently Used list. 588 * - New L1s are allocated from the HEAD. 589 * - Freed L1s are added to the TAIL. 590 * - Recently accessed L1s (where an 'access' is some change to one of 591 * the userland pmaps which owns this L1) are moved to the TAIL. 592 */ 593 static TAILQ_HEAD(, l1_ttable) l1_lru_list; 594 static kmutex_t l1_lru_lock __cacheline_aligned; 595 596 /* 597 * A list of all L1 tables 598 */ 599 static SLIST_HEAD(, l1_ttable) l1_list; 600 #endif /* ARM_MMU_EXTENDED */ 601 602 /* 603 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 604 * 605 * This is normally 16MB worth L2 page descriptors for any given pmap. 606 * Reference counts are maintained for L2 descriptors so they can be 607 * freed when empty. 608 */ 609 struct l2_bucket { 610 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 611 paddr_t l2b_pa; /* Physical address of same */ 612 u_short l2b_l1slot; /* This L2 table's L1 index */ 613 u_short l2b_occupancy; /* How many active descriptors */ 614 }; 615 616 struct l2_dtable { 617 /* The number of L2 page descriptors allocated to this l2_dtable */ 618 u_int l2_occupancy; 619 620 /* List of L2 page descriptors */ 621 struct l2_bucket l2_bucket[L2_BUCKET_SIZE]; 622 }; 623 624 /* 625 * Given an L1 table index, calculate the corresponding l2_dtable index 626 * and bucket index within the l2_dtable. 627 */ 628 #define L2_BUCKET_XSHIFT (L2_BUCKET_XLOG2 - L1_S_SHIFT) 629 #define L2_BUCKET_XFRAME (~(vaddr_t)0 << L2_BUCKET_XLOG2) 630 #define L2_BUCKET_IDX(l1slot) ((l1slot) >> L2_BUCKET_XSHIFT) 631 #define L2_IDX(l1slot) (L2_BUCKET_IDX(l1slot) >> L2_BUCKET_LOG2) 632 #define L2_BUCKET(l1slot) (L2_BUCKET_IDX(l1slot) & (L2_BUCKET_SIZE - 1)) 633 634 __CTASSERT(0x100000000ULL == ((uint64_t)L2_SIZE * L2_BUCKET_SIZE * L1_S_SIZE)); 635 __CTASSERT(L2_BUCKET_XFRAME == ~(L2_BUCKET_XSIZE-1)); 636 637 /* 638 * Given a virtual address, this macro returns the 639 * virtual address required to drop into the next L2 bucket. 640 */ 641 #define L2_NEXT_BUCKET_VA(va) (((va) & L2_BUCKET_XFRAME) + L2_BUCKET_XSIZE) 642 643 /* 644 * L2 allocation. 645 */ 646 #define pmap_alloc_l2_dtable() \ 647 pool_cache_get(&pmap_l2dtable_cache, PR_NOWAIT) 648 #define pmap_free_l2_dtable(l2) \ 649 pool_cache_put(&pmap_l2dtable_cache, (l2)) 650 #define pmap_alloc_l2_ptp(pap) \ 651 ((pt_entry_t *)pool_cache_get_paddr(&pmap_l2ptp_cache,\ 652 PR_NOWAIT, (pap))) 653 654 /* 655 * We try to map the page tables write-through, if possible. However, not 656 * all CPUs have a write-through cache mode, so on those we have to sync 657 * the cache when we frob page tables. 658 * 659 * We try to evaluate this at compile time, if possible. However, it's 660 * not always possible to do that, hence this run-time var. 661 */ 662 int pmap_needs_pte_sync; 663 664 /* 665 * Real definition of pv_entry. 666 */ 667 struct pv_entry { 668 SLIST_ENTRY(pv_entry) pv_link; /* next pv_entry */ 669 pmap_t pv_pmap; /* pmap where mapping lies */ 670 vaddr_t pv_va; /* virtual address for mapping */ 671 u_int pv_flags; /* flags */ 672 }; 673 674 /* 675 * Macros to determine if a mapping might be resident in the 676 * instruction/data cache and/or TLB 677 */ 678 #if ARM_MMU_V7 > 0 && !defined(ARM_MMU_EXTENDED) 679 /* 680 * Speculative loads by Cortex cores can cause TLB entries to be filled even if 681 * there are no explicit accesses, so there may be always be TLB entries to 682 * flush. If we used ASIDs then this would not be a problem. 683 */ 684 #define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC) 685 #define PV_BEEN_REFD(f) (true) 686 #else 687 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 688 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 689 #endif 690 #define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0) 691 #define PV_IS_KENTRY_P(f) (((f) & PVF_KENTRY) != 0) 692 #define PV_IS_WRITE_P(f) (((f) & PVF_WRITE) != 0) 693 694 /* 695 * Local prototypes 696 */ 697 static bool pmap_set_pt_cache_mode(pd_entry_t *, vaddr_t, size_t); 698 static void pmap_alloc_specials(vaddr_t *, int, vaddr_t *, 699 pt_entry_t **); 700 static bool pmap_is_current(pmap_t) __unused; 701 static bool pmap_is_cached(pmap_t); 702 static void pmap_enter_pv(struct vm_page_md *, paddr_t, struct pv_entry *, 703 pmap_t, vaddr_t, u_int); 704 static struct pv_entry *pmap_find_pv(struct vm_page_md *, pmap_t, vaddr_t); 705 static struct pv_entry *pmap_remove_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 706 static u_int pmap_modify_pv(struct vm_page_md *, paddr_t, pmap_t, vaddr_t, 707 u_int, u_int); 708 709 static void pmap_pinit(pmap_t); 710 static int pmap_pmap_ctor(void *, void *, int); 711 712 static void pmap_alloc_l1(pmap_t); 713 static void pmap_free_l1(pmap_t); 714 #ifndef ARM_MMU_EXTENDED 715 static void pmap_use_l1(pmap_t); 716 #endif 717 718 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vaddr_t); 719 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vaddr_t); 720 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 721 static int pmap_l2ptp_ctor(void *, void *, int); 722 static int pmap_l2dtable_ctor(void *, void *, int); 723 724 static void pmap_vac_me_harder(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 725 #ifdef PMAP_CACHE_VIVT 726 static void pmap_vac_me_kpmap(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 727 static void pmap_vac_me_user(struct vm_page_md *, paddr_t, pmap_t, vaddr_t); 728 #endif 729 730 static void pmap_clearbit(struct vm_page_md *, paddr_t, u_int); 731 #ifdef PMAP_CACHE_VIVT 732 static bool pmap_clean_page(struct vm_page_md *, bool); 733 #endif 734 #ifdef PMAP_CACHE_VIPT 735 static void pmap_syncicache_page(struct vm_page_md *, paddr_t); 736 enum pmap_flush_op { 737 PMAP_FLUSH_PRIMARY, 738 PMAP_FLUSH_SECONDARY, 739 PMAP_CLEAN_PRIMARY 740 }; 741 #ifndef ARM_MMU_EXTENDED 742 static void pmap_flush_page(struct vm_page_md *, paddr_t, enum pmap_flush_op); 743 #endif 744 #endif 745 static void pmap_page_remove(struct vm_page_md *, paddr_t); 746 static void pmap_pv_remove(paddr_t); 747 748 #ifndef ARM_MMU_EXTENDED 749 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 750 #endif 751 static vaddr_t kernel_pt_lookup(paddr_t); 752 753 #ifdef ARM_MMU_EXTENDED 754 static struct pool_cache pmap_l1tt_cache; 755 756 static int pmap_l1tt_ctor(void *, void *, int); 757 static void * pmap_l1tt_alloc(struct pool *, int); 758 static void pmap_l1tt_free(struct pool *, void *); 759 760 static struct pool_allocator pmap_l1tt_allocator = { 761 .pa_alloc = pmap_l1tt_alloc, 762 .pa_free = pmap_l1tt_free, 763 .pa_pagesz = L1TT_SIZE, 764 }; 765 #endif 766 767 /* 768 * Misc variables 769 */ 770 vaddr_t virtual_avail; 771 vaddr_t virtual_end; 772 vaddr_t pmap_curmaxkvaddr; 773 774 paddr_t avail_start; 775 paddr_t avail_end; 776 777 pv_addrqh_t pmap_boot_freeq = SLIST_HEAD_INITIALIZER(&pmap_boot_freeq); 778 pv_addr_t kernelpages; 779 pv_addr_t kernel_l1pt; 780 pv_addr_t systempage; 781 #if defined(EFI_RUNTIME) 782 pv_addr_t efirt_l1pt; 783 #endif 784 785 #ifdef PMAP_CACHE_VIPT 786 #define PMAP_VALIDATE_MD_PAGE(md) \ 787 KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \ 788 "(md) %p: attrs=%#x urw=%u krw=%u", (md), \ 789 (md)->pvh_attrs, (md)->urw_mappings, (md)->krw_mappings); 790 #endif /* PMAP_CACHE_VIPT */ 791 /* 792 * A bunch of routines to conditionally flush the caches/TLB depending 793 * on whether the specified pmap actually needs to be flushed at any 794 * given time. 795 */ 796 static inline void 797 pmap_tlb_flush_SE(pmap_t pm, vaddr_t va, u_int flags) 798 { 799 #ifdef ARM_MMU_EXTENDED 800 pmap_tlb_invalidate_addr(pm, va); 801 #else 802 if (pm->pm_cstate.cs_tlb_id != 0) { 803 if (PV_BEEN_EXECD(flags)) { 804 cpu_tlb_flushID_SE(va); 805 } else if (PV_BEEN_REFD(flags)) { 806 cpu_tlb_flushD_SE(va); 807 } 808 } 809 #endif /* ARM_MMU_EXTENDED */ 810 } 811 812 #ifndef ARM_MMU_EXTENDED 813 static inline void 814 pmap_tlb_flushID(pmap_t pm) 815 { 816 if (pm->pm_cstate.cs_tlb_id) { 817 cpu_tlb_flushID(); 818 #if ARM_MMU_V7 == 0 819 /* 820 * Speculative loads by Cortex cores can cause TLB entries to 821 * be filled even if there are no explicit accesses, so there 822 * may be always be TLB entries to flush. If we used ASIDs 823 * then it would not be a problem. 824 * This is not true for other CPUs. 825 */ 826 pm->pm_cstate.cs_tlb = 0; 827 #endif /* ARM_MMU_V7 */ 828 } 829 } 830 831 static inline void 832 pmap_tlb_flushD(pmap_t pm) 833 { 834 if (pm->pm_cstate.cs_tlb_d) { 835 cpu_tlb_flushD(); 836 #if ARM_MMU_V7 == 0 837 /* 838 * Speculative loads by Cortex cores can cause TLB entries to 839 * be filled even if there are no explicit accesses, so there 840 * may be always be TLB entries to flush. If we used ASIDs 841 * then it would not be a problem. 842 * This is not true for other CPUs. 843 */ 844 pm->pm_cstate.cs_tlb_d = 0; 845 #endif /* ARM_MMU_V7 */ 846 } 847 } 848 #endif /* ARM_MMU_EXTENDED */ 849 850 #ifdef PMAP_CACHE_VIVT 851 static inline void 852 pmap_cache_wbinv_page(pmap_t pm, vaddr_t va, bool do_inv, u_int flags) 853 { 854 if (PV_BEEN_EXECD(flags) && pm->pm_cstate.cs_cache_id) { 855 cpu_idcache_wbinv_range(va, PAGE_SIZE); 856 } else if (PV_BEEN_REFD(flags) && pm->pm_cstate.cs_cache_d) { 857 if (do_inv) { 858 if (flags & PVF_WRITE) 859 cpu_dcache_wbinv_range(va, PAGE_SIZE); 860 else 861 cpu_dcache_inv_range(va, PAGE_SIZE); 862 } else if (flags & PVF_WRITE) { 863 cpu_dcache_wb_range(va, PAGE_SIZE); 864 } 865 } 866 } 867 868 static inline void 869 pmap_cache_wbinv_all(pmap_t pm, u_int flags) 870 { 871 if (PV_BEEN_EXECD(flags)) { 872 if (pm->pm_cstate.cs_cache_id) { 873 cpu_idcache_wbinv_all(); 874 pm->pm_cstate.cs_cache = 0; 875 } 876 } else if (pm->pm_cstate.cs_cache_d) { 877 cpu_dcache_wbinv_all(); 878 pm->pm_cstate.cs_cache_d = 0; 879 } 880 } 881 #endif /* PMAP_CACHE_VIVT */ 882 883 static inline uint8_t 884 pmap_domain(pmap_t pm) 885 { 886 #ifdef ARM_MMU_EXTENDED 887 return pm == pmap_kernel() ? PMAP_DOMAIN_KERNEL : PMAP_DOMAIN_USER; 888 #else 889 return pm->pm_domain; 890 #endif 891 } 892 893 static inline pd_entry_t * 894 pmap_l1_kva(pmap_t pm) 895 { 896 #ifdef ARM_MMU_EXTENDED 897 return pm->pm_l1; 898 #else 899 return pm->pm_l1->l1_kva; 900 #endif 901 } 902 903 static inline bool 904 pmap_is_current(pmap_t pm) 905 { 906 if (pm == pmap_kernel() || curproc->p_vmspace->vm_map.pmap == pm) 907 return true; 908 909 return false; 910 } 911 912 static inline bool 913 pmap_is_cached(pmap_t pm) 914 { 915 #ifdef ARM_MMU_EXTENDED 916 if (pm == pmap_kernel()) 917 return true; 918 #ifdef MULTIPROCESSOR 919 // Is this pmap active on any CPU? 920 if (!kcpuset_iszero(pm->pm_active)) 921 return true; 922 #else 923 struct pmap_tlb_info * const ti = cpu_tlb_info(curcpu()); 924 // Is this pmap active? 925 if (PMAP_PAI_ASIDVALID_P(PMAP_PAI(pm, ti), ti)) 926 return true; 927 #endif 928 #else 929 struct cpu_info * const ci = curcpu(); 930 if (pm == pmap_kernel() || ci->ci_pmap_lastuser == NULL 931 || ci->ci_pmap_lastuser == pm) 932 return true; 933 #endif /* ARM_MMU_EXTENDED */ 934 935 return false; 936 } 937 938 /* 939 * PTE_SYNC_CURRENT: 940 * 941 * Make sure the pte is written out to RAM. 942 * We need to do this for one of two cases: 943 * - We're dealing with the kernel pmap 944 * - There is no pmap active in the cache/tlb. 945 * - The specified pmap is 'active' in the cache/tlb. 946 */ 947 948 #ifdef PMAP_INCLUDE_PTE_SYNC 949 static inline void 950 pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep) 951 { 952 if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm)) 953 PTE_SYNC(ptep); 954 dsb(sy); 955 } 956 957 # define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep) 958 #else 959 # define PTE_SYNC_CURRENT(pm, ptep) __nothing 960 #endif 961 962 /* 963 * main pv_entry manipulation functions: 964 * pmap_enter_pv: enter a mapping onto a vm_page list 965 * pmap_remove_pv: remove a mapping from a vm_page list 966 * 967 * NOTE: pmap_enter_pv expects to lock the pvh itself 968 * pmap_remove_pv expects the caller to lock the pvh before calling 969 */ 970 971 /* 972 * pmap_enter_pv: enter a mapping onto a vm_page lst 973 * 974 * => caller should hold the proper lock on pmap_main_lock 975 * => caller should have pmap locked 976 * => we will gain the lock on the vm_page and allocate the new pv_entry 977 * => caller should adjust ptp's wire_count before calling 978 * => caller should not adjust pmap's wire_count 979 */ 980 static void 981 pmap_enter_pv(struct vm_page_md *md, paddr_t pa, struct pv_entry *pv, pmap_t pm, 982 vaddr_t va, u_int flags) 983 { 984 UVMHIST_FUNC(__func__); 985 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 986 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 987 UVMHIST_LOG(maphist, "...pv %#jx flags %#jx", 988 (uintptr_t)pv, flags, 0, 0); 989 990 struct pv_entry **pvp; 991 992 pv->pv_pmap = pm; 993 pv->pv_va = va; 994 pv->pv_flags = flags; 995 996 pvp = &SLIST_FIRST(&md->pvh_list); 997 #ifdef PMAP_CACHE_VIPT 998 /* 999 * Insert unmanaged entries, writeable first, at the head of 1000 * the pv list. 1001 */ 1002 if (__predict_true(!PV_IS_KENTRY_P(flags))) { 1003 while (*pvp != NULL && PV_IS_KENTRY_P((*pvp)->pv_flags)) 1004 pvp = &SLIST_NEXT(*pvp, pv_link); 1005 } 1006 if (!PV_IS_WRITE_P(flags)) { 1007 while (*pvp != NULL && PV_IS_WRITE_P((*pvp)->pv_flags)) 1008 pvp = &SLIST_NEXT(*pvp, pv_link); 1009 } 1010 #endif 1011 SLIST_NEXT(pv, pv_link) = *pvp; /* add to ... */ 1012 *pvp = pv; /* ... locked list */ 1013 md->pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1014 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1015 if ((pv->pv_flags & PVF_KWRITE) == PVF_KWRITE) 1016 md->pvh_attrs |= PVF_KMOD; 1017 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1018 md->pvh_attrs |= PVF_DIRTY; 1019 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1020 #endif 1021 if (pm == pmap_kernel()) { 1022 PMAPCOUNT(kernel_mappings); 1023 if (flags & PVF_WRITE) 1024 md->krw_mappings++; 1025 else 1026 md->kro_mappings++; 1027 } else { 1028 if (flags & PVF_WRITE) 1029 md->urw_mappings++; 1030 else 1031 md->uro_mappings++; 1032 } 1033 1034 #ifdef PMAP_CACHE_VIPT 1035 #ifndef ARM_MMU_EXTENDED 1036 /* 1037 * Even though pmap_vac_me_harder will set PVF_WRITE for us, 1038 * do it here as well to keep the mappings & KVF_WRITE consistent. 1039 */ 1040 if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) { 1041 md->pvh_attrs |= PVF_WRITE; 1042 } 1043 #endif 1044 /* 1045 * If this is an exec mapping and its the first exec mapping 1046 * for this page, make sure to sync the I-cache. 1047 */ 1048 if (PV_IS_EXEC_P(flags)) { 1049 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 1050 pmap_syncicache_page(md, pa); 1051 PMAPCOUNT(exec_synced_map); 1052 } 1053 PMAPCOUNT(exec_mappings); 1054 } 1055 #endif 1056 1057 PMAPCOUNT(mappings); 1058 1059 if (pv->pv_flags & PVF_WIRED) 1060 ++pm->pm_stats.wired_count; 1061 } 1062 1063 /* 1064 * 1065 * pmap_find_pv: Find a pv entry 1066 * 1067 * => caller should hold lock on vm_page 1068 */ 1069 static inline struct pv_entry * 1070 pmap_find_pv(struct vm_page_md *md, pmap_t pm, vaddr_t va) 1071 { 1072 struct pv_entry *pv; 1073 1074 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1075 if (pm == pv->pv_pmap && va == pv->pv_va) 1076 break; 1077 } 1078 1079 return pv; 1080 } 1081 1082 /* 1083 * pmap_remove_pv: try to remove a mapping from a pv_list 1084 * 1085 * => caller should hold proper lock on pmap_main_lock 1086 * => pmap should be locked 1087 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1088 * => caller should adjust ptp's wire_count and free PTP if needed 1089 * => caller should NOT adjust pmap's wire_count 1090 * => we return the removed pv 1091 */ 1092 static struct pv_entry * 1093 pmap_remove_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1094 { 1095 UVMHIST_FUNC(__func__); 1096 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1097 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1098 1099 struct pv_entry *pv, **prevptr; 1100 1101 prevptr = &SLIST_FIRST(&md->pvh_list); /* prev pv_entry ptr */ 1102 pv = *prevptr; 1103 1104 while (pv) { 1105 if (pv->pv_pmap == pm && pv->pv_va == va) { /* match? */ 1106 UVMHIST_LOG(maphist, "pm %#jx md %#jx flags %#jx", 1107 (uintptr_t)pm, (uintptr_t)md, pv->pv_flags, 0); 1108 if (pv->pv_flags & PVF_WIRED) { 1109 --pm->pm_stats.wired_count; 1110 } 1111 *prevptr = SLIST_NEXT(pv, pv_link); /* remove it! */ 1112 if (pm == pmap_kernel()) { 1113 PMAPCOUNT(kernel_unmappings); 1114 if (pv->pv_flags & PVF_WRITE) 1115 md->krw_mappings--; 1116 else 1117 md->kro_mappings--; 1118 } else { 1119 if (pv->pv_flags & PVF_WRITE) 1120 md->urw_mappings--; 1121 else 1122 md->uro_mappings--; 1123 } 1124 1125 PMAPCOUNT(unmappings); 1126 #ifdef PMAP_CACHE_VIPT 1127 /* 1128 * If this page has had an exec mapping, then if 1129 * this was the last mapping, discard the contents, 1130 * otherwise sync the i-cache for this page. 1131 */ 1132 if (PV_IS_EXEC_P(md->pvh_attrs)) { 1133 if (SLIST_EMPTY(&md->pvh_list)) { 1134 md->pvh_attrs &= ~PVF_EXEC; 1135 PMAPCOUNT(exec_discarded_unmap); 1136 } else if (pv->pv_flags & PVF_WRITE) { 1137 pmap_syncicache_page(md, pa); 1138 PMAPCOUNT(exec_synced_unmap); 1139 } 1140 } 1141 #endif /* PMAP_CACHE_VIPT */ 1142 break; 1143 } 1144 prevptr = &SLIST_NEXT(pv, pv_link); /* previous pointer */ 1145 pv = *prevptr; /* advance */ 1146 } 1147 1148 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1149 /* 1150 * If we no longer have a WRITEABLE KENTRY at the head of list, 1151 * clear the KMOD attribute from the page. 1152 */ 1153 if (SLIST_FIRST(&md->pvh_list) == NULL 1154 || (SLIST_FIRST(&md->pvh_list)->pv_flags & PVF_KWRITE) != PVF_KWRITE) 1155 md->pvh_attrs &= ~PVF_KMOD; 1156 1157 /* 1158 * If this was a writeable page and there are no more writeable 1159 * mappings (ignoring KMPAGE), clear the WRITE flag and writeback 1160 * the contents to memory. 1161 */ 1162 if (arm_cache_prefer_mask != 0) { 1163 if (md->krw_mappings + md->urw_mappings == 0) 1164 md->pvh_attrs &= ~PVF_WRITE; 1165 PMAP_VALIDATE_MD_PAGE(md); 1166 } 1167 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1168 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1169 1170 /* return removed pv */ 1171 return pv; 1172 } 1173 1174 /* 1175 * 1176 * pmap_modify_pv: Update pv flags 1177 * 1178 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1179 * => caller should NOT adjust pmap's wire_count 1180 * => caller must call pmap_vac_me_harder() if writable status of a page 1181 * may have changed. 1182 * => we return the old flags 1183 * 1184 * Modify a physical-virtual mapping in the pv table 1185 */ 1186 static u_int 1187 pmap_modify_pv(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va, 1188 u_int clr_mask, u_int set_mask) 1189 { 1190 struct pv_entry *npv; 1191 u_int flags, oflags; 1192 UVMHIST_FUNC(__func__); 1193 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 1194 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 1195 UVMHIST_LOG(maphist, "... clr %#jx set %#jx", clr_mask, set_mask, 0, 0); 1196 1197 KASSERT(!PV_IS_KENTRY_P(clr_mask)); 1198 KASSERT(!PV_IS_KENTRY_P(set_mask)); 1199 1200 if ((npv = pmap_find_pv(md, pm, va)) == NULL) { 1201 UVMHIST_LOG(maphist, "<--- done (not found)", 0, 0, 0, 0); 1202 return 0; 1203 } 1204 1205 /* 1206 * There is at least one VA mapping this page. 1207 */ 1208 1209 if (clr_mask & (PVF_REF | PVF_MOD)) { 1210 md->pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1211 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 1212 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) != PVF_NC) 1213 md->pvh_attrs |= PVF_DIRTY; 1214 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1215 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 1216 } 1217 1218 oflags = npv->pv_flags; 1219 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1220 1221 if ((flags ^ oflags) & PVF_WIRED) { 1222 if (flags & PVF_WIRED) 1223 ++pm->pm_stats.wired_count; 1224 else 1225 --pm->pm_stats.wired_count; 1226 } 1227 1228 if ((flags ^ oflags) & PVF_WRITE) { 1229 if (pm == pmap_kernel()) { 1230 if (flags & PVF_WRITE) { 1231 md->krw_mappings++; 1232 md->kro_mappings--; 1233 } else { 1234 md->kro_mappings++; 1235 md->krw_mappings--; 1236 } 1237 } else { 1238 if (flags & PVF_WRITE) { 1239 md->urw_mappings++; 1240 md->uro_mappings--; 1241 } else { 1242 md->uro_mappings++; 1243 md->urw_mappings--; 1244 } 1245 } 1246 } 1247 #ifdef PMAP_CACHE_VIPT 1248 if (arm_cache_prefer_mask != 0) { 1249 if (md->urw_mappings + md->krw_mappings == 0) { 1250 md->pvh_attrs &= ~PVF_WRITE; 1251 } else { 1252 md->pvh_attrs |= PVF_WRITE; 1253 } 1254 } 1255 /* 1256 * We have two cases here: the first is from enter_pv (new exec 1257 * page), the second is a combined pmap_remove_pv/pmap_enter_pv. 1258 * Since in latter, pmap_enter_pv won't do anything, we just have 1259 * to do what pmap_remove_pv would do. 1260 */ 1261 if ((PV_IS_EXEC_P(flags) && !PV_IS_EXEC_P(md->pvh_attrs)) 1262 || (PV_IS_EXEC_P(md->pvh_attrs) 1263 || (!(flags & PVF_WRITE) && (oflags & PVF_WRITE)))) { 1264 pmap_syncicache_page(md, pa); 1265 PMAPCOUNT(exec_synced_remap); 1266 } 1267 #ifndef ARM_MMU_EXTENDED 1268 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 1269 #endif /* !ARM_MMU_EXTENDED */ 1270 #endif /* PMAP_CACHE_VIPT */ 1271 1272 PMAPCOUNT(remappings); 1273 1274 UVMHIST_LOG(maphist, "<--- done", 0, 0, 0, 0); 1275 1276 return oflags; 1277 } 1278 1279 1280 #if defined(ARM_MMU_EXTENDED) 1281 int 1282 pmap_maxproc_set(int nmaxproc) 1283 { 1284 static const char pmap_l1ttpool_warnmsg[] = 1285 "WARNING: l1ttpool limit reached; increase kern.maxproc"; 1286 1287 pool_cache_prime(&pmap_l1tt_cache, nmaxproc); 1288 1289 /* 1290 * Set the hard limit on the pmap_l1tt_cache to the number 1291 * of processes the kernel is to support. Log the limit 1292 * reached message max once a minute. 1293 */ 1294 pool_cache_sethardlimit(&pmap_l1tt_cache, nmaxproc, 1295 pmap_l1ttpool_warnmsg, 60); 1296 1297 return 0; 1298 } 1299 1300 #endif 1301 1302 /* 1303 * Allocate an L1 translation table for the specified pmap. 1304 * This is called at pmap creation time. 1305 */ 1306 static void 1307 pmap_alloc_l1(pmap_t pm) 1308 { 1309 #ifdef ARM_MMU_EXTENDED 1310 vaddr_t va = (vaddr_t)pool_cache_get_paddr(&pmap_l1tt_cache, PR_WAITOK, 1311 &pm->pm_l1_pa); 1312 1313 pm->pm_l1 = (pd_entry_t *)va; 1314 PTE_SYNC_RANGE(pm->pm_l1, L1TT_SIZE / sizeof(pt_entry_t)); 1315 #else 1316 struct l1_ttable *l1; 1317 uint8_t domain; 1318 1319 /* 1320 * Remove the L1 at the head of the LRU list 1321 */ 1322 mutex_spin_enter(&l1_lru_lock); 1323 l1 = TAILQ_FIRST(&l1_lru_list); 1324 KDASSERT(l1 != NULL); 1325 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1326 1327 /* 1328 * Pick the first available domain number, and update 1329 * the link to the next number. 1330 */ 1331 domain = l1->l1_domain_first; 1332 l1->l1_domain_first = l1->l1_domain_free[domain]; 1333 1334 /* 1335 * If there are still free domain numbers in this L1, 1336 * put it back on the TAIL of the LRU list. 1337 */ 1338 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 1339 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1340 1341 mutex_spin_exit(&l1_lru_lock); 1342 1343 /* 1344 * Fix up the relevant bits in the pmap structure 1345 */ 1346 pm->pm_l1 = l1; 1347 pm->pm_domain = domain + 1; 1348 #endif 1349 } 1350 1351 /* 1352 * Free an L1 translation table. 1353 * This is called at pmap destruction time. 1354 */ 1355 static void 1356 pmap_free_l1(pmap_t pm) 1357 { 1358 #ifdef ARM_MMU_EXTENDED 1359 pool_cache_put_paddr(&pmap_l1tt_cache, (void *)pm->pm_l1, pm->pm_l1_pa); 1360 1361 pm->pm_l1 = NULL; 1362 pm->pm_l1_pa = 0; 1363 #else 1364 struct l1_ttable *l1 = pm->pm_l1; 1365 1366 mutex_spin_enter(&l1_lru_lock); 1367 1368 /* 1369 * If this L1 is currently on the LRU list, remove it. 1370 */ 1371 if (l1->l1_domain_use_count < PMAP_DOMAINS) 1372 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1373 1374 /* 1375 * Free up the domain number which was allocated to the pmap 1376 */ 1377 l1->l1_domain_free[pmap_domain(pm) - 1] = l1->l1_domain_first; 1378 l1->l1_domain_first = pmap_domain(pm) - 1; 1379 l1->l1_domain_use_count--; 1380 1381 /* 1382 * The L1 now must have at least 1 free domain, so add 1383 * it back to the LRU list. If the use count is zero, 1384 * put it at the head of the list, otherwise it goes 1385 * to the tail. 1386 */ 1387 if (l1->l1_domain_use_count == 0) 1388 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 1389 else 1390 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1391 1392 mutex_spin_exit(&l1_lru_lock); 1393 #endif /* ARM_MMU_EXTENDED */ 1394 } 1395 1396 #ifndef ARM_MMU_EXTENDED 1397 static inline void 1398 pmap_use_l1(pmap_t pm) 1399 { 1400 struct l1_ttable *l1; 1401 1402 /* 1403 * Do nothing if we're in interrupt context. 1404 * Access to an L1 by the kernel pmap must not affect 1405 * the LRU list. 1406 */ 1407 if (cpu_intr_p() || pm == pmap_kernel()) 1408 return; 1409 1410 l1 = pm->pm_l1; 1411 1412 /* 1413 * If the L1 is not currently on the LRU list, just return 1414 */ 1415 if (l1->l1_domain_use_count == PMAP_DOMAINS) 1416 return; 1417 1418 mutex_spin_enter(&l1_lru_lock); 1419 1420 /* 1421 * Check the use count again, now that we've acquired the lock 1422 */ 1423 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 1424 mutex_spin_exit(&l1_lru_lock); 1425 return; 1426 } 1427 1428 /* 1429 * Move the L1 to the back of the LRU list 1430 */ 1431 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 1432 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 1433 1434 mutex_spin_exit(&l1_lru_lock); 1435 } 1436 #endif /* !ARM_MMU_EXTENDED */ 1437 1438 /* 1439 * void pmap_free_l2_ptp(pt_entry_t *, paddr_t *) 1440 * 1441 * Free an L2 descriptor table. 1442 */ 1443 static inline void 1444 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1445 pmap_free_l2_ptp(bool need_sync, pt_entry_t *l2, paddr_t pa) 1446 #else 1447 pmap_free_l2_ptp(pt_entry_t *l2, paddr_t pa) 1448 #endif 1449 { 1450 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1451 /* 1452 * Note: With a write-back cache, we may need to sync this 1453 * L2 table before re-using it. 1454 * This is because it may have belonged to a non-current 1455 * pmap, in which case the cache syncs would have been 1456 * skipped for the pages that were being unmapped. If the 1457 * L2 table were then to be immediately re-allocated to 1458 * the *current* pmap, it may well contain stale mappings 1459 * which have not yet been cleared by a cache write-back 1460 * and so would still be visible to the mmu. 1461 */ 1462 if (need_sync) 1463 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1464 #endif /* PMAP_INCLUDE_PTE_SYNC && PMAP_CACHE_VIVT */ 1465 pool_cache_put_paddr(&pmap_l2ptp_cache, (void *)l2, pa); 1466 } 1467 1468 /* 1469 * Returns a pointer to the L2 bucket associated with the specified pmap 1470 * and VA, or NULL if no L2 bucket exists for the address. 1471 */ 1472 static inline struct l2_bucket * 1473 pmap_get_l2_bucket(pmap_t pm, vaddr_t va) 1474 { 1475 const size_t l1slot = l1pte_index(va); 1476 struct l2_dtable *l2; 1477 struct l2_bucket *l2b; 1478 1479 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL || 1480 (l2b = &l2->l2_bucket[L2_BUCKET(l1slot)])->l2b_kva == NULL) 1481 return NULL; 1482 1483 return l2b; 1484 } 1485 1486 /* 1487 * Returns a pointer to the L2 bucket associated with the specified pmap 1488 * and VA. 1489 * 1490 * If no L2 bucket exists, perform the necessary allocations to put an L2 1491 * bucket/page table in place. 1492 * 1493 * Note that if a new L2 bucket/page was allocated, the caller *must* 1494 * increment the bucket occupancy counter appropriately *before* 1495 * releasing the pmap's lock to ensure no other thread or cpu deallocates 1496 * the bucket/page in the meantime. 1497 */ 1498 static struct l2_bucket * 1499 pmap_alloc_l2_bucket(pmap_t pm, vaddr_t va) 1500 { 1501 const size_t l1slot = l1pte_index(va); 1502 struct l2_dtable *l2; 1503 1504 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 1505 /* 1506 * No mapping at this address, as there is 1507 * no entry in the L1 table. 1508 * Need to allocate a new l2_dtable. 1509 */ 1510 if ((l2 = pmap_alloc_l2_dtable()) == NULL) 1511 return NULL; 1512 1513 /* 1514 * Link it into the parent pmap 1515 */ 1516 pm->pm_l2[L2_IDX(l1slot)] = l2; 1517 } 1518 1519 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 1520 1521 /* 1522 * Fetch pointer to the L2 page table associated with the address. 1523 */ 1524 if (l2b->l2b_kva == NULL) { 1525 pt_entry_t *ptep; 1526 1527 /* 1528 * No L2 page table has been allocated. Chances are, this 1529 * is because we just allocated the l2_dtable, above. 1530 */ 1531 if ((ptep = pmap_alloc_l2_ptp(&l2b->l2b_pa)) == NULL) { 1532 /* 1533 * Oops, no more L2 page tables available at this 1534 * time. We may need to deallocate the l2_dtable 1535 * if we allocated a new one above. 1536 */ 1537 if (l2->l2_occupancy == 0) { 1538 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1539 pmap_free_l2_dtable(l2); 1540 } 1541 return NULL; 1542 } 1543 1544 l2->l2_occupancy++; 1545 l2b->l2b_kva = ptep; 1546 l2b->l2b_l1slot = l1slot; 1547 1548 #ifdef ARM_MMU_EXTENDED 1549 /* 1550 * We know there will be a mapping here, so simply 1551 * enter this PTP into the L1 now. 1552 */ 1553 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1554 pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 1555 | L1_C_DOM(pmap_domain(pm)); 1556 KASSERT(*pdep == 0); 1557 l1pte_setone(pdep, npde); 1558 PDE_SYNC(pdep); 1559 #endif 1560 } 1561 1562 return l2b; 1563 } 1564 1565 /* 1566 * One or more mappings in the specified L2 descriptor table have just been 1567 * invalidated. 1568 * 1569 * Garbage collect the metadata and descriptor table itself if necessary. 1570 * 1571 * The pmap lock must be acquired when this is called (not necessary 1572 * for the kernel pmap). 1573 */ 1574 static void 1575 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1576 { 1577 KDASSERT(count <= l2b->l2b_occupancy); 1578 1579 /* 1580 * Update the bucket's reference count according to how many 1581 * PTEs the caller has just invalidated. 1582 */ 1583 l2b->l2b_occupancy -= count; 1584 1585 /* 1586 * Note: 1587 * 1588 * Level 2 page tables allocated to the kernel pmap are never freed 1589 * as that would require checking all Level 1 page tables and 1590 * removing any references to the Level 2 page table. See also the 1591 * comment elsewhere about never freeing bootstrap L2 descriptors. 1592 * 1593 * We make do with just invalidating the mapping in the L2 table. 1594 * 1595 * This isn't really a big deal in practice and, in fact, leads 1596 * to a performance win over time as we don't need to continually 1597 * alloc/free. 1598 */ 1599 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1600 return; 1601 1602 /* 1603 * There are no more valid mappings in this level 2 page table. 1604 * Go ahead and NULL-out the pointer in the bucket, then 1605 * free the page table. 1606 */ 1607 const size_t l1slot = l2b->l2b_l1slot; 1608 pt_entry_t * const ptep = l2b->l2b_kva; 1609 l2b->l2b_kva = NULL; 1610 1611 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 1612 pd_entry_t pde __diagused = *pdep; 1613 1614 #ifdef ARM_MMU_EXTENDED 1615 /* 1616 * Invalidate the L1 slot. 1617 */ 1618 KASSERT((pde & L1_TYPE_MASK) == L1_TYPE_C); 1619 #else 1620 /* 1621 * If the L1 slot matches the pmap's domain number, then invalidate it. 1622 */ 1623 if ((pde & (L1_C_DOM_MASK|L1_TYPE_MASK)) 1624 == (L1_C_DOM(pmap_domain(pm))|L1_TYPE_C)) { 1625 #endif 1626 l1pte_setone(pdep, 0); 1627 PDE_SYNC(pdep); 1628 #ifndef ARM_MMU_EXTENDED 1629 } 1630 #endif 1631 1632 /* 1633 * Release the L2 descriptor table back to the pool cache. 1634 */ 1635 #if defined(PMAP_INCLUDE_PTE_SYNC) && defined(PMAP_CACHE_VIVT) 1636 pmap_free_l2_ptp(!pmap_is_cached(pm), ptep, l2b->l2b_pa); 1637 #else 1638 pmap_free_l2_ptp(ptep, l2b->l2b_pa); 1639 #endif 1640 1641 /* 1642 * Update the reference count in the associated l2_dtable 1643 */ 1644 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 1645 if (--l2->l2_occupancy > 0) 1646 return; 1647 1648 /* 1649 * There are no more valid mappings in any of the Level 1 1650 * slots managed by this l2_dtable. Go ahead and NULL-out 1651 * the pointer in the parent pmap and free the l2_dtable. 1652 */ 1653 pm->pm_l2[L2_IDX(l1slot)] = NULL; 1654 pmap_free_l2_dtable(l2); 1655 } 1656 1657 #if defined(ARM_MMU_EXTENDED) 1658 /* 1659 * Pool cache constructors for L1 translation tables 1660 */ 1661 1662 static int 1663 pmap_l1tt_ctor(void *arg, void *v, int flags) 1664 { 1665 #ifndef PMAP_INCLUDE_PTE_SYNC 1666 #error not supported 1667 #endif 1668 1669 memset(v, 0, L1TT_SIZE); 1670 PTE_SYNC_RANGE(v, L1TT_SIZE / sizeof(pt_entry_t)); 1671 return 0; 1672 } 1673 #endif 1674 1675 /* 1676 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1677 * structures. 1678 */ 1679 static int 1680 pmap_l2ptp_ctor(void *arg, void *v, int flags) 1681 { 1682 #ifndef PMAP_INCLUDE_PTE_SYNC 1683 vaddr_t va = (vaddr_t)v & ~PGOFSET; 1684 1685 /* 1686 * The mappings for these page tables were initially made using 1687 * pmap_kenter_pa() by the pool subsystem. Therefore, the cache- 1688 * mode will not be right for page table mappings. To avoid 1689 * polluting the pmap_kenter_pa() code with a special case for 1690 * page tables, we simply fix up the cache-mode here if it's not 1691 * correct. 1692 */ 1693 if (pte_l2_s_cache_mode != pte_l2_s_cache_mode_pt) { 1694 const struct l2_bucket * const l2b = 1695 pmap_get_l2_bucket(pmap_kernel(), va); 1696 KASSERTMSG(l2b != NULL, "%#lx", va); 1697 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 1698 const pt_entry_t opte = *ptep; 1699 1700 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1701 /* 1702 * Page tables must have the cache-mode set correctly. 1703 */ 1704 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 1705 | pte_l2_s_cache_mode_pt; 1706 l2pte_set(ptep, npte, opte); 1707 PTE_SYNC(ptep); 1708 cpu_tlb_flushD_SE(va); 1709 cpu_cpwait(); 1710 } 1711 } 1712 #endif 1713 1714 memset(v, 0, L2_TABLE_SIZE_REAL); 1715 PTE_SYNC_RANGE(v, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1716 return 0; 1717 } 1718 1719 static int 1720 pmap_l2dtable_ctor(void *arg, void *v, int flags) 1721 { 1722 1723 memset(v, 0, sizeof(struct l2_dtable)); 1724 return 0; 1725 } 1726 1727 static int 1728 pmap_pmap_ctor(void *arg, void *v, int flags) 1729 { 1730 1731 memset(v, 0, sizeof(struct pmap)); 1732 return 0; 1733 } 1734 1735 static void 1736 pmap_pinit(pmap_t pm) 1737 { 1738 #ifndef ARM_HAS_VBAR 1739 struct l2_bucket *l2b; 1740 1741 if (vector_page < KERNEL_BASE) { 1742 /* 1743 * Map the vector page. 1744 */ 1745 pmap_enter(pm, vector_page, systempage.pv_pa, 1746 VM_PROT_READ | VM_PROT_EXECUTE, 1747 VM_PROT_READ | VM_PROT_EXECUTE | PMAP_WIRED); 1748 pmap_update(pm); 1749 1750 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 1751 l2b = pmap_get_l2_bucket(pm, vector_page); 1752 KASSERTMSG(l2b != NULL, "%#lx", vector_page); 1753 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 1754 L1_C_DOM(pmap_domain(pm)); 1755 } else 1756 pm->pm_pl1vec = NULL; 1757 #endif 1758 } 1759 1760 #ifdef PMAP_CACHE_VIVT 1761 /* 1762 * Since we have a virtually indexed cache, we may need to inhibit caching if 1763 * there is more than one mapping and at least one of them is writable. 1764 * Since we purge the cache on every context switch, we only need to check for 1765 * other mappings within the same pmap, or kernel_pmap. 1766 * This function is also called when a page is unmapped, to possibly reenable 1767 * caching on any remaining mappings. 1768 * 1769 * The code implements the following logic, where: 1770 * 1771 * KW = # of kernel read/write pages 1772 * KR = # of kernel read only pages 1773 * UW = # of user read/write pages 1774 * UR = # of user read only pages 1775 * 1776 * KC = kernel mapping is cacheable 1777 * UC = user mapping is cacheable 1778 * 1779 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1780 * +--------------------------------------------- 1781 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1782 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1783 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1784 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1785 */ 1786 1787 static const int pmap_vac_flags[4][4] = { 1788 {-1, 0, 0, PVF_KNC}, 1789 {0, 0, PVF_NC, PVF_NC}, 1790 {0, PVF_NC, PVF_NC, PVF_NC}, 1791 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1792 }; 1793 1794 static inline int 1795 pmap_get_vac_flags(const struct vm_page_md *md) 1796 { 1797 int kidx, uidx; 1798 1799 kidx = 0; 1800 if (md->kro_mappings || md->krw_mappings > 1) 1801 kidx |= 1; 1802 if (md->krw_mappings) 1803 kidx |= 2; 1804 1805 uidx = 0; 1806 if (md->uro_mappings || md->urw_mappings > 1) 1807 uidx |= 1; 1808 if (md->urw_mappings) 1809 uidx |= 2; 1810 1811 return pmap_vac_flags[uidx][kidx]; 1812 } 1813 1814 static inline void 1815 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1816 { 1817 int nattr; 1818 1819 nattr = pmap_get_vac_flags(md); 1820 1821 if (nattr < 0) { 1822 md->pvh_attrs &= ~PVF_NC; 1823 return; 1824 } 1825 1826 if (nattr == 0 && (md->pvh_attrs & PVF_NC) == 0) 1827 return; 1828 1829 if (pm == pmap_kernel()) 1830 pmap_vac_me_kpmap(md, pa, pm, va); 1831 else 1832 pmap_vac_me_user(md, pa, pm, va); 1833 1834 md->pvh_attrs = (md->pvh_attrs & ~PVF_NC) | nattr; 1835 } 1836 1837 static void 1838 pmap_vac_me_kpmap(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1839 { 1840 u_int u_cacheable, u_entries; 1841 struct pv_entry *pv; 1842 pmap_t last_pmap = pm; 1843 1844 /* 1845 * Pass one, see if there are both kernel and user pmaps for 1846 * this page. Calculate whether there are user-writable or 1847 * kernel-writable pages. 1848 */ 1849 u_cacheable = 0; 1850 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1851 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1852 u_cacheable++; 1853 } 1854 1855 u_entries = md->urw_mappings + md->uro_mappings; 1856 1857 /* 1858 * We know we have just been updating a kernel entry, so if 1859 * all user pages are already cacheable, then there is nothing 1860 * further to do. 1861 */ 1862 if (md->k_mappings == 0 && u_cacheable == u_entries) 1863 return; 1864 1865 if (u_entries) { 1866 /* 1867 * Scan over the list again, for each entry, if it 1868 * might not be set correctly, call pmap_vac_me_user 1869 * to recalculate the settings. 1870 */ 1871 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1872 /* 1873 * We know kernel mappings will get set 1874 * correctly in other calls. We also know 1875 * that if the pmap is the same as last_pmap 1876 * then we've just handled this entry. 1877 */ 1878 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1879 continue; 1880 1881 /* 1882 * If there are kernel entries and this page 1883 * is writable but non-cacheable, then we can 1884 * skip this entry also. 1885 */ 1886 if (md->k_mappings && 1887 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1888 (PVF_NC | PVF_WRITE)) 1889 continue; 1890 1891 /* 1892 * Similarly if there are no kernel-writable 1893 * entries and the page is already 1894 * read-only/cacheable. 1895 */ 1896 if (md->krw_mappings == 0 && 1897 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1898 continue; 1899 1900 /* 1901 * For some of the remaining cases, we know 1902 * that we must recalculate, but for others we 1903 * can't tell if they are correct or not, so 1904 * we recalculate anyway. 1905 */ 1906 pmap_vac_me_user(md, pa, (last_pmap = pv->pv_pmap), 0); 1907 } 1908 1909 if (md->k_mappings == 0) 1910 return; 1911 } 1912 1913 pmap_vac_me_user(md, pa, pm, va); 1914 } 1915 1916 static void 1917 pmap_vac_me_user(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 1918 { 1919 pmap_t kpmap = pmap_kernel(); 1920 struct pv_entry *pv, *npv = NULL; 1921 u_int entries = 0; 1922 u_int writable = 0; 1923 u_int cacheable_entries = 0; 1924 u_int kern_cacheable = 0; 1925 u_int other_writable = 0; 1926 1927 /* 1928 * Count mappings and writable mappings in this pmap. 1929 * Include kernel mappings as part of our own. 1930 * Keep a pointer to the first one. 1931 */ 1932 npv = NULL; 1933 KASSERT(pmap_page_locked_p(md)); 1934 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 1935 /* Count mappings in the same pmap */ 1936 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1937 if (entries++ == 0) 1938 npv = pv; 1939 1940 /* Cacheable mappings */ 1941 if ((pv->pv_flags & PVF_NC) == 0) { 1942 cacheable_entries++; 1943 if (kpmap == pv->pv_pmap) 1944 kern_cacheable++; 1945 } 1946 1947 /* Writable mappings */ 1948 if (pv->pv_flags & PVF_WRITE) 1949 ++writable; 1950 } else if (pv->pv_flags & PVF_WRITE) 1951 other_writable = 1; 1952 } 1953 1954 /* 1955 * Enable or disable caching as necessary. 1956 * Note: the first entry might be part of the kernel pmap, 1957 * so we can't assume this is indicative of the state of the 1958 * other (maybe non-kpmap) entries. 1959 */ 1960 if ((entries > 1 && writable) || 1961 (entries > 0 && pm == kpmap && other_writable)) { 1962 if (cacheable_entries == 0) { 1963 return; 1964 } 1965 1966 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1967 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1968 (pv->pv_flags & PVF_NC)) 1969 continue; 1970 1971 pv->pv_flags |= PVF_NC; 1972 1973 struct l2_bucket * const l2b 1974 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1975 KASSERTMSG(l2b != NULL, "%#lx", va); 1976 pt_entry_t * const ptep 1977 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1978 const pt_entry_t opte = *ptep; 1979 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 1980 1981 if ((va != pv->pv_va || pm != pv->pv_pmap) 1982 && l2pte_valid_p(opte)) { 1983 pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va, 1984 true, pv->pv_flags); 1985 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 1986 pv->pv_flags); 1987 } 1988 1989 l2pte_set(ptep, npte, opte); 1990 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1991 } 1992 cpu_cpwait(); 1993 } else if (entries > cacheable_entries) { 1994 /* 1995 * Turn cacheing back on for some pages. If it is a kernel 1996 * page, only do so if there are no other writable pages. 1997 */ 1998 for (pv = npv; pv; pv = SLIST_NEXT(pv, pv_link)) { 1999 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 2000 (kpmap != pv->pv_pmap || other_writable))) 2001 continue; 2002 2003 pv->pv_flags &= ~PVF_NC; 2004 2005 struct l2_bucket * const l2b 2006 = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 2007 KASSERTMSG(l2b != NULL, "%#lx", va); 2008 pt_entry_t * const ptep 2009 = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2010 const pt_entry_t opte = *ptep; 2011 pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 2012 | pte_l2_s_cache_mode; 2013 2014 if (l2pte_valid_p(opte)) { 2015 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, 2016 pv->pv_flags); 2017 } 2018 2019 l2pte_set(ptep, npte, opte); 2020 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2021 } 2022 } 2023 } 2024 #endif 2025 2026 #ifdef PMAP_CACHE_VIPT 2027 static void 2028 pmap_vac_me_harder(struct vm_page_md *md, paddr_t pa, pmap_t pm, vaddr_t va) 2029 { 2030 2031 #ifndef ARM_MMU_EXTENDED 2032 struct pv_entry *pv; 2033 vaddr_t tst_mask; 2034 bool bad_alias; 2035 const u_int 2036 rw_mappings = md->urw_mappings + md->krw_mappings, 2037 ro_mappings = md->uro_mappings + md->kro_mappings; 2038 2039 /* do we need to do anything? */ 2040 if (arm_cache_prefer_mask == 0) 2041 return; 2042 2043 UVMHIST_FUNC(__func__); 2044 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx pm %#jx va %#jx", 2045 (uintptr_t)md, (uintptr_t)pa, (uintptr_t)pm, va); 2046 2047 KASSERT(!va || pm); 2048 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2049 2050 /* Already a conflict? */ 2051 if (__predict_false(md->pvh_attrs & PVF_NC)) { 2052 /* just an add, things are already non-cached */ 2053 KASSERT(!(md->pvh_attrs & PVF_DIRTY)); 2054 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2055 bad_alias = false; 2056 if (va) { 2057 PMAPCOUNT(vac_color_none); 2058 bad_alias = true; 2059 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2060 goto fixup; 2061 } 2062 pv = SLIST_FIRST(&md->pvh_list); 2063 /* the list can't be empty because it would be cachable */ 2064 if (md->pvh_attrs & PVF_KMPAGE) { 2065 tst_mask = md->pvh_attrs; 2066 } else { 2067 KASSERT(pv); 2068 tst_mask = pv->pv_va; 2069 pv = SLIST_NEXT(pv, pv_link); 2070 } 2071 /* 2072 * Only check for a bad alias if we have writable mappings. 2073 */ 2074 tst_mask &= arm_cache_prefer_mask; 2075 if (rw_mappings > 0) { 2076 for (; pv && !bad_alias; pv = SLIST_NEXT(pv, pv_link)) { 2077 /* if there's a bad alias, stop checking. */ 2078 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) 2079 bad_alias = true; 2080 } 2081 md->pvh_attrs |= PVF_WRITE; 2082 if (!bad_alias) 2083 md->pvh_attrs |= PVF_DIRTY; 2084 } else { 2085 /* 2086 * We have only read-only mappings. Let's see if there 2087 * are multiple colors in use or if we mapped a KMPAGE. 2088 * If the latter, we have a bad alias. If the former, 2089 * we need to remember that. 2090 */ 2091 for (; pv; pv = SLIST_NEXT(pv, pv_link)) { 2092 if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) { 2093 if (md->pvh_attrs & PVF_KMPAGE) 2094 bad_alias = true; 2095 break; 2096 } 2097 } 2098 md->pvh_attrs &= ~PVF_WRITE; 2099 /* 2100 * No KMPAGE and we exited early, so we must have 2101 * multiple color mappings. 2102 */ 2103 if (!bad_alias && pv != NULL) 2104 md->pvh_attrs |= PVF_MULTCLR; 2105 } 2106 2107 /* If no conflicting colors, set everything back to cached */ 2108 if (!bad_alias) { 2109 #ifdef DEBUG 2110 if ((md->pvh_attrs & PVF_WRITE) 2111 || ro_mappings < 2) { 2112 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2113 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2114 } 2115 #endif 2116 md->pvh_attrs &= (PAGE_SIZE - 1) & ~PVF_NC; 2117 md->pvh_attrs |= tst_mask | PVF_COLORED; 2118 /* 2119 * Restore DIRTY bit if page is modified 2120 */ 2121 if (md->pvh_attrs & PVF_DMOD) 2122 md->pvh_attrs |= PVF_DIRTY; 2123 PMAPCOUNT(vac_color_restore); 2124 } else { 2125 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2126 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2127 } 2128 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2129 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2130 } else if (!va) { 2131 KASSERT(pmap_is_page_colored_p(md)); 2132 KASSERT(!(md->pvh_attrs & PVF_WRITE) 2133 || (md->pvh_attrs & PVF_DIRTY)); 2134 if (rw_mappings == 0) { 2135 md->pvh_attrs &= ~PVF_WRITE; 2136 if (ro_mappings == 1 2137 && (md->pvh_attrs & PVF_MULTCLR)) { 2138 /* 2139 * If this is the last readonly mapping 2140 * but it doesn't match the current color 2141 * for the page, change the current color 2142 * to match this last readonly mapping. 2143 */ 2144 pv = SLIST_FIRST(&md->pvh_list); 2145 tst_mask = (md->pvh_attrs ^ pv->pv_va) 2146 & arm_cache_prefer_mask; 2147 if (tst_mask) { 2148 md->pvh_attrs ^= tst_mask; 2149 PMAPCOUNT(vac_color_change); 2150 } 2151 } 2152 } 2153 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2154 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2155 return; 2156 } else if (!pmap_is_page_colored_p(md)) { 2157 /* not colored so we just use its color */ 2158 KASSERT(md->pvh_attrs & (PVF_WRITE|PVF_DIRTY)); 2159 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2160 PMAPCOUNT(vac_color_new); 2161 md->pvh_attrs &= PAGE_SIZE - 1; 2162 md->pvh_attrs |= PVF_COLORED 2163 | (va & arm_cache_prefer_mask) 2164 | (rw_mappings > 0 ? PVF_WRITE : 0); 2165 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2166 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2167 return; 2168 } else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) { 2169 bad_alias = false; 2170 if (rw_mappings > 0) { 2171 /* 2172 * We now have writeable mappings and if we have 2173 * readonly mappings in more than once color, we have 2174 * an aliasing problem. Regardless mark the page as 2175 * writeable. 2176 */ 2177 if (md->pvh_attrs & PVF_MULTCLR) { 2178 if (ro_mappings < 2) { 2179 /* 2180 * If we only have less than two 2181 * read-only mappings, just flush the 2182 * non-primary colors from the cache. 2183 */ 2184 pmap_flush_page(md, pa, 2185 PMAP_FLUSH_SECONDARY); 2186 } else { 2187 bad_alias = true; 2188 } 2189 } 2190 md->pvh_attrs |= PVF_WRITE; 2191 } 2192 /* If no conflicting colors, set everything back to cached */ 2193 if (!bad_alias) { 2194 #ifdef DEBUG 2195 if (rw_mappings > 0 2196 || (md->pvh_attrs & PMAP_KMPAGE)) { 2197 tst_mask = md->pvh_attrs & arm_cache_prefer_mask; 2198 SLIST_FOREACH(pv, &md->pvh_list, pv_link) 2199 KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0); 2200 } 2201 #endif 2202 if (SLIST_EMPTY(&md->pvh_list)) 2203 PMAPCOUNT(vac_color_reuse); 2204 else 2205 PMAPCOUNT(vac_color_ok); 2206 2207 /* matching color, just return */ 2208 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2209 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2210 return; 2211 } 2212 KASSERT(SLIST_FIRST(&md->pvh_list) != NULL); 2213 KASSERT(SLIST_NEXT(SLIST_FIRST(&md->pvh_list), pv_link) != NULL); 2214 2215 /* color conflict. evict from cache. */ 2216 2217 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2218 md->pvh_attrs &= ~PVF_COLORED; 2219 md->pvh_attrs |= PVF_NC; 2220 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2221 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2222 PMAPCOUNT(vac_color_erase); 2223 } else if (rw_mappings == 0 2224 && (md->pvh_attrs & PVF_KMPAGE) == 0) { 2225 KASSERT((md->pvh_attrs & PVF_WRITE) == 0); 2226 2227 /* 2228 * If the page has dirty cache lines, clean it. 2229 */ 2230 if (md->pvh_attrs & PVF_DIRTY) 2231 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 2232 2233 /* 2234 * If this is the first remapping (we know that there are no 2235 * writeable mappings), then this is a simple color change. 2236 * Otherwise this is a seconary r/o mapping, which means 2237 * we don't have to do anything. 2238 */ 2239 if (ro_mappings == 1) { 2240 KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0); 2241 md->pvh_attrs &= PAGE_SIZE - 1; 2242 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2243 PMAPCOUNT(vac_color_change); 2244 } else { 2245 PMAPCOUNT(vac_color_blind); 2246 } 2247 md->pvh_attrs |= PVF_MULTCLR; 2248 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2249 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2250 return; 2251 } else { 2252 if (rw_mappings > 0) 2253 md->pvh_attrs |= PVF_WRITE; 2254 2255 /* color conflict. evict from cache. */ 2256 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 2257 2258 /* the list can't be empty because this was a enter/modify */ 2259 pv = SLIST_FIRST(&md->pvh_list); 2260 if ((md->pvh_attrs & PVF_KMPAGE) == 0) { 2261 KASSERT(pv); 2262 /* 2263 * If there's only one mapped page, change color to the 2264 * page's new color and return. Restore the DIRTY bit 2265 * that was erased by pmap_flush_page. 2266 */ 2267 if (SLIST_NEXT(pv, pv_link) == NULL) { 2268 md->pvh_attrs &= PAGE_SIZE - 1; 2269 md->pvh_attrs |= (va & arm_cache_prefer_mask); 2270 if (md->pvh_attrs & PVF_DMOD) 2271 md->pvh_attrs |= PVF_DIRTY; 2272 PMAPCOUNT(vac_color_change); 2273 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2274 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2275 KASSERT(!(md->pvh_attrs & PVF_MULTCLR)); 2276 return; 2277 } 2278 } 2279 bad_alias = true; 2280 md->pvh_attrs &= ~PVF_COLORED; 2281 md->pvh_attrs |= PVF_NC; 2282 PMAPCOUNT(vac_color_erase); 2283 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 2284 } 2285 2286 fixup: 2287 KASSERT((rw_mappings == 0) == !(md->pvh_attrs & PVF_WRITE)); 2288 2289 /* 2290 * Turn cacheing on/off for all pages. 2291 */ 2292 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2293 struct l2_bucket * const l2b = pmap_get_l2_bucket(pv->pv_pmap, 2294 pv->pv_va); 2295 KASSERTMSG(l2b != NULL, "%#lx", va); 2296 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2297 const pt_entry_t opte = *ptep; 2298 pt_entry_t npte = opte & ~L2_S_CACHE_MASK; 2299 if (bad_alias) { 2300 pv->pv_flags |= PVF_NC; 2301 } else { 2302 pv->pv_flags &= ~PVF_NC; 2303 npte |= pte_l2_s_cache_mode; 2304 } 2305 2306 if (opte == npte) /* only update is there's a change */ 2307 continue; 2308 2309 if (l2pte_valid_p(opte)) { 2310 pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags); 2311 } 2312 2313 l2pte_set(ptep, npte, opte); 2314 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 2315 } 2316 #endif /* !ARM_MMU_EXTENDED */ 2317 } 2318 #endif /* PMAP_CACHE_VIPT */ 2319 2320 2321 /* 2322 * Modify pte bits for all ptes corresponding to the given physical address. 2323 * We use `maskbits' rather than `clearbits' because we're always passing 2324 * constants and the latter would require an extra inversion at run-time. 2325 */ 2326 static void 2327 pmap_clearbit(struct vm_page_md *md, paddr_t pa, u_int maskbits) 2328 { 2329 struct pv_entry *pv; 2330 #ifdef PMAP_CACHE_VIPT 2331 const bool want_syncicache = PV_IS_EXEC_P(md->pvh_attrs); 2332 bool need_syncicache = false; 2333 #ifndef ARM_MMU_EXTENDED 2334 bool need_vac_me_harder = false; 2335 #endif 2336 #endif /* PMAP_CACHE_VIPT */ 2337 2338 UVMHIST_FUNC(__func__); 2339 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx maskbits %#jx", 2340 (uintptr_t)md, pa, maskbits, 0); 2341 2342 #ifdef PMAP_CACHE_VIPT 2343 /* 2344 * If we might want to sync the I-cache and we've modified it, 2345 * then we know we definitely need to sync or discard it. 2346 */ 2347 if (want_syncicache) { 2348 if (md->pvh_attrs & PVF_MOD) { 2349 need_syncicache = true; 2350 } 2351 } 2352 #endif 2353 KASSERT(pmap_page_locked_p(md)); 2354 2355 /* 2356 * Clear saved attributes (modify, reference) 2357 */ 2358 md->pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 2359 2360 if (SLIST_EMPTY(&md->pvh_list)) { 2361 #if defined(PMAP_CACHE_VIPT) 2362 if (need_syncicache) { 2363 /* 2364 * No one has it mapped, so just discard it. The next 2365 * exec remapping will cause it to be synced. 2366 */ 2367 md->pvh_attrs &= ~PVF_EXEC; 2368 PMAPCOUNT(exec_discarded_clearbit); 2369 } 2370 #endif 2371 return; 2372 } 2373 2374 /* 2375 * Loop over all current mappings setting/clearing as appropriate 2376 */ 2377 for (pv = SLIST_FIRST(&md->pvh_list); pv != NULL;) { 2378 pmap_t pm = pv->pv_pmap; 2379 const vaddr_t va = pv->pv_va; 2380 const u_int oflags = pv->pv_flags; 2381 #ifndef ARM_MMU_EXTENDED 2382 /* 2383 * Kernel entries are unmanaged and as such not to be changed. 2384 */ 2385 if (PV_IS_KENTRY_P(oflags)) { 2386 pv = SLIST_NEXT(pv, pv_link); 2387 continue; 2388 } 2389 #endif 2390 2391 /* 2392 * Try to get a hold on the pmap's lock. We must do this 2393 * while still holding the page locked, to know that the 2394 * page is still associated with the pmap and the mapping is 2395 * in place. If a hold can't be had, unlock and wait for 2396 * the pmap's lock to become available and retry. The pmap 2397 * must be ref'd over this dance to stop it disappearing 2398 * behind us. 2399 */ 2400 if (!mutex_tryenter(&pm->pm_lock)) { 2401 pmap_reference(pm); 2402 pmap_release_page_lock(md); 2403 pmap_acquire_pmap_lock(pm); 2404 /* nothing, just wait for it */ 2405 pmap_release_pmap_lock(pm); 2406 pmap_destroy(pm); 2407 /* Restart from the beginning. */ 2408 pmap_acquire_page_lock(md); 2409 pv = SLIST_FIRST(&md->pvh_list); 2410 continue; 2411 } 2412 pv->pv_flags &= ~maskbits; 2413 2414 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, va); 2415 KASSERTMSG(l2b != NULL, "%#lx", va); 2416 2417 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 2418 const pt_entry_t opte = *ptep; 2419 pt_entry_t npte = opte; 2420 2421 #if defined(ARM_MMU_EXTENDED) 2422 if ((maskbits & PVF_EXEC) != 0 && l2pte_valid_p(opte)) { 2423 KASSERT((opte & L2_TYPE_S) != 0); 2424 npte |= L2_XS_XN; 2425 } 2426 2427 KASSERT((opte & L2_XS_nG) == (pm == pmap_kernel() ? 0 : L2_XS_nG)); 2428 #endif 2429 2430 UVMHIST_LOG(maphist, "pv %#jx pm %#jx va %#jx flag %#jx", 2431 (uintptr_t)pv, (uintptr_t)pm, va, oflags); 2432 2433 if (maskbits & (PVF_WRITE|PVF_MOD)) { 2434 #ifdef PMAP_CACHE_VIVT 2435 if ((oflags & PVF_NC)) { 2436 /* 2437 * Entry is not cacheable: 2438 * 2439 * Don't turn caching on again if this is a 2440 * modified emulation. This would be 2441 * inconsitent with the settings created by 2442 * pmap_vac_me_harder(). Otherwise, it's safe 2443 * to re-enable cacheing. 2444 * 2445 * There's no need to call pmap_vac_me_harder() 2446 * here: all pages are losing their write 2447 * permission. 2448 */ 2449 if (maskbits & PVF_WRITE) { 2450 npte |= pte_l2_s_cache_mode; 2451 pv->pv_flags &= ~PVF_NC; 2452 } 2453 } else if (l2pte_writable_p(opte)) { 2454 /* 2455 * Entry is writable/cacheable: check if pmap 2456 * is current if it is flush it, otherwise it 2457 * won't be in the cache 2458 */ 2459 pmap_cache_wbinv_page(pm, va, 2460 (maskbits & PVF_REF) != 0, 2461 oflags|PVF_WRITE); 2462 } 2463 #endif 2464 2465 /* make the pte read only */ 2466 npte = l2pte_set_readonly(npte); 2467 2468 if ((maskbits & oflags & PVF_WRITE)) { 2469 /* 2470 * Keep alias accounting up to date 2471 */ 2472 if (pm == pmap_kernel()) { 2473 md->krw_mappings--; 2474 md->kro_mappings++; 2475 } else { 2476 md->urw_mappings--; 2477 md->uro_mappings++; 2478 } 2479 #ifdef PMAP_CACHE_VIPT 2480 if (arm_cache_prefer_mask != 0) { 2481 if (md->urw_mappings + md->krw_mappings == 0) { 2482 md->pvh_attrs &= ~PVF_WRITE; 2483 } else { 2484 PMAP_VALIDATE_MD_PAGE(md); 2485 } 2486 } 2487 if (want_syncicache) 2488 need_syncicache = true; 2489 #ifndef ARM_MMU_EXTENDED 2490 need_vac_me_harder = true; 2491 #endif 2492 #endif /* PMAP_CACHE_VIPT */ 2493 } 2494 } 2495 2496 if (maskbits & PVF_REF) { 2497 if (true 2498 #ifndef ARM_MMU_EXTENDED 2499 && (oflags & PVF_NC) == 0 2500 #endif 2501 && (maskbits & (PVF_WRITE|PVF_MOD)) == 0 2502 && l2pte_valid_p(npte)) { 2503 #ifdef PMAP_CACHE_VIVT 2504 /* 2505 * Check npte here; we may have already 2506 * done the wbinv above, and the validity 2507 * of the PTE is the same for opte and 2508 * npte. 2509 */ 2510 pmap_cache_wbinv_page(pm, va, true, oflags); 2511 #endif 2512 } 2513 2514 /* 2515 * Make the PTE invalid so that we will take a 2516 * page fault the next time the mapping is 2517 * referenced. 2518 */ 2519 npte &= ~L2_TYPE_MASK; 2520 npte |= L2_TYPE_INV; 2521 } 2522 2523 if (npte != opte) { 2524 l2pte_reset(ptep); 2525 PTE_SYNC(ptep); 2526 2527 /* Flush the TLB entry if a current pmap. */ 2528 pmap_tlb_flush_SE(pm, va, oflags); 2529 2530 l2pte_set(ptep, npte, 0); 2531 PTE_SYNC(ptep); 2532 } 2533 2534 pmap_release_pmap_lock(pm); 2535 2536 UVMHIST_LOG(maphist, "pm %#jx va %#jx opte %#jx npte %#jx", 2537 (uintptr_t)pm, va, opte, npte); 2538 2539 /* Move to next entry. */ 2540 pv = SLIST_NEXT(pv, pv_link); 2541 } 2542 2543 #if defined(PMAP_CACHE_VIPT) 2544 /* 2545 * If we need to sync the I-cache and we haven't done it yet, do it. 2546 */ 2547 if (need_syncicache) { 2548 pmap_syncicache_page(md, pa); 2549 PMAPCOUNT(exec_synced_clearbit); 2550 } 2551 #ifndef ARM_MMU_EXTENDED 2552 /* 2553 * If we are changing this to read-only, we need to call vac_me_harder 2554 * so we can change all the read-only pages to cacheable. We pretend 2555 * this as a page deletion. 2556 */ 2557 if (need_vac_me_harder) { 2558 if (md->pvh_attrs & PVF_NC) 2559 pmap_vac_me_harder(md, pa, NULL, 0); 2560 } 2561 #endif /* !ARM_MMU_EXTENDED */ 2562 #endif /* PMAP_CACHE_VIPT */ 2563 } 2564 2565 /* 2566 * pmap_clean_page() 2567 * 2568 * This is a local function used to work out the best strategy to clean 2569 * a single page referenced by its entry in the PV table. It's used by 2570 * pmap_copy_page, pmap_zero_page and maybe some others later on. 2571 * 2572 * Its policy is effectively: 2573 * o If there are no mappings, we don't bother doing anything with the cache. 2574 * o If there is one mapping, we clean just that page. 2575 * o If there are multiple mappings, we clean the entire cache. 2576 * 2577 * So that some functions can be further optimised, it returns 0 if it didn't 2578 * clean the entire cache, or 1 if it did. 2579 * 2580 * XXX One bug in this routine is that if the pv_entry has a single page 2581 * mapped at 0x00000000 a whole cache clean will be performed rather than 2582 * just the 1 page. Since this should not occur in everyday use and if it does 2583 * it will just result in not the most efficient clean for the page. 2584 */ 2585 #ifdef PMAP_CACHE_VIVT 2586 static bool 2587 pmap_clean_page(struct vm_page_md *md, bool is_src) 2588 { 2589 struct pv_entry *pv; 2590 pmap_t pm_to_clean = NULL; 2591 bool cache_needs_cleaning = false; 2592 vaddr_t page_to_clean = 0; 2593 u_int flags = 0; 2594 2595 /* 2596 * Since we flush the cache each time we change to a different 2597 * user vmspace, we only need to flush the page if it is in the 2598 * current pmap. 2599 */ 2600 KASSERT(pmap_page_locked_p(md)); 2601 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 2602 if (pmap_is_current(pv->pv_pmap)) { 2603 flags |= pv->pv_flags; 2604 /* 2605 * The page is mapped non-cacheable in 2606 * this map. No need to flush the cache. 2607 */ 2608 if (pv->pv_flags & PVF_NC) { 2609 #ifdef DIAGNOSTIC 2610 KASSERT(!cache_needs_cleaning); 2611 #endif 2612 break; 2613 } else if (is_src && (pv->pv_flags & PVF_WRITE) == 0) 2614 continue; 2615 if (cache_needs_cleaning) { 2616 page_to_clean = 0; 2617 break; 2618 } else { 2619 page_to_clean = pv->pv_va; 2620 pm_to_clean = pv->pv_pmap; 2621 } 2622 cache_needs_cleaning = true; 2623 } 2624 } 2625 2626 if (page_to_clean) { 2627 pmap_cache_wbinv_page(pm_to_clean, page_to_clean, 2628 !is_src, flags | PVF_REF); 2629 } else if (cache_needs_cleaning) { 2630 pmap_t const pm = curproc->p_vmspace->vm_map.pmap; 2631 2632 pmap_cache_wbinv_all(pm, flags); 2633 return true; 2634 } 2635 return false; 2636 } 2637 #endif 2638 2639 #ifdef PMAP_CACHE_VIPT 2640 /* 2641 * Sync a page with the I-cache. Since this is a VIPT, we must pick the 2642 * right cache alias to make sure we flush the right stuff. 2643 */ 2644 void 2645 pmap_syncicache_page(struct vm_page_md *md, paddr_t pa) 2646 { 2647 pmap_t kpm = pmap_kernel(); 2648 const size_t way_size = arm_pcache.icache_type == CACHE_TYPE_PIPT 2649 ? PAGE_SIZE 2650 : arm_pcache.icache_way_size; 2651 2652 UVMHIST_FUNC(__func__); 2653 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx (attrs=%#jx)", 2654 (uintptr_t)md, pa, md->pvh_attrs, 0); 2655 2656 /* 2657 * No need to clean the page if it's non-cached. 2658 */ 2659 #ifndef ARM_MMU_EXTENDED 2660 if (md->pvh_attrs & PVF_NC) 2661 return; 2662 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED); 2663 #endif 2664 2665 pt_entry_t * const ptep = cpu_cdst_pte(0); 2666 const vaddr_t dstp = cpu_cdstp(0); 2667 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 2668 if (way_size <= PAGE_SIZE) { 2669 bool ok = false; 2670 vaddr_t vdstp = pmap_direct_mapped_phys(pa, &ok, dstp); 2671 if (ok) { 2672 cpu_icache_sync_range(vdstp, way_size); 2673 return; 2674 } 2675 } 2676 #endif 2677 2678 /* 2679 * We don't worry about the color of the exec page, we map the 2680 * same page to pages in the way and then do the icache_sync on 2681 * the entire way making sure we are cleaned. 2682 */ 2683 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 2684 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE); 2685 2686 for (size_t i = 0, j = 0; i < way_size; 2687 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2688 l2pte_reset(ptep + j); 2689 PTE_SYNC(ptep + j); 2690 2691 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2692 /* 2693 * Set up a PTE with to flush these cache lines. 2694 */ 2695 l2pte_set(ptep + j, npte, 0); 2696 } 2697 PTE_SYNC_RANGE(ptep, way_size / L2_S_SIZE); 2698 2699 /* 2700 * Flush it. 2701 */ 2702 cpu_icache_sync_range(dstp, way_size); 2703 2704 for (size_t i = 0, j = 0; i < way_size; 2705 i += PAGE_SIZE, j += PAGE_SIZE / L2_S_SIZE) { 2706 /* 2707 * Unmap the page(s). 2708 */ 2709 l2pte_reset(ptep + j); 2710 PTE_SYNC(ptep + j); 2711 2712 pmap_tlb_flush_SE(kpm, dstp + i, PVF_REF | PVF_EXEC); 2713 } 2714 2715 md->pvh_attrs |= PVF_EXEC; 2716 PMAPCOUNT(exec_synced); 2717 } 2718 2719 #ifndef ARM_MMU_EXTENDED 2720 void 2721 pmap_flush_page(struct vm_page_md *md, paddr_t pa, enum pmap_flush_op flush) 2722 { 2723 vsize_t va_offset, end_va; 2724 bool wbinv_p; 2725 2726 if (arm_cache_prefer_mask == 0) 2727 return; 2728 2729 UVMHIST_FUNC(__func__); 2730 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx op %#jx", 2731 (uintptr_t)md, pa, op, 0); 2732 2733 switch (flush) { 2734 case PMAP_FLUSH_PRIMARY: 2735 if (md->pvh_attrs & PVF_MULTCLR) { 2736 va_offset = 0; 2737 end_va = arm_cache_prefer_mask; 2738 md->pvh_attrs &= ~PVF_MULTCLR; 2739 PMAPCOUNT(vac_flush_lots); 2740 } else { 2741 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2742 end_va = va_offset; 2743 PMAPCOUNT(vac_flush_one); 2744 } 2745 /* 2746 * Mark that the page is no longer dirty. 2747 */ 2748 md->pvh_attrs &= ~PVF_DIRTY; 2749 wbinv_p = true; 2750 break; 2751 case PMAP_FLUSH_SECONDARY: 2752 va_offset = 0; 2753 end_va = arm_cache_prefer_mask; 2754 wbinv_p = true; 2755 md->pvh_attrs &= ~PVF_MULTCLR; 2756 PMAPCOUNT(vac_flush_lots); 2757 break; 2758 case PMAP_CLEAN_PRIMARY: 2759 va_offset = md->pvh_attrs & arm_cache_prefer_mask; 2760 end_va = va_offset; 2761 wbinv_p = false; 2762 /* 2763 * Mark that the page is no longer dirty. 2764 */ 2765 if ((md->pvh_attrs & PVF_DMOD) == 0) 2766 md->pvh_attrs &= ~PVF_DIRTY; 2767 PMAPCOUNT(vac_clean_one); 2768 break; 2769 default: 2770 return; 2771 } 2772 2773 KASSERT(!(md->pvh_attrs & PVF_NC)); 2774 2775 UVMHIST_LOG(maphist, "md %#jx (attrs=%#jx)", (uintptr_t)md, 2776 md->pvh_attrs, 0, 0); 2777 2778 const size_t scache_line_size = arm_scache.dcache_line_size; 2779 2780 for (; va_offset <= end_va; va_offset += PAGE_SIZE) { 2781 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 2782 const vaddr_t dstp = cpu_cdstp(va_offset); 2783 const pt_entry_t opte = *ptep; 2784 2785 if (flush == PMAP_FLUSH_SECONDARY 2786 && va_offset == (md->pvh_attrs & arm_cache_prefer_mask)) 2787 continue; 2788 2789 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2790 /* 2791 * Set up a PTE with the right coloring to flush 2792 * existing cache entries. 2793 */ 2794 const pt_entry_t npte = L2_S_PROTO 2795 | pa 2796 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ|VM_PROT_WRITE) 2797 | pte_l2_s_cache_mode; 2798 l2pte_set(ptep, npte, opte); 2799 PTE_SYNC(ptep); 2800 2801 /* 2802 * Flush it. Make sure to flush secondary cache too since 2803 * bus_dma will ignore uncached pages. 2804 */ 2805 if (scache_line_size != 0) { 2806 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2807 if (wbinv_p) { 2808 cpu_sdcache_wbinv_range(dstp, pa, PAGE_SIZE); 2809 cpu_dcache_inv_range(dstp, PAGE_SIZE); 2810 } else { 2811 cpu_sdcache_wb_range(dstp, pa, PAGE_SIZE); 2812 } 2813 } else { 2814 if (wbinv_p) { 2815 cpu_dcache_wbinv_range(dstp, PAGE_SIZE); 2816 } else { 2817 cpu_dcache_wb_range(dstp, PAGE_SIZE); 2818 } 2819 } 2820 2821 /* 2822 * Restore the page table entry since we might have interrupted 2823 * pmap_zero_page or pmap_copy_page which was already using 2824 * this pte. 2825 */ 2826 if (opte) { 2827 l2pte_set(ptep, opte, npte); 2828 } else { 2829 l2pte_reset(ptep); 2830 } 2831 PTE_SYNC(ptep); 2832 pmap_tlb_flush_SE(pmap_kernel(), dstp, PVF_REF | PVF_EXEC); 2833 } 2834 } 2835 #endif /* ARM_MMU_EXTENDED */ 2836 #endif /* PMAP_CACHE_VIPT */ 2837 2838 /* 2839 * Routine: pmap_page_remove 2840 * Function: 2841 * Removes this physical page from 2842 * all physical maps in which it resides. 2843 * Reflects back modify bits to the pager. 2844 */ 2845 static void 2846 pmap_page_remove(struct vm_page_md *md, paddr_t pa) 2847 { 2848 struct l2_bucket *l2b; 2849 struct pv_entry *pv; 2850 pt_entry_t *ptep; 2851 #ifndef ARM_MMU_EXTENDED 2852 bool flush = false; 2853 #endif 2854 u_int flags = 0; 2855 2856 UVMHIST_FUNC(__func__); 2857 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx", (uintptr_t)md, pa, 0, 0); 2858 2859 kpreempt_disable(); 2860 pmap_acquire_page_lock(md); 2861 struct pv_entry **pvp = &SLIST_FIRST(&md->pvh_list); 2862 if (*pvp == NULL) { 2863 #ifdef PMAP_CACHE_VIPT 2864 /* 2865 * We *know* the page contents are about to be replaced. 2866 * Discard the exec contents 2867 */ 2868 if (PV_IS_EXEC_P(md->pvh_attrs)) 2869 PMAPCOUNT(exec_discarded_page_protect); 2870 md->pvh_attrs &= ~PVF_EXEC; 2871 PMAP_VALIDATE_MD_PAGE(md); 2872 #endif 2873 pmap_release_page_lock(md); 2874 kpreempt_enable(); 2875 2876 return; 2877 } 2878 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 2879 KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md)); 2880 #endif 2881 2882 /* 2883 * Clear alias counts 2884 */ 2885 #ifdef PMAP_CACHE_VIVT 2886 md->k_mappings = 0; 2887 #endif 2888 md->urw_mappings = md->uro_mappings = 0; 2889 2890 #ifdef PMAP_CACHE_VIVT 2891 pmap_clean_page(md, false); 2892 #endif 2893 2894 for (pv = *pvp; pv != NULL;) { 2895 pmap_t pm = pv->pv_pmap; 2896 #ifndef ARM_MMU_EXTENDED 2897 if (flush == false && pmap_is_current(pm)) 2898 flush = true; 2899 #endif 2900 2901 #ifdef PMAP_CACHE_VIPT 2902 if (pm == pmap_kernel() && PV_IS_KENTRY_P(pv->pv_flags)) { 2903 /* If this was unmanaged mapping, it must be ignored. */ 2904 pvp = &SLIST_NEXT(pv, pv_link); 2905 pv = *pvp; 2906 continue; 2907 } 2908 #endif 2909 2910 /* 2911 * Try to get a hold on the pmap's lock. We must do this 2912 * while still holding the page locked, to know that the 2913 * page is still associated with the pmap and the mapping is 2914 * in place. If a hold can't be had, unlock and wait for 2915 * the pmap's lock to become available and retry. The pmap 2916 * must be ref'd over this dance to stop it disappearing 2917 * behind us. 2918 */ 2919 if (!mutex_tryenter(&pm->pm_lock)) { 2920 pmap_reference(pm); 2921 pmap_release_page_lock(md); 2922 pmap_acquire_pmap_lock(pm); 2923 /* nothing, just wait for it */ 2924 pmap_release_pmap_lock(pm); 2925 pmap_destroy(pm); 2926 /* Restart from the beginning. */ 2927 pmap_acquire_page_lock(md); 2928 pvp = &SLIST_FIRST(&md->pvh_list); 2929 pv = *pvp; 2930 continue; 2931 } 2932 2933 if (pm == pmap_kernel()) { 2934 #ifdef PMAP_CACHE_VIPT 2935 if (pv->pv_flags & PVF_WRITE) 2936 md->krw_mappings--; 2937 else 2938 md->kro_mappings--; 2939 #endif 2940 PMAPCOUNT(kernel_unmappings); 2941 } 2942 *pvp = SLIST_NEXT(pv, pv_link); /* remove from list */ 2943 PMAPCOUNT(unmappings); 2944 2945 pmap_release_page_lock(md); 2946 2947 l2b = pmap_get_l2_bucket(pm, pv->pv_va); 2948 KASSERTMSG(l2b != NULL, "%#lx", pv->pv_va); 2949 2950 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2951 2952 /* 2953 * Update statistics 2954 */ 2955 --pm->pm_stats.resident_count; 2956 2957 /* Wired bit */ 2958 if (pv->pv_flags & PVF_WIRED) 2959 --pm->pm_stats.wired_count; 2960 2961 flags |= pv->pv_flags; 2962 2963 /* 2964 * Invalidate the PTEs. 2965 */ 2966 l2pte_reset(ptep); 2967 PTE_SYNC_CURRENT(pm, ptep); 2968 2969 #ifdef ARM_MMU_EXTENDED 2970 pmap_tlb_invalidate_addr(pm, pv->pv_va); 2971 #endif 2972 2973 pmap_free_l2_bucket(pm, l2b, PAGE_SIZE / L2_S_SIZE); 2974 2975 pmap_release_pmap_lock(pm); 2976 2977 pool_put(&pmap_pv_pool, pv); 2978 pmap_acquire_page_lock(md); 2979 2980 /* 2981 * Restart at the beginning of the list. 2982 */ 2983 pvp = &SLIST_FIRST(&md->pvh_list); 2984 pv = *pvp; 2985 } 2986 /* 2987 * if we reach the end of the list and there are still mappings, they 2988 * might be able to be cached now. And they must be kernel mappings. 2989 */ 2990 if (!SLIST_EMPTY(&md->pvh_list)) { 2991 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 2992 } 2993 2994 #ifdef PMAP_CACHE_VIPT 2995 /* 2996 * Its EXEC cache is now gone. 2997 */ 2998 if (PV_IS_EXEC_P(md->pvh_attrs)) 2999 PMAPCOUNT(exec_discarded_page_protect); 3000 md->pvh_attrs &= ~PVF_EXEC; 3001 KASSERT(md->urw_mappings == 0); 3002 KASSERT(md->uro_mappings == 0); 3003 #ifndef ARM_MMU_EXTENDED 3004 if (arm_cache_prefer_mask != 0) { 3005 if (md->krw_mappings == 0) 3006 md->pvh_attrs &= ~PVF_WRITE; 3007 PMAP_VALIDATE_MD_PAGE(md); 3008 } 3009 #endif /* ARM_MMU_EXTENDED */ 3010 #endif /* PMAP_CACHE_VIPT */ 3011 pmap_release_page_lock(md); 3012 3013 #ifndef ARM_MMU_EXTENDED 3014 if (flush) { 3015 /* 3016 * Note: We can't use pmap_tlb_flush{I,D}() here since that 3017 * would need a subsequent call to pmap_update() to ensure 3018 * curpm->pm_cstate.cs_all is reset. Our callers are not 3019 * required to do that (see pmap(9)), so we can't modify 3020 * the current pmap's state. 3021 */ 3022 if (PV_BEEN_EXECD(flags)) 3023 cpu_tlb_flushID(); 3024 else 3025 cpu_tlb_flushD(); 3026 } 3027 cpu_cpwait(); 3028 #endif /* ARM_MMU_EXTENDED */ 3029 3030 kpreempt_enable(); 3031 } 3032 3033 /* 3034 * pmap_t pmap_create(void) 3035 * 3036 * Create a new pmap structure from scratch. 3037 */ 3038 pmap_t 3039 pmap_create(void) 3040 { 3041 pmap_t pm; 3042 3043 pm = pool_cache_get(&pmap_cache, PR_WAITOK); 3044 3045 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 3046 3047 pm->pm_refs = 1; 3048 pm->pm_stats.wired_count = 0; 3049 pm->pm_stats.resident_count = 1; 3050 #ifdef ARM_MMU_EXTENDED 3051 #ifdef MULTIPROCESSOR 3052 kcpuset_create(&pm->pm_active, true); 3053 kcpuset_create(&pm->pm_onproc, true); 3054 #endif 3055 #else 3056 pm->pm_cstate.cs_all = 0; 3057 #endif 3058 pmap_alloc_l1(pm); 3059 3060 /* 3061 * Note: The pool cache ensures that the pm_l2[] array is already 3062 * initialised to zero. 3063 */ 3064 3065 pmap_pinit(pm); 3066 3067 return pm; 3068 } 3069 3070 u_int 3071 arm32_mmap_flags(paddr_t pa) 3072 { 3073 /* 3074 * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff 3075 * and we're using the upper bits in page numbers to pass flags around 3076 * so we might as well use the same bits 3077 */ 3078 return (u_int)pa & PMAP_MD_MASK; 3079 } 3080 /* 3081 * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, 3082 * u_int flags) 3083 * 3084 * Insert the given physical page (p) at 3085 * the specified virtual address (v) in the 3086 * target physical map with the protection requested. 3087 * 3088 * NB: This is the only routine which MAY NOT lazy-evaluate 3089 * or lose information. That is, this routine must actually 3090 * insert this page into the given map NOW. 3091 */ 3092 int 3093 pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3094 { 3095 struct l2_bucket *l2b; 3096 struct vm_page *pg, *opg; 3097 u_int nflags; 3098 u_int oflags; 3099 const bool kpm_p = pm == pmap_kernel(); 3100 #if defined(EFI_RUNTIME) 3101 const bool efirt_p = pm == pmap_efirt(); 3102 #else 3103 const bool efirt_p = false; 3104 #endif 3105 #ifdef ARM_HAS_VBAR 3106 const bool vector_page_p = false; 3107 #else 3108 const bool vector_page_p = (va == vector_page); 3109 #endif 3110 struct pmap_page *pp = pmap_pv_tracked(pa); 3111 struct pv_entry *new_pv = NULL; 3112 struct pv_entry *old_pv = NULL; 3113 int error = 0; 3114 3115 UVMHIST_FUNC(__func__); 3116 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx pa %#jx prot %#jx", 3117 (uintptr_t)pm, va, pa, prot); 3118 UVMHIST_LOG(maphist, " flag %#jx", flags, 0, 0, 0); 3119 3120 KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0); 3121 KDASSERT(((va | pa) & PGOFSET) == 0); 3122 3123 /* 3124 * Get a pointer to the page. Later on in this function, we 3125 * test for a managed page by checking pg != NULL. 3126 */ 3127 pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL; 3128 /* 3129 * if we may need a new pv entry allocate if now, as we can't do it 3130 * with the kernel_pmap locked 3131 */ 3132 if (pg || pp) 3133 new_pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3134 3135 nflags = 0; 3136 if (prot & VM_PROT_WRITE) 3137 nflags |= PVF_WRITE; 3138 if (prot & VM_PROT_EXECUTE) 3139 nflags |= PVF_EXEC; 3140 if (flags & PMAP_WIRED) 3141 nflags |= PVF_WIRED; 3142 3143 kpreempt_disable(); 3144 pmap_acquire_pmap_lock(pm); 3145 3146 /* 3147 * Fetch the L2 bucket which maps this page, allocating one if 3148 * necessary for user pmaps. 3149 */ 3150 if (kpm_p) { 3151 l2b = pmap_get_l2_bucket(pm, va); 3152 } else { 3153 l2b = pmap_alloc_l2_bucket(pm, va); 3154 } 3155 if (l2b == NULL) { 3156 if (flags & PMAP_CANFAIL) { 3157 pmap_release_pmap_lock(pm); 3158 kpreempt_enable(); 3159 3160 error = ENOMEM; 3161 goto free_pv; 3162 } 3163 panic("pmap_enter: failed to allocate L2 bucket"); 3164 } 3165 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(va)]; 3166 const pt_entry_t opte = *ptep; 3167 pt_entry_t npte = pa; 3168 oflags = 0; 3169 3170 if (opte) { 3171 /* 3172 * There is already a mapping at this address. 3173 * If the physical address is different, lookup the 3174 * vm_page. 3175 */ 3176 if (l2pte_pa(opte) != pa) { 3177 KASSERT(!pmap_pv_tracked(pa)); 3178 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3179 } else 3180 opg = pg; 3181 } else 3182 opg = NULL; 3183 3184 if (pg || pp) { 3185 KASSERT((pg != NULL) != (pp != NULL)); 3186 struct vm_page_md *md = (pg != NULL) ? VM_PAGE_TO_MD(pg) : 3187 PMAP_PAGE_TO_MD(pp); 3188 3189 UVMHIST_LOG(maphist, " pg %#jx pp %#jx pvh_attrs %#jx " 3190 "nflags %#jx", (uintptr_t)pg, (uintptr_t)pp, 3191 md->pvh_attrs, nflags); 3192 3193 /* 3194 * This is to be a managed mapping. 3195 */ 3196 pmap_acquire_page_lock(md); 3197 if ((flags & VM_PROT_ALL) || (md->pvh_attrs & PVF_REF)) { 3198 /* 3199 * - The access type indicates that we don't need 3200 * to do referenced emulation. 3201 * OR 3202 * - The physical page has already been referenced 3203 * so no need to re-do referenced emulation here. 3204 */ 3205 npte |= l2pte_set_readonly(L2_S_PROTO); 3206 3207 nflags |= PVF_REF; 3208 3209 if ((prot & VM_PROT_WRITE) != 0 && 3210 ((flags & VM_PROT_WRITE) != 0 || 3211 (md->pvh_attrs & PVF_MOD) != 0)) { 3212 /* 3213 * This is a writable mapping, and the 3214 * page's mod state indicates it has 3215 * already been modified. Make it 3216 * writable from the outset. 3217 */ 3218 npte = l2pte_set_writable(npte); 3219 nflags |= PVF_MOD; 3220 } 3221 3222 #ifdef ARM_MMU_EXTENDED 3223 /* 3224 * If the page has been cleaned, then the pvh_attrs 3225 * will have PVF_EXEC set, so mark it execute so we 3226 * don't get an access fault when trying to execute 3227 * from it. 3228 */ 3229 if (md->pvh_attrs & nflags & PVF_EXEC) { 3230 npte &= ~L2_XS_XN; 3231 } 3232 #endif 3233 } else { 3234 /* 3235 * Need to do page referenced emulation. 3236 */ 3237 npte |= L2_TYPE_INV; 3238 } 3239 3240 if (flags & ARM32_MMAP_WRITECOMBINE) { 3241 npte |= pte_l2_s_wc_mode; 3242 } else 3243 npte |= pte_l2_s_cache_mode; 3244 3245 if (pg != NULL && pg == opg) { 3246 /* 3247 * We're changing the attrs of an existing mapping. 3248 */ 3249 oflags = pmap_modify_pv(md, pa, pm, va, 3250 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3251 PVF_MOD | PVF_REF, nflags); 3252 3253 #ifdef PMAP_CACHE_VIVT 3254 /* 3255 * We may need to flush the cache if we're 3256 * doing rw-ro... 3257 */ 3258 if (pm->pm_cstate.cs_cache_d && 3259 (oflags & PVF_NC) == 0 && 3260 l2pte_writable_p(opte) && 3261 (prot & VM_PROT_WRITE) == 0) 3262 cpu_dcache_wb_range(va, PAGE_SIZE); 3263 #endif 3264 } else { 3265 struct pv_entry *pv; 3266 /* 3267 * New mapping, or changing the backing page 3268 * of an existing mapping. 3269 */ 3270 if (opg) { 3271 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3272 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3273 3274 /* 3275 * Replacing an existing mapping with a new one. 3276 * It is part of our managed memory so we 3277 * must remove it from the PV list 3278 */ 3279 pv = pmap_remove_pv(omd, opa, pm, va); 3280 pmap_vac_me_harder(omd, opa, pm, 0); 3281 oflags = pv->pv_flags; 3282 3283 #ifdef PMAP_CACHE_VIVT 3284 /* 3285 * If the old mapping was valid (ref/mod 3286 * emulation creates 'invalid' mappings 3287 * initially) then make sure to frob 3288 * the cache. 3289 */ 3290 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3291 pmap_cache_wbinv_page(pm, va, true, 3292 oflags); 3293 } 3294 #endif 3295 } else { 3296 pv = new_pv; 3297 new_pv = NULL; 3298 if (pv == NULL) { 3299 pmap_release_page_lock(md); 3300 pmap_release_pmap_lock(pm); 3301 if ((flags & PMAP_CANFAIL) == 0) 3302 panic("pmap_enter: " 3303 "no pv entries"); 3304 3305 pmap_free_l2_bucket(pm, l2b, 0); 3306 UVMHIST_LOG(maphist, " <-- done (ENOMEM)", 3307 0, 0, 0, 0); 3308 kpreempt_enable(); 3309 3310 return ENOMEM; 3311 } 3312 } 3313 3314 pmap_enter_pv(md, pa, pv, pm, va, nflags); 3315 } 3316 pmap_release_page_lock(md); 3317 } else { 3318 /* 3319 * We're mapping an unmanaged page. 3320 * These are always readable, and possibly writable, from 3321 * the get go as we don't need to track ref/mod status. 3322 */ 3323 npte |= l2pte_set_readonly(L2_S_PROTO); 3324 if (prot & VM_PROT_WRITE) 3325 npte = l2pte_set_writable(npte); 3326 3327 if (efirt_p) { 3328 if (prot & VM_PROT_EXECUTE) { 3329 npte &= ~L2_XS_XN; /* and executable */ 3330 } 3331 } 3332 3333 /* 3334 * Make sure the vector table is mapped cacheable 3335 */ 3336 if ((vector_page_p && !kpm_p) 3337 || (flags & ARM32_MMAP_CACHEABLE)) { 3338 npte |= pte_l2_s_cache_mode; 3339 #ifdef ARM_MMU_EXTENDED 3340 npte &= ~L2_XS_XN; /* and executable */ 3341 #endif 3342 } else if (flags & ARM32_MMAP_WRITECOMBINE) { 3343 npte |= pte_l2_s_wc_mode; 3344 } 3345 if (opg) { 3346 /* 3347 * Looks like there's an existing 'managed' mapping 3348 * at this address. 3349 */ 3350 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3351 paddr_t opa = VM_PAGE_TO_PHYS(opg); 3352 3353 pmap_acquire_page_lock(omd); 3354 old_pv = pmap_remove_pv(omd, opa, pm, va); 3355 pmap_vac_me_harder(omd, opa, pm, 0); 3356 oflags = old_pv->pv_flags; 3357 pmap_release_page_lock(omd); 3358 3359 #ifdef PMAP_CACHE_VIVT 3360 if (!(oflags & PVF_NC) && l2pte_valid_p(opte)) { 3361 pmap_cache_wbinv_page(pm, va, true, oflags); 3362 } 3363 #endif 3364 } 3365 } 3366 3367 /* 3368 * Make sure userland mappings get the right permissions 3369 */ 3370 if (!vector_page_p && !kpm_p) { 3371 npte |= L2_S_PROT_U; 3372 #ifdef ARM_MMU_EXTENDED 3373 npte |= L2_XS_nG; /* user pages are not global */ 3374 #endif 3375 } 3376 3377 /* 3378 * Keep the stats up to date 3379 */ 3380 if (opte == 0) { 3381 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3382 pm->pm_stats.resident_count++; 3383 } 3384 3385 UVMHIST_LOG(maphist, " opte %#jx npte %#jx", opte, npte, 0, 0); 3386 3387 #if defined(ARM_MMU_EXTENDED) 3388 /* 3389 * If exec protection was requested but the page hasn't been synced, 3390 * sync it now and allow execution from it. 3391 */ 3392 3393 if ((nflags & PVF_EXEC) && (npte & L2_XS_XN)) { 3394 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3395 npte &= ~L2_XS_XN; 3396 pmap_syncicache_page(md, pa); 3397 PMAPCOUNT(exec_synced_map); 3398 } 3399 #endif 3400 /* 3401 * If this is just a wiring change, the two PTEs will be 3402 * identical, so there's no need to update the page table. 3403 */ 3404 if (npte != opte) { 3405 l2pte_reset(ptep); 3406 PTE_SYNC(ptep); 3407 if (l2pte_valid_p(opte)) { 3408 pmap_tlb_flush_SE(pm, va, oflags); 3409 } 3410 l2pte_set(ptep, npte, 0); 3411 PTE_SYNC(ptep); 3412 #ifndef ARM_MMU_EXTENDED 3413 bool is_cached = pmap_is_cached(pm); 3414 if (is_cached) { 3415 /* 3416 * We only need to frob the cache/tlb if this pmap 3417 * is current 3418 */ 3419 if (!vector_page_p && l2pte_valid_p(npte)) { 3420 /* 3421 * This mapping is likely to be accessed as 3422 * soon as we return to userland. Fix up the 3423 * L1 entry to avoid taking another 3424 * page/domain fault. 3425 */ 3426 pd_entry_t *pdep = pmap_l1_kva(pm) 3427 + l1pte_index(va); 3428 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa 3429 | L1_C_DOM(pmap_domain(pm)); 3430 if (*pdep != pde) { 3431 l1pte_setone(pdep, pde); 3432 PDE_SYNC(pdep); 3433 } 3434 } 3435 } 3436 3437 UVMHIST_LOG(maphist, " is_cached %jd cs 0x%08jx", 3438 is_cached, pm->pm_cstate.cs_all, 0, 0); 3439 3440 if (pg != NULL) { 3441 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3442 3443 pmap_acquire_page_lock(md); 3444 pmap_vac_me_harder(md, pa, pm, va); 3445 pmap_release_page_lock(md); 3446 } 3447 #endif 3448 } 3449 #if defined(PMAP_CACHE_VIPT) && defined(DIAGNOSTIC) 3450 if (pg) { 3451 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3452 3453 pmap_acquire_page_lock(md); 3454 #ifndef ARM_MMU_EXTENDED 3455 KASSERT((md->pvh_attrs & PVF_DMOD) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3456 #endif 3457 PMAP_VALIDATE_MD_PAGE(md); 3458 pmap_release_page_lock(md); 3459 } 3460 #endif 3461 3462 pmap_release_pmap_lock(pm); 3463 kpreempt_enable(); 3464 3465 if (old_pv) 3466 pool_put(&pmap_pv_pool, old_pv); 3467 free_pv: 3468 if (new_pv) 3469 pool_put(&pmap_pv_pool, new_pv); 3470 3471 return error; 3472 } 3473 3474 /* 3475 * pmap_remove() 3476 * 3477 * pmap_remove is responsible for nuking a number of mappings for a range 3478 * of virtual address space in the current pmap. To do this efficiently 3479 * is interesting, because in a number of cases a wide virtual address 3480 * range may be supplied that contains few actual mappings. So, the 3481 * optimisations are: 3482 * 1. Skip over hunks of address space for which no L1 or L2 entry exists. 3483 * 2. Build up a list of pages we've hit, up to a maximum, so we can 3484 * maybe do just a partial cache clean. This path of execution is 3485 * complicated by the fact that the cache must be flushed _before_ 3486 * the PTE is nuked, being a VAC :-) 3487 * 3. If we're called after UVM calls pmap_remove_all(), we can defer 3488 * all invalidations until pmap_update(), since pmap_remove_all() has 3489 * already flushed the cache. 3490 * 4. Maybe later fast-case a single page, but I don't think this is 3491 * going to make _that_ much difference overall. 3492 */ 3493 3494 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3495 3496 void 3497 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva) 3498 { 3499 SLIST_HEAD(,pv_entry) opv_list; 3500 struct pv_entry *pv, *npv; 3501 UVMHIST_FUNC(__func__); 3502 UVMHIST_CALLARGS(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)", 3503 (uintptr_t)pm, sva, eva, 0); 3504 3505 #ifdef PMAP_FAULTINFO 3506 curpcb->pcb_faultinfo.pfi_faultaddr = 0; 3507 curpcb->pcb_faultinfo.pfi_repeats = 0; 3508 curpcb->pcb_faultinfo.pfi_faultptep = NULL; 3509 #endif 3510 3511 SLIST_INIT(&opv_list); 3512 /* 3513 * we lock in the pmap => pv_head direction 3514 */ 3515 kpreempt_disable(); 3516 pmap_acquire_pmap_lock(pm); 3517 3518 #ifndef ARM_MMU_EXTENDED 3519 u_int cleanlist_idx, total, cnt; 3520 struct { 3521 vaddr_t va; 3522 pt_entry_t *ptep; 3523 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3524 3525 if (pm->pm_remove_all || !pmap_is_cached(pm)) { 3526 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3527 if (pm->pm_cstate.cs_tlb == 0) 3528 pm->pm_remove_all = true; 3529 } else 3530 cleanlist_idx = 0; 3531 total = 0; 3532 #endif 3533 3534 while (sva < eva) { 3535 /* 3536 * Do one L2 bucket's worth at a time. 3537 */ 3538 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(sva); 3539 if (next_bucket > eva) 3540 next_bucket = eva; 3541 3542 struct l2_bucket * const l2b = pmap_get_l2_bucket(pm, sva); 3543 if (l2b == NULL) { 3544 sva = next_bucket; 3545 continue; 3546 } 3547 3548 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3549 u_int mappings = 0; 3550 3551 for (;sva < next_bucket; 3552 sva += PAGE_SIZE, ptep += PAGE_SIZE / L2_S_SIZE) { 3553 pt_entry_t opte = *ptep; 3554 3555 if (opte == 0) { 3556 /* Nothing here, move along */ 3557 continue; 3558 } 3559 3560 u_int flags = PVF_REF; 3561 paddr_t pa = l2pte_pa(opte); 3562 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 3563 3564 /* 3565 * Update flags. In a number of circumstances, 3566 * we could cluster a lot of these and do a 3567 * number of sequential pages in one go. 3568 */ 3569 if (pg != NULL) { 3570 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3571 3572 pmap_acquire_page_lock(md); 3573 pv = pmap_remove_pv(md, pa, pm, sva); 3574 pmap_vac_me_harder(md, pa, pm, 0); 3575 pmap_release_page_lock(md); 3576 if (pv != NULL) { 3577 if (pm->pm_remove_all == false) { 3578 flags = pv->pv_flags; 3579 } 3580 SLIST_INSERT_HEAD(&opv_list, 3581 pv, pv_link); 3582 } 3583 } 3584 mappings += PAGE_SIZE / L2_S_SIZE; 3585 3586 if (!l2pte_valid_p(opte)) { 3587 /* 3588 * Ref/Mod emulation is still active for this 3589 * mapping, therefore it is has not yet been 3590 * accessed. No need to frob the cache/tlb. 3591 */ 3592 l2pte_reset(ptep); 3593 PTE_SYNC_CURRENT(pm, ptep); 3594 continue; 3595 } 3596 3597 #ifdef ARM_MMU_EXTENDED 3598 l2pte_reset(ptep); 3599 PTE_SYNC(ptep); 3600 if (__predict_false(pm->pm_remove_all == false)) { 3601 pmap_tlb_flush_SE(pm, sva, flags); 3602 } 3603 #else 3604 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3605 /* Add to the clean list. */ 3606 cleanlist[cleanlist_idx].ptep = ptep; 3607 cleanlist[cleanlist_idx].va = 3608 sva | (flags & PVF_EXEC); 3609 cleanlist_idx++; 3610 } else if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3611 /* Nuke everything if needed. */ 3612 #ifdef PMAP_CACHE_VIVT 3613 pmap_cache_wbinv_all(pm, PVF_EXEC); 3614 #endif 3615 /* 3616 * Roll back the previous PTE list, 3617 * and zero out the current PTE. 3618 */ 3619 for (cnt = 0; 3620 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3621 l2pte_reset(cleanlist[cnt].ptep); 3622 PTE_SYNC(cleanlist[cnt].ptep); 3623 } 3624 l2pte_reset(ptep); 3625 PTE_SYNC(ptep); 3626 cleanlist_idx++; 3627 pm->pm_remove_all = true; 3628 } else { 3629 l2pte_reset(ptep); 3630 PTE_SYNC(ptep); 3631 if (pm->pm_remove_all == false) { 3632 pmap_tlb_flush_SE(pm, sva, flags); 3633 } 3634 } 3635 #endif 3636 } 3637 3638 #ifndef ARM_MMU_EXTENDED 3639 /* 3640 * Deal with any left overs 3641 */ 3642 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3643 total += cleanlist_idx; 3644 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3645 l2pte_reset(cleanlist[cnt].ptep); 3646 PTE_SYNC_CURRENT(pm, cleanlist[cnt].ptep); 3647 vaddr_t va = cleanlist[cnt].va; 3648 if (pm->pm_cstate.cs_all != 0) { 3649 vaddr_t clva = va & ~PAGE_MASK; 3650 u_int flags = va & PVF_EXEC; 3651 #ifdef PMAP_CACHE_VIVT 3652 pmap_cache_wbinv_page(pm, clva, true, 3653 PVF_REF | PVF_WRITE | flags); 3654 #endif 3655 pmap_tlb_flush_SE(pm, clva, 3656 PVF_REF | flags); 3657 } 3658 } 3659 3660 /* 3661 * If it looks like we're removing a whole bunch 3662 * of mappings, it's faster to just write-back 3663 * the whole cache now and defer TLB flushes until 3664 * pmap_update() is called. 3665 */ 3666 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3667 cleanlist_idx = 0; 3668 else { 3669 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3670 #ifdef PMAP_CACHE_VIVT 3671 pmap_cache_wbinv_all(pm, PVF_EXEC); 3672 #endif 3673 pm->pm_remove_all = true; 3674 } 3675 } 3676 #endif /* ARM_MMU_EXTENDED */ 3677 3678 pmap_free_l2_bucket(pm, l2b, mappings); 3679 pm->pm_stats.resident_count -= mappings / (PAGE_SIZE/L2_S_SIZE); 3680 } 3681 3682 pmap_release_pmap_lock(pm); 3683 kpreempt_enable(); 3684 3685 SLIST_FOREACH_SAFE(pv, &opv_list, pv_link, npv) { 3686 pool_put(&pmap_pv_pool, pv); 3687 } 3688 } 3689 3690 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3691 static struct pv_entry * 3692 pmap_kremove_pg(struct vm_page *pg, vaddr_t va) 3693 { 3694 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 3695 paddr_t pa = VM_PAGE_TO_PHYS(pg); 3696 struct pv_entry *pv; 3697 3698 KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC)); 3699 KASSERT((md->pvh_attrs & PVF_KMPAGE) == 0); 3700 KASSERT(pmap_page_locked_p(md)); 3701 3702 pv = pmap_remove_pv(md, pa, pmap_kernel(), va); 3703 KASSERTMSG(pv, "pg %p (pa #%lx) va %#lx", pg, pa, va); 3704 KASSERT(PV_IS_KENTRY_P(pv->pv_flags)); 3705 3706 /* 3707 * We are removing a writeable mapping to a cached exec page, if 3708 * it's the last mapping then clear its execness otherwise sync 3709 * the page to the icache. 3710 */ 3711 if ((md->pvh_attrs & (PVF_NC|PVF_EXEC)) == PVF_EXEC 3712 && (pv->pv_flags & PVF_WRITE) != 0) { 3713 if (SLIST_EMPTY(&md->pvh_list)) { 3714 md->pvh_attrs &= ~PVF_EXEC; 3715 PMAPCOUNT(exec_discarded_kremove); 3716 } else { 3717 pmap_syncicache_page(md, pa); 3718 PMAPCOUNT(exec_synced_kremove); 3719 } 3720 } 3721 pmap_vac_me_harder(md, pa, pmap_kernel(), 0); 3722 3723 return pv; 3724 } 3725 #endif /* PMAP_CACHE_VIPT && !ARM_MMU_EXTENDED */ 3726 3727 /* 3728 * pmap_kenter_pa: enter an unmanaged, wired kernel mapping 3729 * 3730 * We assume there is already sufficient KVM space available 3731 * to do this, as we can't allocate L2 descriptor tables/metadata 3732 * from here. 3733 */ 3734 void 3735 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 3736 { 3737 #ifdef PMAP_CACHE_VIVT 3738 struct vm_page *pg = (flags & PMAP_KMPAGE) ? PHYS_TO_VM_PAGE(pa) : NULL; 3739 #endif 3740 #ifdef PMAP_CACHE_VIPT 3741 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 3742 struct vm_page *opg; 3743 #ifndef ARM_MMU_EXTENDED 3744 struct pv_entry *pv = NULL; 3745 #endif 3746 #endif 3747 struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL; 3748 3749 UVMHIST_FUNC(__func__); 3750 3751 if (pmap_initialized) { 3752 UVMHIST_CALLARGS(maphist, 3753 "va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", va, pa, prot, 3754 flags); 3755 } 3756 3757 kpreempt_disable(); 3758 pmap_t kpm = pmap_kernel(); 3759 pmap_acquire_pmap_lock(kpm); 3760 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3761 const size_t l1slot __diagused = l1pte_index(va); 3762 KASSERTMSG(l2b != NULL, 3763 "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p", 3764 va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)], 3765 kpm->pm_l2[L2_IDX(l1slot)] 3766 ? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)] 3767 : NULL, 3768 kpm->pm_l2[L2_IDX(l1slot)] 3769 ? kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)].l2b_kva 3770 : NULL); 3771 KASSERT(l2b->l2b_kva != NULL); 3772 3773 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 3774 const pt_entry_t opte = *ptep; 3775 3776 if (opte == 0) { 3777 PMAPCOUNT(kenter_mappings); 3778 l2b->l2b_occupancy += PAGE_SIZE / L2_S_SIZE; 3779 } else { 3780 PMAPCOUNT(kenter_remappings); 3781 #ifdef PMAP_CACHE_VIPT 3782 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3783 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3784 if (opg && arm_cache_prefer_mask != 0) { 3785 KASSERT(opg != pg); 3786 KASSERT((omd->pvh_attrs & PVF_KMPAGE) == 0); 3787 KASSERT((flags & PMAP_KMPAGE) == 0); 3788 #ifndef ARM_MMU_EXTENDED 3789 pmap_acquire_page_lock(omd); 3790 pv = pmap_kremove_pg(opg, va); 3791 pmap_release_page_lock(omd); 3792 #endif 3793 } 3794 #endif 3795 if (l2pte_valid_p(opte)) { 3796 l2pte_reset(ptep); 3797 PTE_SYNC(ptep); 3798 #ifdef PMAP_CACHE_VIVT 3799 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3800 #endif 3801 cpu_tlb_flushD_SE(va); 3802 cpu_cpwait(); 3803 } 3804 } 3805 pmap_release_pmap_lock(kpm); 3806 pt_entry_t npte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 3807 3808 if (flags & PMAP_PTE) { 3809 KASSERT((flags & PMAP_CACHE_MASK) == 0); 3810 if (!(flags & PMAP_NOCACHE)) 3811 npte |= pte_l2_s_cache_mode_pt; 3812 } else { 3813 switch (flags & (PMAP_CACHE_MASK | PMAP_DEV_MASK)) { 3814 case PMAP_DEV ... PMAP_DEV | PMAP_CACHE_MASK: 3815 break; 3816 case PMAP_NOCACHE: 3817 npte |= pte_l2_s_nocache_mode; 3818 break; 3819 case PMAP_WRITE_COMBINE: 3820 npte |= pte_l2_s_wc_mode; 3821 break; 3822 default: 3823 npte |= pte_l2_s_cache_mode; 3824 break; 3825 } 3826 } 3827 #ifdef ARM_MMU_EXTENDED 3828 if (prot & VM_PROT_EXECUTE) 3829 npte &= ~L2_XS_XN; 3830 #endif 3831 l2pte_set(ptep, npte, 0); 3832 PTE_SYNC(ptep); 3833 3834 if (pg) { 3835 if (flags & PMAP_KMPAGE) { 3836 KASSERT(md->urw_mappings == 0); 3837 KASSERT(md->uro_mappings == 0); 3838 KASSERT(md->krw_mappings == 0); 3839 KASSERT(md->kro_mappings == 0); 3840 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3841 KASSERT(pv == NULL); 3842 KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0); 3843 KASSERT((md->pvh_attrs & PVF_NC) == 0); 3844 /* if there is a color conflict, evict from cache. */ 3845 if (pmap_is_page_colored_p(md) 3846 && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) { 3847 PMAPCOUNT(vac_color_change); 3848 pmap_flush_page(md, pa, PMAP_FLUSH_PRIMARY); 3849 } else if (md->pvh_attrs & PVF_MULTCLR) { 3850 /* 3851 * If this page has multiple colors, expunge 3852 * them. 3853 */ 3854 PMAPCOUNT(vac_flush_lots2); 3855 pmap_flush_page(md, pa, PMAP_FLUSH_SECONDARY); 3856 } 3857 /* 3858 * Since this is a KMPAGE, there can be no contention 3859 * for this page so don't lock it. 3860 */ 3861 md->pvh_attrs &= PAGE_SIZE - 1; 3862 md->pvh_attrs |= PVF_KMPAGE | PVF_COLORED | PVF_DIRTY 3863 | (va & arm_cache_prefer_mask); 3864 #else /* !PMAP_CACHE_VIPT || ARM_MMU_EXTENDED */ 3865 md->pvh_attrs |= PVF_KMPAGE; 3866 #endif 3867 atomic_inc_32(&pmap_kmpages); 3868 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3869 } else if (arm_cache_prefer_mask != 0) { 3870 if (pv == NULL) { 3871 pv = pool_get(&pmap_pv_pool, PR_NOWAIT); 3872 KASSERT(pv != NULL); 3873 } 3874 pmap_acquire_page_lock(md); 3875 pmap_enter_pv(md, pa, pv, pmap_kernel(), va, 3876 PVF_WIRED | PVF_KENTRY 3877 | (prot & VM_PROT_WRITE ? PVF_WRITE : 0)); 3878 if ((prot & VM_PROT_WRITE) 3879 && !(md->pvh_attrs & PVF_NC)) 3880 md->pvh_attrs |= PVF_DIRTY; 3881 KASSERT((prot & VM_PROT_WRITE) == 0 || (md->pvh_attrs & (PVF_DIRTY|PVF_NC))); 3882 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 3883 pmap_release_page_lock(md); 3884 #endif 3885 } 3886 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3887 } else { 3888 if (pv != NULL) 3889 pool_put(&pmap_pv_pool, pv); 3890 #endif 3891 } 3892 kpreempt_enable(); 3893 3894 if (pmap_initialized) { 3895 UVMHIST_LOG(maphist, " <-- done (ptep %#jx: %#jx -> %#jx)", 3896 (uintptr_t)ptep, opte, npte, 0); 3897 } 3898 3899 } 3900 3901 void 3902 pmap_kremove(vaddr_t va, vsize_t len) 3903 { 3904 #ifdef UVMHIST 3905 u_int total_mappings = 0; 3906 #endif 3907 3908 PMAPCOUNT(kenter_unmappings); 3909 3910 UVMHIST_FUNC(__func__); 3911 UVMHIST_CALLARGS(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0); 3912 3913 const vaddr_t eva = va + len; 3914 pmap_t kpm = pmap_kernel(); 3915 3916 kpreempt_disable(); 3917 pmap_acquire_pmap_lock(kpm); 3918 3919 while (va < eva) { 3920 vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va); 3921 if (next_bucket > eva) 3922 next_bucket = eva; 3923 3924 struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va); 3925 KDASSERT(l2b != NULL); 3926 3927 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 3928 pt_entry_t *ptep = sptep; 3929 u_int mappings = 0; 3930 3931 while (va < next_bucket) { 3932 const pt_entry_t opte = *ptep; 3933 struct vm_page *opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3934 if (opg != NULL) { 3935 struct vm_page_md *omd = VM_PAGE_TO_MD(opg); 3936 3937 if (omd->pvh_attrs & PVF_KMPAGE) { 3938 KASSERT(omd->urw_mappings == 0); 3939 KASSERT(omd->uro_mappings == 0); 3940 KASSERT(omd->krw_mappings == 0); 3941 KASSERT(omd->kro_mappings == 0); 3942 omd->pvh_attrs &= ~PVF_KMPAGE; 3943 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3944 if (arm_cache_prefer_mask != 0) { 3945 omd->pvh_attrs &= ~PVF_WRITE; 3946 } 3947 #endif 3948 atomic_dec_32(&pmap_kmpages); 3949 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 3950 } else if (arm_cache_prefer_mask != 0) { 3951 pmap_acquire_page_lock(omd); 3952 pool_put(&pmap_pv_pool, 3953 pmap_kremove_pg(opg, va)); 3954 pmap_release_page_lock(omd); 3955 #endif 3956 } 3957 } 3958 if (l2pte_valid_p(opte)) { 3959 l2pte_reset(ptep); 3960 PTE_SYNC(ptep); 3961 #ifdef PMAP_CACHE_VIVT 3962 cpu_dcache_wbinv_range(va, PAGE_SIZE); 3963 #endif 3964 cpu_tlb_flushD_SE(va); 3965 3966 mappings += PAGE_SIZE / L2_S_SIZE; 3967 } 3968 va += PAGE_SIZE; 3969 ptep += PAGE_SIZE / L2_S_SIZE; 3970 } 3971 KDASSERTMSG(mappings <= l2b->l2b_occupancy, "%u %u", 3972 mappings, l2b->l2b_occupancy); 3973 l2b->l2b_occupancy -= mappings; 3974 //PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3975 #ifdef UVMHIST 3976 total_mappings += mappings; 3977 #endif 3978 } 3979 pmap_release_pmap_lock(kpm); 3980 cpu_cpwait(); 3981 kpreempt_enable(); 3982 3983 UVMHIST_LOG(maphist, " <--- done (%ju mappings removed)", 3984 total_mappings, 0, 0, 0); 3985 } 3986 3987 bool 3988 pmap_extract(pmap_t pm, vaddr_t va, paddr_t *pap) 3989 { 3990 3991 return pmap_extract_coherency(pm, va, pap, NULL); 3992 } 3993 3994 bool 3995 pmap_extract_coherency(pmap_t pm, vaddr_t va, paddr_t *pap, bool *coherentp) 3996 { 3997 struct l2_dtable *l2; 3998 pd_entry_t *pdep, pde; 3999 pt_entry_t *ptep, pte; 4000 paddr_t pa; 4001 u_int l1slot; 4002 bool coherent; 4003 4004 kpreempt_disable(); 4005 pmap_acquire_pmap_lock(pm); 4006 4007 l1slot = l1pte_index(va); 4008 pdep = pmap_l1_kva(pm) + l1slot; 4009 pde = *pdep; 4010 4011 if (l1pte_section_p(pde)) { 4012 /* 4013 * These should only happen for pmap_kernel() 4014 */ 4015 KDASSERT(pm == pmap_kernel()); 4016 pmap_release_pmap_lock(pm); 4017 kpreempt_enable(); 4018 4019 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 4020 if (l1pte_supersection_p(pde)) { 4021 pa = (pde & L1_SS_FRAME) | (va & L1_SS_OFFSET); 4022 } else 4023 #endif 4024 pa = (pde & L1_S_FRAME) | (va & L1_S_OFFSET); 4025 coherent = (pde & L1_S_CACHE_MASK) == 0; 4026 } else { 4027 /* 4028 * Note that we can't rely on the validity of the L1 4029 * descriptor as an indication that a mapping exists. 4030 * We have to look it up in the L2 dtable. 4031 */ 4032 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4033 4034 if (l2 == NULL || 4035 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 4036 pmap_release_pmap_lock(pm); 4037 kpreempt_enable(); 4038 4039 return false; 4040 } 4041 4042 pte = ptep[l2pte_index(va)]; 4043 pmap_release_pmap_lock(pm); 4044 kpreempt_enable(); 4045 4046 if (pte == 0) 4047 return false; 4048 4049 switch (pte & L2_TYPE_MASK) { 4050 case L2_TYPE_L: 4051 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 4052 coherent = (pte & L2_L_CACHE_MASK) == 0; 4053 break; 4054 4055 default: 4056 pa = (pte & ~PAGE_MASK) | (va & PAGE_MASK); 4057 coherent = (pte & L2_S_CACHE_MASK) == 0; 4058 break; 4059 } 4060 } 4061 4062 if (pap != NULL) 4063 *pap = pa; 4064 4065 if (coherentp != NULL) 4066 *coherentp = (pm == pmap_kernel() && coherent); 4067 4068 return true; 4069 } 4070 4071 /* 4072 * pmap_pv_remove: remove an unmanaged pv-tracked page from all pmaps 4073 * that map it 4074 */ 4075 4076 static void 4077 pmap_pv_remove(paddr_t pa) 4078 { 4079 struct pmap_page *pp; 4080 4081 KASSERT(kpreempt_disabled()); 4082 pp = pmap_pv_tracked(pa); 4083 if (pp == NULL) 4084 panic("pmap_pv_protect: page not pv-tracked: 0x%"PRIxPADDR, 4085 pa); 4086 4087 struct vm_page_md *md = PMAP_PAGE_TO_MD(pp); 4088 pmap_page_remove(md, pa); 4089 } 4090 4091 void 4092 pmap_pv_protect(paddr_t pa, vm_prot_t prot) 4093 { 4094 4095 /* the only case is remove at the moment */ 4096 KASSERT(prot == VM_PROT_NONE); 4097 pmap_pv_remove(pa); 4098 } 4099 4100 void 4101 pmap_protect(pmap_t pm, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 4102 { 4103 struct l2_bucket *l2b; 4104 vaddr_t next_bucket; 4105 4106 UVMHIST_FUNC(__func__); 4107 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx prot %#jx", 4108 (uintptr_t)pm, sva, eva, prot); 4109 4110 if ((prot & VM_PROT_READ) == 0) { 4111 pmap_remove(pm, sva, eva); 4112 return; 4113 } 4114 4115 if (prot & VM_PROT_WRITE) { 4116 /* 4117 * If this is a read->write transition, just ignore it and let 4118 * uvm_fault() take care of it later. 4119 */ 4120 return; 4121 } 4122 4123 kpreempt_disable(); 4124 pmap_acquire_pmap_lock(pm); 4125 4126 #ifndef ARM_MMU_EXTENDED 4127 const bool flush = eva - sva >= PAGE_SIZE * 4; 4128 u_int flags = 0; 4129 #endif 4130 u_int clr_mask = PVF_WRITE | ((prot & VM_PROT_EXECUTE) ? 0 : PVF_EXEC); 4131 4132 while (sva < eva) { 4133 next_bucket = L2_NEXT_BUCKET_VA(sva); 4134 if (next_bucket > eva) 4135 next_bucket = eva; 4136 4137 l2b = pmap_get_l2_bucket(pm, sva); 4138 if (l2b == NULL) { 4139 sva = next_bucket; 4140 continue; 4141 } 4142 4143 pt_entry_t *ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4144 4145 while (sva < next_bucket) { 4146 const pt_entry_t opte = *ptep; 4147 if (l2pte_valid_p(opte) && l2pte_writable_p(opte)) { 4148 struct vm_page *pg; 4149 #ifndef ARM_MMU_EXTENDED 4150 u_int f; 4151 #endif 4152 4153 #ifdef PMAP_CACHE_VIVT 4154 /* 4155 * OK, at this point, we know we're doing 4156 * write-protect operation. If the pmap is 4157 * active, write-back the page. 4158 */ 4159 pmap_cache_wbinv_page(pm, sva, false, 4160 PVF_REF | PVF_WRITE); 4161 #endif 4162 4163 pg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 4164 pt_entry_t npte = l2pte_set_readonly(opte); 4165 l2pte_reset(ptep); 4166 PTE_SYNC(ptep); 4167 #ifdef ARM_MMU_EXTENDED 4168 pmap_tlb_flush_SE(pm, sva, PVF_REF); 4169 #endif 4170 l2pte_set(ptep, npte, 0); 4171 PTE_SYNC(ptep); 4172 4173 if (pg != NULL) { 4174 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4175 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4176 4177 pmap_acquire_page_lock(md); 4178 #ifndef ARM_MMU_EXTENDED 4179 f = 4180 #endif 4181 pmap_modify_pv(md, pa, pm, sva, 4182 clr_mask, 0); 4183 pmap_vac_me_harder(md, pa, pm, sva); 4184 pmap_release_page_lock(md); 4185 #ifndef ARM_MMU_EXTENDED 4186 } else { 4187 f = PVF_REF | PVF_EXEC; 4188 } 4189 4190 if (flush) { 4191 flags |= f; 4192 } else { 4193 pmap_tlb_flush_SE(pm, sva, f); 4194 #endif 4195 } 4196 } 4197 4198 sva += PAGE_SIZE; 4199 ptep += PAGE_SIZE / L2_S_SIZE; 4200 } 4201 } 4202 4203 #ifndef ARM_MMU_EXTENDED 4204 if (flush) { 4205 if (PV_BEEN_EXECD(flags)) { 4206 pmap_tlb_flushID(pm); 4207 } else if (PV_BEEN_REFD(flags)) { 4208 pmap_tlb_flushD(pm); 4209 } 4210 } 4211 #endif 4212 4213 pmap_release_pmap_lock(pm); 4214 kpreempt_enable(); 4215 } 4216 4217 void 4218 pmap_icache_sync_range(pmap_t pm, vaddr_t sva, vaddr_t eva) 4219 { 4220 struct l2_bucket *l2b; 4221 pt_entry_t *ptep; 4222 vaddr_t next_bucket; 4223 vsize_t page_size = trunc_page(sva) + PAGE_SIZE - sva; 4224 4225 UVMHIST_FUNC(__func__); 4226 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx...#%jx", 4227 (uintptr_t)pm, sva, eva, 0); 4228 4229 pmap_acquire_pmap_lock(pm); 4230 4231 while (sva < eva) { 4232 next_bucket = L2_NEXT_BUCKET_VA(sva); 4233 if (next_bucket > eva) 4234 next_bucket = eva; 4235 4236 l2b = pmap_get_l2_bucket(pm, sva); 4237 if (l2b == NULL) { 4238 sva = next_bucket; 4239 continue; 4240 } 4241 4242 for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; 4243 sva < next_bucket; 4244 sva += page_size, 4245 ptep += PAGE_SIZE / L2_S_SIZE, 4246 page_size = PAGE_SIZE) { 4247 if (l2pte_valid_p(*ptep)) { 4248 cpu_icache_sync_range(sva, 4249 uimin(page_size, eva - sva)); 4250 } 4251 } 4252 } 4253 4254 pmap_release_pmap_lock(pm); 4255 } 4256 4257 void 4258 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 4259 { 4260 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4261 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4262 4263 UVMHIST_FUNC(__func__); 4264 UVMHIST_CALLARGS(maphist, "md %#jx pa %#jx prot %#jx", 4265 (uintptr_t)md, pa, prot, 0); 4266 4267 switch(prot) { 4268 case VM_PROT_READ|VM_PROT_WRITE: 4269 #if defined(ARM_MMU_EXTENDED) 4270 pmap_acquire_page_lock(md); 4271 pmap_clearbit(md, pa, PVF_EXEC); 4272 pmap_release_page_lock(md); 4273 break; 4274 #endif 4275 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 4276 break; 4277 4278 case VM_PROT_READ: 4279 #if defined(ARM_MMU_EXTENDED) 4280 pmap_acquire_page_lock(md); 4281 pmap_clearbit(md, pa, PVF_WRITE|PVF_EXEC); 4282 pmap_release_page_lock(md); 4283 break; 4284 #endif 4285 case VM_PROT_READ|VM_PROT_EXECUTE: 4286 pmap_acquire_page_lock(md); 4287 pmap_clearbit(md, pa, PVF_WRITE); 4288 pmap_release_page_lock(md); 4289 break; 4290 4291 default: 4292 pmap_page_remove(md, pa); 4293 break; 4294 } 4295 } 4296 4297 /* 4298 * pmap_clear_modify: 4299 * 4300 * Clear the "modified" attribute for a page. 4301 */ 4302 bool 4303 pmap_clear_modify(struct vm_page *pg) 4304 { 4305 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4306 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4307 bool rv; 4308 4309 pmap_acquire_page_lock(md); 4310 4311 if (md->pvh_attrs & PVF_MOD) { 4312 rv = true; 4313 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4314 /* 4315 * If we are going to clear the modified bit and there are 4316 * no other modified bits set, flush the page to memory and 4317 * mark it clean. 4318 */ 4319 if ((md->pvh_attrs & (PVF_DMOD|PVF_NC)) == PVF_MOD) 4320 pmap_flush_page(md, pa, PMAP_CLEAN_PRIMARY); 4321 #endif 4322 pmap_clearbit(md, pa, PVF_MOD); 4323 } else { 4324 rv = false; 4325 } 4326 pmap_release_page_lock(md); 4327 4328 return rv; 4329 } 4330 4331 /* 4332 * pmap_clear_reference: 4333 * 4334 * Clear the "referenced" attribute for a page. 4335 */ 4336 bool 4337 pmap_clear_reference(struct vm_page *pg) 4338 { 4339 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4340 paddr_t pa = VM_PAGE_TO_PHYS(pg); 4341 bool rv; 4342 4343 pmap_acquire_page_lock(md); 4344 4345 if (md->pvh_attrs & PVF_REF) { 4346 rv = true; 4347 pmap_clearbit(md, pa, PVF_REF); 4348 } else { 4349 rv = false; 4350 } 4351 pmap_release_page_lock(md); 4352 4353 return rv; 4354 } 4355 4356 /* 4357 * pmap_is_modified: 4358 * 4359 * Test if a page has the "modified" attribute. 4360 */ 4361 /* See <arm/arm32/pmap.h> */ 4362 4363 /* 4364 * pmap_is_referenced: 4365 * 4366 * Test if a page has the "referenced" attribute. 4367 */ 4368 /* See <arm/arm32/pmap.h> */ 4369 4370 #if defined(ARM_MMU_EXTENDED) && 0 4371 int 4372 pmap_prefetchabt_fixup(void *v) 4373 { 4374 struct trapframe * const tf = v; 4375 vaddr_t va = trunc_page(tf->tf_pc); 4376 int rv = ABORT_FIXUP_FAILED; 4377 4378 if (!TRAP_USERMODE(tf) && va < VM_MAXUSER_ADDRESS) 4379 return rv; 4380 4381 kpreempt_disable(); 4382 pmap_t pm = curcpu()->ci_pmap_cur; 4383 const size_t l1slot = l1pte_index(va); 4384 struct l2_dtable * const l2 = pm->pm_l2[L2_IDX(l1slot)]; 4385 if (l2 == NULL) 4386 goto out; 4387 4388 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4389 if (l2b->l2b_kva == NULL) 4390 goto out; 4391 4392 /* 4393 * Check the PTE itself. 4394 */ 4395 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4396 const pt_entry_t opte = *ptep; 4397 if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0) 4398 goto out; 4399 4400 paddr_t pa = l2pte_pa(opte); 4401 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4402 KASSERT(pg != NULL); 4403 4404 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4405 4406 pmap_acquire_page_lock(md); 4407 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4408 KASSERT(pv != NULL); 4409 4410 if (PV_IS_EXEC_P(pv->pv_flags)) { 4411 l2pte_reset(ptep); 4412 PTE_SYNC(ptep); 4413 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4414 if (!PV_IS_EXEC_P(md->pvh_attrs)) { 4415 pmap_syncicache_page(md, pa); 4416 } 4417 rv = ABORT_FIXUP_RETURN; 4418 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4419 PTE_SYNC(ptep); 4420 } 4421 pmap_release_page_lock(md); 4422 4423 out: 4424 kpreempt_enable(); 4425 4426 return rv; 4427 } 4428 #endif 4429 4430 int 4431 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user) 4432 { 4433 struct l2_dtable *l2; 4434 struct l2_bucket *l2b; 4435 paddr_t pa; 4436 const size_t l1slot = l1pte_index(va); 4437 int rv = 0; 4438 4439 UVMHIST_FUNC(__func__); 4440 UVMHIST_CALLARGS(maphist, "pm=%#jx, va=%#jx, ftype=%#jx, user=%jd", 4441 (uintptr_t)pm, va, ftype, user); 4442 4443 va = trunc_page(va); 4444 4445 KASSERT(!user || (pm != pmap_kernel())); 4446 4447 #ifdef ARM_MMU_EXTENDED 4448 UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx", 4449 (uintptr_t)cpu_tlb_info(curcpu()), 4450 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())), 4451 (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0); 4452 #endif 4453 4454 kpreempt_disable(); 4455 pmap_acquire_pmap_lock(pm); 4456 4457 /* 4458 * If there is no l2_dtable for this address, then the process 4459 * has no business accessing it. 4460 * 4461 * Note: This will catch userland processes trying to access 4462 * kernel addresses. 4463 */ 4464 l2 = pm->pm_l2[L2_IDX(l1slot)]; 4465 if (l2 == NULL) { 4466 UVMHIST_LOG(maphist, " no l2 for l1slot %#jx", l1slot, 0, 0, 0); 4467 goto out; 4468 } 4469 4470 /* 4471 * Likewise if there is no L2 descriptor table 4472 */ 4473 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 4474 if (l2b->l2b_kva == NULL) { 4475 UVMHIST_LOG(maphist, " <-- done (no ptep for l1slot %#jx)", 4476 l1slot, 0, 0, 0); 4477 goto out; 4478 } 4479 4480 /* 4481 * Check the PTE itself. 4482 */ 4483 pt_entry_t * const ptep = &l2b->l2b_kva[l2pte_index(va)]; 4484 pt_entry_t const opte = *ptep; 4485 if (opte == 0 || (opte & L2_TYPE_MASK) == L2_TYPE_L) { 4486 UVMHIST_LOG(maphist, " <-- done (empty pte)", 4487 0, 0, 0, 0); 4488 goto out; 4489 } 4490 4491 #ifndef ARM_HAS_VBAR 4492 /* 4493 * Catch a userland access to the vector page mapped at 0x0 4494 */ 4495 if (user && (opte & L2_S_PROT_U) == 0) { 4496 UVMHIST_LOG(maphist, " <-- done (vector_page)", 0, 0, 0, 0); 4497 goto out; 4498 } 4499 #endif 4500 4501 pa = l2pte_pa(opte); 4502 UVMHIST_LOG(maphist, " pa %#jx opte %#jx ", pa, opte, 0, 0); 4503 4504 if ((ftype & VM_PROT_WRITE) && !l2pte_writable_p(opte)) { 4505 /* 4506 * This looks like a good candidate for "page modified" 4507 * emulation... 4508 */ 4509 struct pv_entry *pv; 4510 struct vm_page *pg; 4511 4512 /* Extract the physical address of the page */ 4513 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4514 UVMHIST_LOG(maphist, " <-- done (mod/ref unmanaged page)", 0, 0, 0, 0); 4515 goto out; 4516 } 4517 4518 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4519 4520 /* Get the current flags for this page. */ 4521 pmap_acquire_page_lock(md); 4522 pv = pmap_find_pv(md, pm, va); 4523 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4524 pmap_release_page_lock(md); 4525 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: no PV)", 0, 0, 0, 0); 4526 goto out; 4527 } 4528 4529 /* 4530 * Do the flags say this page is writable? If not then it 4531 * is a genuine write fault. If yes then the write fault is 4532 * our fault as we did not reflect the write access in the 4533 * PTE. Now we know a write has occurred we can correct this 4534 * and also set the modified bit 4535 */ 4536 if ((pv->pv_flags & PVF_WRITE) == 0) { 4537 pmap_release_page_lock(md); 4538 UVMHIST_LOG(maphist, " <-- done (write fault)", 0, 0, 0, 0); 4539 goto out; 4540 } 4541 4542 md->pvh_attrs |= PVF_REF | PVF_MOD; 4543 pv->pv_flags |= PVF_REF | PVF_MOD; 4544 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 4545 /* 4546 * If there are cacheable mappings for this page, mark it dirty. 4547 */ 4548 if ((md->pvh_attrs & PVF_NC) == 0) 4549 md->pvh_attrs |= PVF_DIRTY; 4550 #endif 4551 #ifdef ARM_MMU_EXTENDED 4552 if (md->pvh_attrs & PVF_EXEC) { 4553 md->pvh_attrs &= ~PVF_EXEC; 4554 PMAPCOUNT(exec_discarded_modfixup); 4555 } 4556 #endif 4557 pmap_release_page_lock(md); 4558 4559 /* 4560 * Re-enable write permissions for the page. No need to call 4561 * pmap_vac_me_harder(), since this is just a 4562 * modified-emulation fault, and the PVF_WRITE bit isn't 4563 * changing. We've already set the cacheable bits based on 4564 * the assumption that we can write to this page. 4565 */ 4566 const pt_entry_t npte = 4567 l2pte_set_writable((opte & ~L2_TYPE_MASK) | L2_S_PROTO) 4568 #ifdef ARM_MMU_EXTENDED 4569 | (pm != pmap_kernel() ? L2_XS_nG : 0) 4570 #endif 4571 | 0; 4572 l2pte_reset(ptep); 4573 PTE_SYNC(ptep); 4574 pmap_tlb_flush_SE(pm, va, 4575 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4576 l2pte_set(ptep, npte, 0); 4577 PTE_SYNC(ptep); 4578 PMAPCOUNT(fixup_mod); 4579 rv = 1; 4580 UVMHIST_LOG(maphist, " <-- done (mod/ref emul: changed pte " 4581 "from %#jx to %#jx)", opte, npte, 0, 0); 4582 } else if ((opte & L2_TYPE_MASK) == L2_TYPE_INV) { 4583 /* 4584 * This looks like a good candidate for "page referenced" 4585 * emulation. 4586 */ 4587 struct vm_page *pg; 4588 4589 /* Extract the physical address of the page */ 4590 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 4591 UVMHIST_LOG(maphist, " <-- done (ref emul: unmanaged page)", 0, 0, 0, 0); 4592 goto out; 4593 } 4594 4595 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4596 4597 /* Get the current flags for this page. */ 4598 pmap_acquire_page_lock(md); 4599 struct pv_entry *pv = pmap_find_pv(md, pm, va); 4600 if (pv == NULL || PV_IS_KENTRY_P(pv->pv_flags)) { 4601 pmap_release_page_lock(md); 4602 UVMHIST_LOG(maphist, " <-- done (ref emul no PV)", 0, 0, 0, 0); 4603 goto out; 4604 } 4605 4606 md->pvh_attrs |= PVF_REF; 4607 pv->pv_flags |= PVF_REF; 4608 4609 pt_entry_t npte = 4610 l2pte_set_readonly((opte & ~L2_TYPE_MASK) | L2_S_PROTO); 4611 #ifdef ARM_MMU_EXTENDED 4612 if (pm != pmap_kernel()) { 4613 npte |= L2_XS_nG; 4614 } 4615 /* 4616 * If we got called from prefetch abort, then ftype will have 4617 * VM_PROT_EXECUTE set. Now see if we have no-execute set in 4618 * the PTE. 4619 */ 4620 if (user && (ftype & VM_PROT_EXECUTE) && (npte & L2_XS_XN)) { 4621 /* 4622 * Is this a mapping of an executable page? 4623 */ 4624 if ((pv->pv_flags & PVF_EXEC) == 0) { 4625 pmap_release_page_lock(md); 4626 UVMHIST_LOG(maphist, " <-- done (ref emul: no exec)", 4627 0, 0, 0, 0); 4628 goto out; 4629 } 4630 /* 4631 * If we haven't synced the page, do so now. 4632 */ 4633 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4634 UVMHIST_LOG(maphist, " ref emul: syncicache " 4635 "page #%#jx", pa, 0, 0, 0); 4636 pmap_syncicache_page(md, pa); 4637 PMAPCOUNT(fixup_exec); 4638 } 4639 npte &= ~L2_XS_XN; 4640 } 4641 #endif /* ARM_MMU_EXTENDED */ 4642 pmap_release_page_lock(md); 4643 l2pte_reset(ptep); 4644 PTE_SYNC(ptep); 4645 pmap_tlb_flush_SE(pm, va, 4646 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4647 l2pte_set(ptep, npte, 0); 4648 PTE_SYNC(ptep); 4649 PMAPCOUNT(fixup_ref); 4650 rv = 1; 4651 UVMHIST_LOG(maphist, " <-- done (ref emul: changed pte from " 4652 "%#jx to %#jx)", opte, npte, 0, 0); 4653 #ifdef ARM_MMU_EXTENDED 4654 } else if (user && (ftype & VM_PROT_EXECUTE) && (opte & L2_XS_XN)) { 4655 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 4656 if (pg == NULL) { 4657 UVMHIST_LOG(maphist, " <-- done (unmanaged page)", 0, 0, 0, 0); 4658 goto out; 4659 } 4660 4661 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 4662 4663 /* Get the current flags for this page. */ 4664 pmap_acquire_page_lock(md); 4665 struct pv_entry * const pv = pmap_find_pv(md, pm, va); 4666 if (pv == NULL || (pv->pv_flags & PVF_EXEC) == 0) { 4667 pmap_release_page_lock(md); 4668 UVMHIST_LOG(maphist, " <-- done (no PV or not EXEC)", 0, 0, 0, 0); 4669 goto out; 4670 } 4671 4672 /* 4673 * If we haven't synced the page, do so now. 4674 */ 4675 if ((md->pvh_attrs & PVF_EXEC) == 0) { 4676 UVMHIST_LOG(maphist, "syncicache page #%#jx", 4677 pa, 0, 0, 0); 4678 pmap_syncicache_page(md, pa); 4679 } 4680 pmap_release_page_lock(md); 4681 /* 4682 * Turn off no-execute. 4683 */ 4684 KASSERT(opte & L2_XS_nG); 4685 l2pte_reset(ptep); 4686 PTE_SYNC(ptep); 4687 pmap_tlb_flush_SE(pm, va, PVF_EXEC | PVF_REF); 4688 l2pte_set(ptep, opte & ~L2_XS_XN, 0); 4689 PTE_SYNC(ptep); 4690 rv = 1; 4691 PMAPCOUNT(fixup_exec); 4692 UVMHIST_LOG(maphist, "exec: changed pte from %#jx to %#jx", 4693 opte, opte & ~L2_XS_XN, 0, 0); 4694 #endif 4695 } 4696 4697 #ifndef ARM_MMU_EXTENDED 4698 /* 4699 * We know there is a valid mapping here, so simply 4700 * fix up the L1 if necessary. 4701 */ 4702 pd_entry_t * const pdep = pmap_l1_kva(pm) + l1slot; 4703 pd_entry_t pde = L1_C_PROTO | l2b->l2b_pa | L1_C_DOM(pmap_domain(pm)); 4704 if (*pdep != pde) { 4705 l1pte_setone(pdep, pde); 4706 PDE_SYNC(pdep); 4707 rv = 1; 4708 PMAPCOUNT(fixup_pdes); 4709 } 4710 #endif 4711 4712 #ifdef CPU_SA110 4713 /* 4714 * There are bugs in the rev K SA110. This is a check for one 4715 * of them. 4716 */ 4717 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 4718 curcpu()->ci_arm_cpurev < 3) { 4719 /* Always current pmap */ 4720 if (l2pte_valid_p(opte)) { 4721 extern int kernel_debug; 4722 if (kernel_debug & 1) { 4723 struct proc *p = curlwp->l_proc; 4724 printf("prefetch_abort: page is already " 4725 "mapped - pte=%p *pte=%08x\n", ptep, opte); 4726 printf("prefetch_abort: pc=%08lx proc=%p " 4727 "process=%s\n", va, p, p->p_comm); 4728 printf("prefetch_abort: far=%08x fs=%x\n", 4729 cpu_faultaddress(), cpu_faultstatus()); 4730 } 4731 #ifdef DDB 4732 if (kernel_debug & 2) 4733 Debugger(); 4734 #endif 4735 rv = 1; 4736 } 4737 } 4738 #endif /* CPU_SA110 */ 4739 4740 #ifndef ARM_MMU_EXTENDED 4741 /* 4742 * If 'rv == 0' at this point, it generally indicates that there is a 4743 * stale TLB entry for the faulting address. That might be due to a 4744 * wrong setting of pmap_needs_pte_sync. So set it and retry. 4745 */ 4746 if (rv == 0 4747 && pm->pm_l1->l1_domain_use_count == 1 4748 && pmap_needs_pte_sync == 0) { 4749 pmap_needs_pte_sync = 1; 4750 PTE_SYNC(ptep); 4751 PMAPCOUNT(fixup_ptesync); 4752 rv = 1; 4753 } 4754 #endif 4755 4756 #ifndef MULTIPROCESSOR 4757 #if defined(DEBUG) || 1 4758 /* 4759 * If 'rv == 0' at this point, it generally indicates that there is a 4760 * stale TLB entry for the faulting address. This happens when two or 4761 * more processes are sharing an L1. Since we don't flush the TLB on 4762 * a context switch between such processes, we can take domain faults 4763 * for mappings which exist at the same VA in both processes. EVEN IF 4764 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 4765 * example. 4766 * 4767 * This is extremely likely to happen if pmap_enter() updated the L1 4768 * entry for a recently entered mapping. In this case, the TLB is 4769 * flushed for the new mapping, but there may still be TLB entries for 4770 * other mappings belonging to other processes in the 1MB range 4771 * covered by the L1 entry. 4772 * 4773 * Since 'rv == 0', we know that the L1 already contains the correct 4774 * value, so the fault must be due to a stale TLB entry. 4775 * 4776 * Since we always need to flush the TLB anyway in the case where we 4777 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 4778 * stale TLB entries dynamically. 4779 * 4780 * However, the above condition can ONLY happen if the current L1 is 4781 * being shared. If it happens when the L1 is unshared, it indicates 4782 * that other parts of the pmap are not doing their job WRT managing 4783 * the TLB. 4784 */ 4785 if (rv == 0 4786 #ifndef ARM_MMU_EXTENDED 4787 && pm->pm_l1->l1_domain_use_count == 1 4788 #endif 4789 && true) { 4790 #ifdef DEBUG 4791 extern int last_fault_code; 4792 #else 4793 int last_fault_code = ftype & VM_PROT_EXECUTE 4794 ? armreg_ifsr_read() 4795 : armreg_dfsr_read(); 4796 #endif 4797 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 4798 pm, va, ftype); 4799 printf("fixup: l2 %p, l2b %p, ptep %p, pte %#x\n", 4800 l2, l2b, ptep, opte); 4801 4802 #ifndef ARM_MMU_EXTENDED 4803 printf("fixup: pdep %p, pde %#x, fsr %#x\n", 4804 pdep, pde, last_fault_code); 4805 #else 4806 printf("fixup: pdep %p, pde %#x, ttbcr %#x\n", 4807 &pmap_l1_kva(pm)[l1slot], pmap_l1_kva(pm)[l1slot], 4808 armreg_ttbcr_read()); 4809 printf("fixup: fsr %#x cpm %p casid %#x contextidr %#x dacr %#x\n", 4810 last_fault_code, curcpu()->ci_pmap_cur, 4811 curcpu()->ci_pmap_asid_cur, 4812 armreg_contextidr_read(), armreg_dacr_read()); 4813 #ifdef _ARM_ARCH_7 4814 if (ftype & VM_PROT_WRITE) 4815 armreg_ats1cuw_write(va); 4816 else 4817 armreg_ats1cur_write(va); 4818 isb(); 4819 printf("fixup: par %#x\n", armreg_par_read()); 4820 #endif 4821 #endif 4822 #ifdef DDB 4823 extern int kernel_debug; 4824 4825 if (kernel_debug & 2) { 4826 pmap_release_pmap_lock(pm); 4827 #ifdef UVMHIST 4828 KERNHIST_DUMP(maphist); 4829 #endif 4830 cpu_Debugger(); 4831 pmap_acquire_pmap_lock(pm); 4832 } 4833 #endif 4834 } 4835 #endif 4836 #endif 4837 4838 #ifndef ARM_MMU_EXTENDED 4839 /* Flush the TLB in the shared L1 case - see comment above */ 4840 pmap_tlb_flush_SE(pm, va, 4841 (ftype & VM_PROT_EXECUTE) ? PVF_EXEC | PVF_REF : PVF_REF); 4842 #endif 4843 4844 rv = 1; 4845 4846 out: 4847 pmap_release_pmap_lock(pm); 4848 kpreempt_enable(); 4849 4850 return rv; 4851 } 4852 4853 /* 4854 * Routine: pmap_procwr 4855 * 4856 * Function: 4857 * Synchronize caches corresponding to [addr, addr+len) in p. 4858 * 4859 */ 4860 void 4861 pmap_procwr(struct proc *p, vaddr_t va, int len) 4862 { 4863 #ifndef ARM_MMU_EXTENDED 4864 4865 /* We only need to do anything if it is the current process. */ 4866 if (p == curproc) 4867 cpu_icache_sync_range(va, len); 4868 #endif 4869 } 4870 4871 /* 4872 * Routine: pmap_unwire 4873 * Function: Clear the wired attribute for a map/virtual-address pair. 4874 * 4875 * In/out conditions: 4876 * The mapping must already exist in the pmap. 4877 */ 4878 void 4879 pmap_unwire(pmap_t pm, vaddr_t va) 4880 { 4881 struct l2_bucket *l2b; 4882 pt_entry_t *ptep, pte; 4883 struct vm_page *pg; 4884 paddr_t pa; 4885 4886 UVMHIST_FUNC(__func__); 4887 UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx", (uintptr_t)pm, va, 0, 0); 4888 4889 kpreempt_disable(); 4890 pmap_acquire_pmap_lock(pm); 4891 4892 l2b = pmap_get_l2_bucket(pm, va); 4893 KDASSERT(l2b != NULL); 4894 4895 ptep = &l2b->l2b_kva[l2pte_index(va)]; 4896 pte = *ptep; 4897 4898 /* Extract the physical address of the page */ 4899 pa = l2pte_pa(pte); 4900 4901 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 4902 /* Update the wired bit in the pv entry for this page. */ 4903 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 4904 4905 pmap_acquire_page_lock(md); 4906 (void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0); 4907 pmap_release_page_lock(md); 4908 } 4909 4910 pmap_release_pmap_lock(pm); 4911 kpreempt_enable(); 4912 4913 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 4914 } 4915 4916 #ifdef ARM_MMU_EXTENDED 4917 void 4918 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l) 4919 { 4920 UVMHIST_FUNC(__func__); 4921 struct cpu_info * const ci = curcpu(); 4922 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4923 4924 UVMHIST_CALLARGS(maphist, "pm %#jx (pm->pm_l1_pa %08jx asid %ju)", 4925 (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0); 4926 4927 /* 4928 * Assume that TTBR1 has only global mappings and TTBR0 only 4929 * has non-global mappings. To prevent speculation from doing 4930 * evil things we disable translation table walks using TTBR0 4931 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 4932 * Once both are set, table walks are reenabled. 4933 */ 4934 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4935 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4936 isb(); 4937 4938 pmap_tlb_asid_acquire(pm, l); 4939 4940 cpu_setttb(pm->pm_l1_pa, pai->pai_asid); 4941 /* 4942 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 4943 * have been updated. 4944 */ 4945 isb(); 4946 4947 if (pm != pmap_kernel()) { 4948 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 4949 } 4950 cpu_cpwait(); 4951 4952 KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u", 4953 ci->ci_pmap_asid_cur, pai->pai_asid); 4954 ci->ci_pmap_cur = pm; 4955 } 4956 4957 void 4958 pmap_md_pdetab_deactivate(pmap_t pm) 4959 { 4960 4961 UVMHIST_FUNC(__func__); 4962 UVMHIST_CALLARGS(maphist, "pm %#jx", (uintptr_t)pm, 0, 0, 0); 4963 4964 kpreempt_disable(); 4965 struct cpu_info * const ci = curcpu(); 4966 /* 4967 * Disable translation table walks from TTBR0 while no pmap has been 4968 * activated. 4969 */ 4970 const uint32_t old_ttbcr = armreg_ttbcr_read(); 4971 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 4972 isb(); 4973 pmap_tlb_asid_deactivate(pm); 4974 cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID); 4975 isb(); 4976 4977 ci->ci_pmap_cur = pmap_kernel(); 4978 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 4979 ci->ci_pmap_asid_cur); 4980 kpreempt_enable(); 4981 } 4982 #endif 4983 4984 4985 #if defined(EFI_RUNTIME) 4986 void 4987 pmap_activate_efirt(void) 4988 { 4989 struct pmap * const pm = &efirt_pmap; 4990 4991 UVMHIST_FUNC(__func__); 4992 UVMHIST_CALLARGS(maphist, " (pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 4993 4994 KASSERT(kpreempt_disabled()); 4995 4996 struct cpu_info * const ci = curcpu(); 4997 struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci)); 4998 4999 PMAPCOUNT(activations); 5000 5001 /* 5002 * Assume that TTBR1 has only global mappings and TTBR0 only 5003 * has non-global mappings. To prevent speculation from doing 5004 * evil things we disable translation table walks using TTBR0 5005 * before setting the CONTEXTIDR (ASID) or new TTBR0 value. 5006 * Once both are set, table walks are reenabled. 5007 */ 5008 const uint32_t old_ttbcr = armreg_ttbcr_read(); 5009 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 5010 isb(); 5011 5012 armreg_contextidr_write(pai->pai_asid); 5013 armreg_ttbr_write(pm->pm_l1_pa | 5014 (ci->ci_mpidr ? TTBR_MPATTR : TTBR_UPATTR)); 5015 /* 5016 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0 5017 * have been updated. 5018 */ 5019 isb(); 5020 5021 armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0); 5022 5023 ci->ci_pmap_asid_cur = pai->pai_asid; 5024 ci->ci_pmap_cur = pm; 5025 5026 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5027 } 5028 5029 #endif 5030 5031 5032 void 5033 pmap_activate(struct lwp *l) 5034 { 5035 extern int block_userspace_access; 5036 pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap; 5037 5038 UVMHIST_FUNC(__func__); 5039 UVMHIST_CALLARGS(maphist, "l=%#jx pm=%#jx", (uintptr_t)l, 5040 (uintptr_t)npm, 0, 0); 5041 5042 #ifdef ARM_MMU_EXTENDED 5043 KASSERT(kpreempt_disabled()); 5044 #endif 5045 5046 struct cpu_info * const ci = curcpu(); 5047 5048 /* 5049 * If activating a non-current lwp or the current lwp is 5050 * already active, just return. 5051 */ 5052 if (false 5053 || l != curlwp 5054 #ifdef ARM_MMU_EXTENDED 5055 || (ci->ci_pmap_cur == npm && 5056 (npm == pmap_kernel() 5057 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */)) 5058 #else 5059 || npm->pm_activated == true 5060 #endif 5061 || false) { 5062 UVMHIST_LOG(maphist, " <-- (same pmap)", (uintptr_t)curlwp, 5063 (uintptr_t)l, 0, 0); 5064 return; 5065 } 5066 5067 #ifndef ARM_MMU_EXTENDED 5068 const uint32_t ndacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 5069 | (DOMAIN_CLIENT << (pmap_domain(npm) * 2)); 5070 5071 /* 5072 * If TTB and DACR are unchanged, short-circuit all the 5073 * TLB/cache management stuff. 5074 */ 5075 pmap_t opm = ci->ci_lastlwp 5076 ? ci->ci_lastlwp->l_proc->p_vmspace->vm_map.pmap 5077 : NULL; 5078 if (opm != NULL) { 5079 uint32_t odacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) 5080 | (DOMAIN_CLIENT << (pmap_domain(opm) * 2)); 5081 5082 if (opm->pm_l1 == npm->pm_l1 && odacr == ndacr) 5083 goto all_done; 5084 } 5085 #endif /* !ARM_MMU_EXTENDED */ 5086 5087 PMAPCOUNT(activations); 5088 block_userspace_access = 1; 5089 5090 #ifndef ARM_MMU_EXTENDED 5091 /* 5092 * If switching to a user vmspace which is different to the 5093 * most recent one, and the most recent one is potentially 5094 * live in the cache, we must write-back and invalidate the 5095 * entire cache. 5096 */ 5097 pmap_t rpm = ci->ci_pmap_lastuser; 5098 5099 /* 5100 * XXXSCW: There's a corner case here which can leave turds in the 5101 * cache as reported in kern/41058. They're probably left over during 5102 * tear-down and switching away from an exiting process. Until the root 5103 * cause is identified and fixed, zap the cache when switching pmaps. 5104 * This will result in a few unnecessary cache flushes, but that's 5105 * better than silently corrupting data. 5106 */ 5107 #if 0 5108 if (npm != pmap_kernel() && rpm && npm != rpm && 5109 rpm->pm_cstate.cs_cache) { 5110 rpm->pm_cstate.cs_cache = 0; 5111 #ifdef PMAP_CACHE_VIVT 5112 cpu_idcache_wbinv_all(); 5113 #endif 5114 } 5115 #else 5116 if (rpm) { 5117 rpm->pm_cstate.cs_cache = 0; 5118 if (npm == pmap_kernel()) 5119 ci->ci_pmap_lastuser = NULL; 5120 #ifdef PMAP_CACHE_VIVT 5121 cpu_idcache_wbinv_all(); 5122 #endif 5123 } 5124 #endif 5125 5126 /* No interrupts while we frob the TTB/DACR */ 5127 uint32_t oldirqstate = disable_interrupts(IF32_bits); 5128 #endif /* !ARM_MMU_EXTENDED */ 5129 5130 #ifndef ARM_HAS_VBAR 5131 /* 5132 * For ARM_VECTORS_LOW, we MUST, I repeat, MUST fix up the L1 5133 * entry corresponding to 'vector_page' in the incoming L1 table 5134 * before switching to it otherwise subsequent interrupts/exceptions 5135 * (including domain faults!) will jump into hyperspace. 5136 */ 5137 if (npm->pm_pl1vec != NULL) { 5138 cpu_tlb_flushID_SE((u_int)vector_page); 5139 cpu_cpwait(); 5140 *npm->pm_pl1vec = npm->pm_l1vec; 5141 PTE_SYNC(npm->pm_pl1vec); 5142 } 5143 #endif 5144 5145 #ifdef ARM_MMU_EXTENDED 5146 pmap_md_pdetab_activate(npm, l); 5147 #else 5148 cpu_domains(ndacr); 5149 if (npm == pmap_kernel() || npm == rpm) { 5150 /* 5151 * Switching to a kernel thread, or back to the 5152 * same user vmspace as before... Simply update 5153 * the TTB (no TLB flush required) 5154 */ 5155 cpu_setttb(npm->pm_l1->l1_physaddr, false); 5156 cpu_cpwait(); 5157 } else { 5158 /* 5159 * Otherwise, update TTB and flush TLB 5160 */ 5161 cpu_context_switch(npm->pm_l1->l1_physaddr); 5162 if (rpm != NULL) 5163 rpm->pm_cstate.cs_tlb = 0; 5164 } 5165 5166 restore_interrupts(oldirqstate); 5167 #endif /* ARM_MMU_EXTENDED */ 5168 5169 block_userspace_access = 0; 5170 5171 #ifndef ARM_MMU_EXTENDED 5172 all_done: 5173 /* 5174 * The new pmap is resident. Make sure it's marked 5175 * as resident in the cache/TLB. 5176 */ 5177 npm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5178 if (npm != pmap_kernel()) 5179 ci->ci_pmap_lastuser = npm; 5180 5181 /* The old pmap is not longer active */ 5182 if (opm != npm) { 5183 if (opm != NULL) 5184 opm->pm_activated = false; 5185 5186 /* But the new one is */ 5187 npm->pm_activated = true; 5188 } 5189 ci->ci_pmap_cur = npm; 5190 #endif 5191 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5192 } 5193 5194 5195 void 5196 pmap_deactivate(struct lwp *l) 5197 { 5198 pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap; 5199 5200 UVMHIST_FUNC(__func__); 5201 UVMHIST_CALLARGS(maphist, "l=%#jx (pm=%#jx)", (uintptr_t)l, 5202 (uintptr_t)pm, 0, 0); 5203 5204 #ifdef ARM_MMU_EXTENDED 5205 KASSERT(kpreempt_disabled()); 5206 pmap_md_pdetab_deactivate(pm); 5207 #else 5208 /* 5209 * If the process is exiting, make sure pmap_activate() does 5210 * a full MMU context-switch and cache flush, which we might 5211 * otherwise skip. See PR port-arm/38950. 5212 */ 5213 if (l->l_proc->p_sflag & PS_WEXIT) 5214 curcpu()->ci_lastlwp = NULL; 5215 5216 pm->pm_activated = false; 5217 #endif 5218 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5219 } 5220 5221 5222 #if defined(EFI_RUNTIME) 5223 void 5224 pmap_deactivate_efirt(void) 5225 { 5226 UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist); 5227 5228 KASSERT(kpreempt_disabled()); 5229 struct cpu_info * const ci = curcpu(); 5230 5231 /* 5232 * Disable translation table walks from TTBR0 while no pmap has been 5233 * activated. 5234 */ 5235 const uint32_t old_ttbcr = armreg_ttbcr_read(); 5236 armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0); 5237 isb(); 5238 5239 armreg_contextidr_write(KERNEL_PID); 5240 isb(); 5241 5242 KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u", 5243 ci->ci_pmap_asid_cur); 5244 5245 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5246 } 5247 #endif 5248 5249 5250 void 5251 pmap_update(pmap_t pm) 5252 { 5253 5254 UVMHIST_FUNC(__func__); 5255 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5256 pm->pm_remove_all, 0, 0); 5257 5258 #ifndef ARM_MMU_EXTENDED 5259 if (pm->pm_remove_all) { 5260 /* 5261 * Finish up the pmap_remove_all() optimisation by flushing 5262 * the TLB. 5263 */ 5264 pmap_tlb_flushID(pm); 5265 pm->pm_remove_all = false; 5266 } 5267 5268 if (pmap_is_current(pm)) { 5269 /* 5270 * If we're dealing with a current userland pmap, move its L1 5271 * to the end of the LRU. 5272 */ 5273 if (pm != pmap_kernel()) 5274 pmap_use_l1(pm); 5275 5276 /* 5277 * We can assume we're done with frobbing the cache/tlb for 5278 * now. Make sure any future pmap ops don't skip cache/tlb 5279 * flushes. 5280 */ 5281 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5282 } 5283 #else 5284 5285 kpreempt_disable(); 5286 #if defined(MULTIPROCESSOR) && PMAP_TLB_MAX > 1 5287 u_int pending = atomic_swap_uint(&pmap->pm_shootdown_pending, 0); 5288 if (pending && pmap_tlb_shootdown_bystanders(pmap)) { 5289 PMAP_COUNT(shootdown_ipis); 5290 } 5291 #endif 5292 5293 /* 5294 * If pmap_remove_all was called, we deactivated ourselves and released 5295 * our ASID. Now we have to reactivate ourselves. 5296 */ 5297 if (__predict_false(pm->pm_remove_all)) { 5298 pm->pm_remove_all = false; 5299 5300 KASSERT(pm != pmap_kernel()); 5301 pmap_md_pdetab_activate(pm, curlwp); 5302 } 5303 5304 if (arm_has_mpext_p) 5305 armreg_bpiallis_write(0); 5306 else 5307 armreg_bpiall_write(0); 5308 5309 kpreempt_enable(); 5310 5311 KASSERTMSG(pm == pmap_kernel() 5312 || curcpu()->ci_pmap_cur != pm 5313 || pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur, 5314 "pmap/asid %p/%#x != %s cur pmap/asid %p/%#x", pm, 5315 pm->pm_pai[0].pai_asid, curcpu()->ci_data.cpu_name, 5316 curcpu()->ci_pmap_cur, curcpu()->ci_pmap_asid_cur); 5317 #endif 5318 5319 PMAPCOUNT(updates); 5320 5321 /* 5322 * make sure TLB/cache operations have completed. 5323 */ 5324 cpu_cpwait(); 5325 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5326 } 5327 5328 bool 5329 pmap_remove_all(pmap_t pm) 5330 { 5331 5332 UVMHIST_FUNC(__func__); 5333 UVMHIST_CALLARGS(maphist, "(pm=%#jx)", (uintptr_t)pm, 0, 0, 0); 5334 5335 KASSERT(pm != pmap_kernel()); 5336 5337 kpreempt_disable(); 5338 /* 5339 * The vmspace described by this pmap is about to be torn down. 5340 * Until pmap_update() is called, UVM will only make calls 5341 * to pmap_remove(). We can make life much simpler by flushing 5342 * the cache now, and deferring TLB invalidation to pmap_update(). 5343 */ 5344 #ifdef PMAP_CACHE_VIVT 5345 pmap_cache_wbinv_all(pm, PVF_EXEC); 5346 #endif 5347 #ifdef ARM_MMU_EXTENDED 5348 #ifdef MULTIPROCESSOR 5349 struct cpu_info * const ci = curcpu(); 5350 // This should be the last CPU with this pmap onproc 5351 KASSERT(!kcpuset_isotherset(pm->pm_onproc, cpu_index(ci))); 5352 if (kcpuset_isset(pm->pm_onproc, cpu_index(ci))) 5353 #endif 5354 pmap_tlb_asid_deactivate(pm); 5355 #ifdef MULTIPROCESSOR 5356 KASSERT(kcpuset_iszero(pm->pm_onproc)); 5357 #endif 5358 5359 pmap_tlb_asid_release_all(pm); 5360 #endif 5361 pm->pm_remove_all = true; 5362 kpreempt_enable(); 5363 5364 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5365 return false; 5366 } 5367 5368 /* 5369 * Retire the given physical map from service. 5370 * Should only be called if the map contains no valid mappings. 5371 */ 5372 void 5373 pmap_destroy(pmap_t pm) 5374 { 5375 UVMHIST_FUNC(__func__); 5376 UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm, 5377 pm ? pm->pm_remove_all : 0, 0, 0); 5378 5379 if (pm == NULL) 5380 return; 5381 5382 if (pm->pm_remove_all) { 5383 #ifdef ARM_MMU_EXTENDED 5384 pmap_tlb_asid_release_all(pm); 5385 #else 5386 pmap_tlb_flushID(pm); 5387 #endif 5388 pm->pm_remove_all = false; 5389 } 5390 5391 /* 5392 * Drop reference count 5393 */ 5394 membar_release(); 5395 if (atomic_dec_uint_nv(&pm->pm_refs) > 0) { 5396 #ifndef ARM_MMU_EXTENDED 5397 if (pmap_is_current(pm)) { 5398 if (pm != pmap_kernel()) 5399 pmap_use_l1(pm); 5400 pm->pm_cstate.cs_all = PMAP_CACHE_STATE_ALL; 5401 } 5402 #endif 5403 return; 5404 } 5405 membar_acquire(); 5406 5407 /* 5408 * reference count is zero, free pmap resources and then free pmap. 5409 */ 5410 5411 #ifndef ARM_HAS_VBAR 5412 if (vector_page < KERNEL_BASE) { 5413 KDASSERT(!pmap_is_current(pm)); 5414 5415 /* Remove the vector page mapping */ 5416 pmap_remove(pm, vector_page, vector_page + PAGE_SIZE); 5417 pmap_update(pm); 5418 } 5419 #endif 5420 5421 pmap_free_l1(pm); 5422 5423 #ifdef ARM_MMU_EXTENDED 5424 #ifdef MULTIPROCESSOR 5425 kcpuset_destroy(pm->pm_active); 5426 kcpuset_destroy(pm->pm_onproc); 5427 #endif 5428 #else 5429 struct cpu_info * const ci = curcpu(); 5430 if (ci->ci_pmap_lastuser == pm) 5431 ci->ci_pmap_lastuser = NULL; 5432 #endif 5433 5434 mutex_destroy(&pm->pm_lock); 5435 pool_cache_put(&pmap_cache, pm); 5436 UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0); 5437 } 5438 5439 5440 /* 5441 * void pmap_reference(pmap_t pm) 5442 * 5443 * Add a reference to the specified pmap. 5444 */ 5445 void 5446 pmap_reference(pmap_t pm) 5447 { 5448 5449 if (pm == NULL) 5450 return; 5451 5452 #ifndef ARM_MMU_EXTENDED 5453 pmap_use_l1(pm); 5454 #endif 5455 5456 atomic_inc_uint(&pm->pm_refs); 5457 } 5458 5459 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 5460 5461 static struct evcnt pmap_prefer_nochange_ev = 5462 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "nochange"); 5463 static struct evcnt pmap_prefer_change_ev = 5464 EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "pmap prefer", "change"); 5465 5466 EVCNT_ATTACH_STATIC(pmap_prefer_change_ev); 5467 EVCNT_ATTACH_STATIC(pmap_prefer_nochange_ev); 5468 5469 void 5470 pmap_prefer(vaddr_t hint, vaddr_t *vap, int td) 5471 { 5472 vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1); 5473 vaddr_t va = *vap; 5474 vaddr_t diff = (hint - va) & mask; 5475 if (diff == 0) { 5476 pmap_prefer_nochange_ev.ev_count++; 5477 } else { 5478 pmap_prefer_change_ev.ev_count++; 5479 if (__predict_false(td)) 5480 va -= mask + 1; 5481 *vap = va + diff; 5482 } 5483 } 5484 #endif /* ARM_MMU_V6 | ARM_MMU_V7 */ 5485 5486 /* 5487 * pmap_zero_page() 5488 * 5489 * Zero a given physical page by mapping it at a page hook point. 5490 * In doing the zero page op, the page we zero is mapped cachable, as with 5491 * StrongARM accesses to non-cached pages are non-burst making writing 5492 * _any_ bulk data very slow. 5493 */ 5494 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5495 void 5496 pmap_zero_page_generic(paddr_t pa) 5497 { 5498 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5499 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5500 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5501 #endif 5502 #if defined(PMAP_CACHE_VIPT) 5503 /* Choose the last page color it had, if any */ 5504 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5505 #else 5506 const vsize_t va_offset = 0; 5507 #endif 5508 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5509 /* 5510 * Is this page mapped at its natural color? 5511 * If we have all of memory mapped, then just convert PA to VA. 5512 */ 5513 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5514 || va_offset == (pa & arm_cache_prefer_mask); 5515 const vaddr_t vdstp = okcolor 5516 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5517 : cpu_cdstp(va_offset); 5518 #else 5519 const bool okcolor = false; 5520 const vaddr_t vdstp = cpu_cdstp(va_offset); 5521 #endif 5522 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5523 5524 5525 #ifdef DEBUG 5526 if (!SLIST_EMPTY(&md->pvh_list)) 5527 panic("pmap_zero_page: page has mappings"); 5528 #endif 5529 5530 KDASSERT((pa & PGOFSET) == 0); 5531 5532 if (!okcolor) { 5533 /* 5534 * Hook in the page, zero it, and purge the cache for that 5535 * zeroed page. Invalidate the TLB as needed. 5536 */ 5537 const pt_entry_t npte = L2_S_PROTO | pa | pte_l2_s_cache_mode 5538 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 5539 l2pte_set(ptep, npte, 0); 5540 PTE_SYNC(ptep); 5541 cpu_tlb_flushD_SE(vdstp); 5542 cpu_cpwait(); 5543 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) \ 5544 && !defined(ARM_MMU_EXTENDED) 5545 /* 5546 * If we are direct-mapped and our color isn't ok, then before 5547 * we bzero the page invalidate its contents from the cache and 5548 * reset the color to its natural color. 5549 */ 5550 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5551 md->pvh_attrs &= ~arm_cache_prefer_mask; 5552 md->pvh_attrs |= (pa & arm_cache_prefer_mask); 5553 #endif 5554 } 5555 bzero_page(vdstp); 5556 if (!okcolor) { 5557 /* 5558 * Unmap the page. 5559 */ 5560 l2pte_reset(ptep); 5561 PTE_SYNC(ptep); 5562 cpu_tlb_flushD_SE(vdstp); 5563 #ifdef PMAP_CACHE_VIVT 5564 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5565 #endif 5566 } 5567 #ifdef PMAP_CACHE_VIPT 5568 /* 5569 * This page is now cache resident so it now has a page color. 5570 * Any contents have been obliterated so clear the EXEC flag. 5571 */ 5572 #ifndef ARM_MMU_EXTENDED 5573 if (!pmap_is_page_colored_p(md)) { 5574 PMAPCOUNT(vac_color_new); 5575 md->pvh_attrs |= PVF_COLORED; 5576 } 5577 md->pvh_attrs |= PVF_DIRTY; 5578 #endif 5579 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5580 md->pvh_attrs &= ~PVF_EXEC; 5581 PMAPCOUNT(exec_discarded_zero); 5582 } 5583 #endif 5584 } 5585 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5586 5587 #if ARM_MMU_XSCALE == 1 5588 void 5589 pmap_zero_page_xscale(paddr_t pa) 5590 { 5591 #ifdef DEBUG 5592 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 5593 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5594 5595 if (!SLIST_EMPTY(&md->pvh_list)) 5596 panic("pmap_zero_page: page has mappings"); 5597 #endif 5598 5599 KDASSERT((pa & PGOFSET) == 0); 5600 5601 /* 5602 * Hook in the page, zero it, and purge the cache for that 5603 * zeroed page. Invalidate the TLB as needed. 5604 */ 5605 5606 pt_entry_t npte = L2_S_PROTO | pa | 5607 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 5608 L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5609 l2pte_set(cdst_pte, npte, 0); 5610 PTE_SYNC(cdst_pte); 5611 cpu_tlb_flushD_SE(cdstp); 5612 cpu_cpwait(); 5613 bzero_page(cdstp); 5614 xscale_cache_clean_minidata(); 5615 l2pte_reset(cdst_pte); 5616 PTE_SYNC(cdst_pte); 5617 } 5618 #endif /* ARM_MMU_XSCALE == 1 */ 5619 5620 /* pmap_pageidlezero() 5621 * 5622 * The same as above, except that we assume that the page is not 5623 * mapped. This means we never have to flush the cache first. Called 5624 * from the idle loop. 5625 */ 5626 bool 5627 pmap_pageidlezero(paddr_t pa) 5628 { 5629 bool rv = true; 5630 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5631 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 5632 struct vm_page_md *md = VM_PAGE_TO_MD(pg); 5633 #endif 5634 #ifdef PMAP_CACHE_VIPT 5635 /* Choose the last page color it had, if any */ 5636 const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask; 5637 #else 5638 const vsize_t va_offset = 0; 5639 #endif 5640 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 5641 bool okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5642 || va_offset == (pa & arm_cache_prefer_mask); 5643 const vaddr_t vdstp = okcolor 5644 ? pmap_direct_mapped_phys(pa, &okcolor, cpu_cdstp(va_offset)) 5645 : cpu_cdstp(va_offset); 5646 #else 5647 const bool okcolor = false; 5648 const vaddr_t vdstp = cpu_cdstp(va_offset); 5649 #endif 5650 pt_entry_t * const ptep = cpu_cdst_pte(va_offset); 5651 5652 5653 #ifdef DEBUG 5654 if (!SLIST_EMPTY(&md->pvh_list)) 5655 panic("pmap_pageidlezero: page has mappings"); 5656 #endif 5657 5658 KDASSERT((pa & PGOFSET) == 0); 5659 5660 if (!okcolor) { 5661 /* 5662 * Hook in the page, zero it, and purge the cache for that 5663 * zeroed page. Invalidate the TLB as needed. 5664 */ 5665 const pt_entry_t npte = L2_S_PROTO | pa | 5666 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5667 l2pte_set(ptep, npte, 0); 5668 PTE_SYNC(ptep); 5669 cpu_tlb_flushD_SE(vdstp); 5670 cpu_cpwait(); 5671 } 5672 5673 uint64_t *ptr = (uint64_t *)vdstp; 5674 for (size_t i = 0; i < PAGE_SIZE / sizeof(*ptr); i++) { 5675 if (sched_curcpu_runnable_p() != 0) { 5676 /* 5677 * A process has become ready. Abort now, 5678 * so we don't keep it waiting while we 5679 * do slow memory access to finish this 5680 * page. 5681 */ 5682 rv = false; 5683 break; 5684 } 5685 *ptr++ = 0; 5686 } 5687 5688 #ifdef PMAP_CACHE_VIVT 5689 if (rv) 5690 /* 5691 * if we aborted we'll rezero this page again later so don't 5692 * purge it unless we finished it 5693 */ 5694 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5695 #elif defined(PMAP_CACHE_VIPT) 5696 /* 5697 * This page is now cache resident so it now has a page color. 5698 * Any contents have been obliterated so clear the EXEC flag. 5699 */ 5700 #ifndef ARM_MMU_EXTENDED 5701 if (!pmap_is_page_colored_p(md)) { 5702 PMAPCOUNT(vac_color_new); 5703 md->pvh_attrs |= PVF_COLORED; 5704 } 5705 #endif 5706 if (PV_IS_EXEC_P(md->pvh_attrs)) { 5707 md->pvh_attrs &= ~PVF_EXEC; 5708 PMAPCOUNT(exec_discarded_zero); 5709 } 5710 #endif 5711 /* 5712 * Unmap the page. 5713 */ 5714 if (!okcolor) { 5715 l2pte_reset(ptep); 5716 PTE_SYNC(ptep); 5717 cpu_tlb_flushD_SE(vdstp); 5718 } 5719 5720 return rv; 5721 } 5722 5723 /* 5724 * pmap_copy_page() 5725 * 5726 * Copy one physical page into another, by mapping the pages into 5727 * hook points. The same comment regarding cachability as in 5728 * pmap_zero_page also applies here. 5729 */ 5730 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 5731 void 5732 pmap_copy_page_generic(paddr_t src, paddr_t dst) 5733 { 5734 struct vm_page * const src_pg = PHYS_TO_VM_PAGE(src); 5735 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5736 #if defined(PMAP_CACHE_VIPT) || defined(DEBUG) 5737 struct vm_page * const dst_pg = PHYS_TO_VM_PAGE(dst); 5738 struct vm_page_md *dst_md = VM_PAGE_TO_MD(dst_pg); 5739 #endif 5740 #ifdef PMAP_CACHE_VIPT 5741 const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask; 5742 const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask; 5743 #else 5744 const vsize_t src_va_offset = 0; 5745 const vsize_t dst_va_offset = 0; 5746 #endif 5747 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 5748 /* 5749 * Is this page mapped at its natural color? 5750 * If we have all of memory mapped, then just convert PA to VA. 5751 */ 5752 bool src_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5753 || src_va_offset == (src & arm_cache_prefer_mask); 5754 bool dst_okcolor = arm_pcache.dcache_type == CACHE_TYPE_PIPT 5755 || dst_va_offset == (dst & arm_cache_prefer_mask); 5756 const vaddr_t vsrcp = src_okcolor 5757 ? pmap_direct_mapped_phys(src, &src_okcolor, 5758 cpu_csrcp(src_va_offset)) 5759 : cpu_csrcp(src_va_offset); 5760 const vaddr_t vdstp = pmap_direct_mapped_phys(dst, &dst_okcolor, 5761 cpu_cdstp(dst_va_offset)); 5762 #else 5763 const bool src_okcolor = false; 5764 const bool dst_okcolor = false; 5765 const vaddr_t vsrcp = cpu_csrcp(src_va_offset); 5766 const vaddr_t vdstp = cpu_cdstp(dst_va_offset); 5767 #endif 5768 pt_entry_t * const src_ptep = cpu_csrc_pte(src_va_offset); 5769 pt_entry_t * const dst_ptep = cpu_cdst_pte(dst_va_offset); 5770 5771 #ifdef DEBUG 5772 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5773 panic("pmap_copy_page: dst page has mappings"); 5774 #endif 5775 5776 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5777 KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC)); 5778 #endif 5779 KDASSERT((src & PGOFSET) == 0); 5780 KDASSERT((dst & PGOFSET) == 0); 5781 5782 /* 5783 * Clean the source page. Hold the source page's lock for 5784 * the duration of the copy so that no other mappings can 5785 * be created while we have a potentially aliased mapping. 5786 */ 5787 #ifdef PMAP_CACHE_VIVT 5788 pmap_acquire_page_lock(src_md); 5789 (void) pmap_clean_page(src_md, true); 5790 pmap_release_page_lock(src_md); 5791 #endif 5792 5793 /* 5794 * Map the pages into the page hook points, copy them, and purge 5795 * the cache for the appropriate page. Invalidate the TLB 5796 * as required. 5797 */ 5798 if (!src_okcolor) { 5799 const pt_entry_t nsrc_pte = L2_S_PROTO 5800 | src 5801 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 5802 | ((src_md->pvh_attrs & PVF_NC) ? 0 : pte_l2_s_cache_mode) 5803 #else // defined(PMAP_CACHE_VIVT) || defined(ARM_MMU_EXTENDED) 5804 | pte_l2_s_cache_mode 5805 #endif 5806 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ); 5807 l2pte_set(src_ptep, nsrc_pte, 0); 5808 PTE_SYNC(src_ptep); 5809 cpu_tlb_flushD_SE(vsrcp); 5810 cpu_cpwait(); 5811 } 5812 if (!dst_okcolor) { 5813 const pt_entry_t ndst_pte = L2_S_PROTO | dst | 5814 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 5815 l2pte_set(dst_ptep, ndst_pte, 0); 5816 PTE_SYNC(dst_ptep); 5817 cpu_tlb_flushD_SE(vdstp); 5818 cpu_cpwait(); 5819 #if defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) && defined(PMAP_CACHE_VIPT) 5820 /* 5821 * If we are direct-mapped and our color isn't ok, then before 5822 * we bcopy to the new page invalidate its contents from the 5823 * cache and reset its color to its natural color. 5824 */ 5825 cpu_dcache_inv_range(vdstp, PAGE_SIZE); 5826 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5827 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5828 #endif 5829 } 5830 bcopy_page(vsrcp, vdstp); 5831 #ifdef PMAP_CACHE_VIVT 5832 cpu_dcache_inv_range(vsrcp, PAGE_SIZE); 5833 cpu_dcache_wbinv_range(vdstp, PAGE_SIZE); 5834 #endif 5835 /* 5836 * Unmap the pages. 5837 */ 5838 if (!src_okcolor) { 5839 l2pte_reset(src_ptep); 5840 PTE_SYNC(src_ptep); 5841 cpu_tlb_flushD_SE(vsrcp); 5842 cpu_cpwait(); 5843 } 5844 if (!dst_okcolor) { 5845 l2pte_reset(dst_ptep); 5846 PTE_SYNC(dst_ptep); 5847 cpu_tlb_flushD_SE(vdstp); 5848 cpu_cpwait(); 5849 } 5850 #ifdef PMAP_CACHE_VIPT 5851 /* 5852 * Now that the destination page is in the cache, mark it as colored. 5853 * If this was an exec page, discard it. 5854 */ 5855 pmap_acquire_page_lock(dst_md); 5856 #ifndef ARM_MMU_EXTENDED 5857 if (arm_pcache.cache_type == CACHE_TYPE_PIPT) { 5858 dst_md->pvh_attrs &= ~arm_cache_prefer_mask; 5859 dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask); 5860 } 5861 if (!pmap_is_page_colored_p(dst_md)) { 5862 PMAPCOUNT(vac_color_new); 5863 dst_md->pvh_attrs |= PVF_COLORED; 5864 } 5865 dst_md->pvh_attrs |= PVF_DIRTY; 5866 #endif 5867 if (PV_IS_EXEC_P(dst_md->pvh_attrs)) { 5868 dst_md->pvh_attrs &= ~PVF_EXEC; 5869 PMAPCOUNT(exec_discarded_copy); 5870 } 5871 pmap_release_page_lock(dst_md); 5872 #endif 5873 } 5874 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 5875 5876 #if ARM_MMU_XSCALE == 1 5877 void 5878 pmap_copy_page_xscale(paddr_t src, paddr_t dst) 5879 { 5880 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 5881 struct vm_page_md *src_md = VM_PAGE_TO_MD(src_pg); 5882 #ifdef DEBUG 5883 struct vm_page_md *dst_md = VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst)); 5884 5885 if (!SLIST_EMPTY(&dst_md->pvh_list)) 5886 panic("pmap_copy_page: dst page has mappings"); 5887 #endif 5888 5889 KDASSERT((src & PGOFSET) == 0); 5890 KDASSERT((dst & PGOFSET) == 0); 5891 5892 /* 5893 * Clean the source page. Hold the source page's lock for 5894 * the duration of the copy so that no other mappings can 5895 * be created while we have a potentially aliased mapping. 5896 */ 5897 #ifdef PMAP_CACHE_VIVT 5898 pmap_acquire_page_lock(src_md); 5899 (void) pmap_clean_page(src_md, true); 5900 pmap_release_page_lock(src_md); 5901 #endif 5902 5903 /* 5904 * Map the pages into the page hook points, copy them, and purge 5905 * the cache for the appropriate page. Invalidate the TLB 5906 * as required. 5907 */ 5908 const pt_entry_t nsrc_pte = L2_S_PROTO | src 5909 | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 5910 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5911 l2pte_set(csrc_pte, nsrc_pte, 0); 5912 PTE_SYNC(csrc_pte); 5913 5914 const pt_entry_t ndst_pte = L2_S_PROTO | dst 5915 | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) 5916 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */ 5917 l2pte_set(cdst_pte, ndst_pte, 0); 5918 PTE_SYNC(cdst_pte); 5919 5920 cpu_tlb_flushD_SE(csrcp); 5921 cpu_tlb_flushD_SE(cdstp); 5922 cpu_cpwait(); 5923 bcopy_page(csrcp, cdstp); 5924 xscale_cache_clean_minidata(); 5925 l2pte_reset(csrc_pte); 5926 l2pte_reset(cdst_pte); 5927 PTE_SYNC(csrc_pte); 5928 PTE_SYNC(cdst_pte); 5929 } 5930 #endif /* ARM_MMU_XSCALE == 1 */ 5931 5932 /* 5933 * void pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5934 * 5935 * Return the start and end addresses of the kernel's virtual space. 5936 * These values are setup in pmap_bootstrap and are updated as pages 5937 * are allocated. 5938 */ 5939 void 5940 pmap_virtual_space(vaddr_t *start, vaddr_t *end) 5941 { 5942 *start = virtual_avail; 5943 *end = virtual_end; 5944 } 5945 5946 /* 5947 * Helper function for pmap_grow_l2_bucket() 5948 */ 5949 static inline int 5950 pmap_grow_map(vaddr_t va, paddr_t *pap) 5951 { 5952 paddr_t pa; 5953 5954 KASSERT((va & PGOFSET) == 0); 5955 5956 if (uvm.page_init_done == false) { 5957 #ifdef PMAP_STEAL_MEMORY 5958 pv_addr_t pv; 5959 pmap_boot_pagealloc(PAGE_SIZE, 5960 #ifdef PMAP_CACHE_VIPT 5961 arm_cache_prefer_mask, 5962 va & arm_cache_prefer_mask, 5963 #else 5964 0, 0, 5965 #endif 5966 &pv); 5967 pa = pv.pv_pa; 5968 #else 5969 if (uvm_page_physget(&pa) == false) 5970 return 1; 5971 #endif /* PMAP_STEAL_MEMORY */ 5972 } else { 5973 struct vm_page *pg; 5974 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_USERESERVE); 5975 if (pg == NULL) 5976 return 1; 5977 pa = VM_PAGE_TO_PHYS(pg); 5978 /* 5979 * This new page must not have any mappings. 5980 */ 5981 struct vm_page_md *md __diagused = VM_PAGE_TO_MD(pg); 5982 KASSERT(SLIST_EMPTY(&md->pvh_list)); 5983 } 5984 5985 /* 5986 * Enter it via pmap_kenter_pa and let that routine do the hard work. 5987 */ 5988 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 5989 PMAP_KMPAGE | PMAP_PTE); 5990 5991 if (pap) 5992 *pap = pa; 5993 5994 PMAPCOUNT(pt_mappings); 5995 5996 const pmap_t kpm __diagused = pmap_kernel(); 5997 struct l2_bucket * const l2b __diagused = pmap_get_l2_bucket(kpm, va); 5998 KASSERT(l2b != NULL); 5999 6000 pt_entry_t * const ptep __diagused = &l2b->l2b_kva[l2pte_index(va)]; 6001 const pt_entry_t pte __diagused = *ptep; 6002 KASSERT(l2pte_valid_p(pte)); 6003 KASSERT((pte & L2_S_CACHE_MASK) == pte_l2_s_cache_mode_pt); 6004 6005 memset((void *)va, 0, PAGE_SIZE); 6006 6007 return 0; 6008 } 6009 6010 /* 6011 * This is the same as pmap_alloc_l2_bucket(), except that it is only 6012 * used by pmap_growkernel(). 6013 */ 6014 static inline struct l2_bucket * 6015 pmap_grow_l2_bucket(pmap_t pm, vaddr_t va) 6016 { 6017 const size_t l1slot = l1pte_index(va); 6018 struct l2_dtable *l2; 6019 vaddr_t nva; 6020 6021 CTASSERT((PAGE_SIZE % L2_TABLE_SIZE_REAL) == 0); 6022 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6023 /* 6024 * No mapping at this address, as there is 6025 * no entry in the L1 table. 6026 * Need to allocate a new l2_dtable. 6027 */ 6028 nva = pmap_kernel_l2dtable_kva; 6029 if ((nva & PGOFSET) == 0) { 6030 /* 6031 * Need to allocate a backing page 6032 */ 6033 if (pmap_grow_map(nva, NULL)) 6034 return NULL; 6035 } 6036 6037 l2 = (struct l2_dtable *)nva; 6038 nva += sizeof(struct l2_dtable); 6039 6040 if ((nva & PGOFSET) < (pmap_kernel_l2dtable_kva & PGOFSET)) { 6041 /* 6042 * The new l2_dtable straddles a page boundary. 6043 * Map in another page to cover it. 6044 */ 6045 if (pmap_grow_map(nva & ~PGOFSET, NULL)) 6046 return NULL; 6047 } 6048 6049 pmap_kernel_l2dtable_kva = nva; 6050 6051 /* 6052 * Link it into the parent pmap 6053 */ 6054 pm->pm_l2[L2_IDX(l1slot)] = l2; 6055 } 6056 6057 struct l2_bucket * const l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6058 6059 /* 6060 * Fetch pointer to the L2 page table associated with the address. 6061 */ 6062 if (l2b->l2b_kva == NULL) { 6063 pt_entry_t *ptep; 6064 6065 /* 6066 * No L2 page table has been allocated. Chances are, this 6067 * is because we just allocated the l2_dtable, above. 6068 */ 6069 nva = pmap_kernel_l2ptp_kva; 6070 ptep = (pt_entry_t *)nva; 6071 if ((nva & PGOFSET) == 0) { 6072 /* 6073 * Need to allocate a backing page 6074 */ 6075 if (pmap_grow_map(nva, &pmap_kernel_l2ptp_phys)) 6076 return NULL; 6077 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 6078 } 6079 6080 l2->l2_occupancy++; 6081 l2b->l2b_kva = ptep; 6082 l2b->l2b_l1slot = l1slot; 6083 l2b->l2b_pa = pmap_kernel_l2ptp_phys; 6084 6085 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 6086 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 6087 } 6088 6089 return l2b; 6090 } 6091 6092 vaddr_t 6093 pmap_growkernel(vaddr_t maxkvaddr) 6094 { 6095 UVMHIST_FUNC(__func__); 6096 UVMHIST_CALLARGS(maphist, "growing kernel from %#jx to %#jx", 6097 pmap_curmaxkvaddr, maxkvaddr, 0, 0); 6098 6099 pmap_t kpm = pmap_kernel(); 6100 #ifndef ARM_MMU_EXTENDED 6101 struct l1_ttable *l1; 6102 #endif 6103 int s; 6104 6105 if (maxkvaddr <= pmap_curmaxkvaddr) 6106 goto out; /* we are OK */ 6107 6108 KDASSERT(maxkvaddr <= virtual_end); 6109 6110 /* 6111 * whoops! we need to add kernel PTPs 6112 */ 6113 6114 vaddr_t pmap_maxkvaddr = pmap_curmaxkvaddr; 6115 6116 s = splvm(); /* to be safe */ 6117 mutex_enter(&kpm_lock); 6118 6119 /* Map 1MB at a time */ 6120 size_t l1slot = l1pte_index(pmap_maxkvaddr); 6121 #ifdef ARM_MMU_EXTENDED 6122 pd_entry_t * const spdep = &kpm->pm_l1[l1slot]; 6123 pd_entry_t *pdep = spdep; 6124 #endif 6125 for (;pmap_curmaxkvaddr < maxkvaddr; pmap_curmaxkvaddr += L1_S_SIZE, 6126 #ifdef ARM_MMU_EXTENDED 6127 pdep++, 6128 #endif 6129 l1slot++) { 6130 struct l2_bucket *l2b = 6131 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 6132 KASSERT(l2b != NULL); 6133 6134 const pd_entry_t npde = L1_C_PROTO | l2b->l2b_pa 6135 | L1_C_DOM(PMAP_DOMAIN_KERNEL); 6136 #ifdef ARM_MMU_EXTENDED 6137 KASSERT(*pdep == 0); 6138 l1pte_setone(pdep, npde); 6139 #else 6140 /* Distribute new L1 entry to all L1s */ 6141 SLIST_FOREACH(l1, &l1_list, l1_link) { 6142 pd_entry_t * const pdep = &l1->l1_kva[l1slot]; 6143 l1pte_setone(pdep, npde); 6144 PDE_SYNC(pdep); 6145 } 6146 #endif 6147 } 6148 #ifdef ARM_MMU_EXTENDED 6149 PDE_SYNC_RANGE(spdep, pdep - spdep); 6150 #endif 6151 6152 #ifdef PMAP_CACHE_VIVT 6153 /* 6154 * flush out the cache, expensive but growkernel will happen so 6155 * rarely 6156 */ 6157 cpu_dcache_wbinv_all(); 6158 cpu_tlb_flushD(); 6159 cpu_cpwait(); 6160 #endif 6161 6162 mutex_exit(&kpm_lock); 6163 splx(s); 6164 6165 kasan_shadow_map((void *)pmap_maxkvaddr, 6166 (size_t)(pmap_curmaxkvaddr - pmap_maxkvaddr)); 6167 6168 out: 6169 return pmap_curmaxkvaddr; 6170 } 6171 6172 /************************ Utility routines ****************************/ 6173 6174 #ifndef ARM_HAS_VBAR 6175 /* 6176 * vector_page_setprot: 6177 * 6178 * Manipulate the protection of the vector page. 6179 */ 6180 void 6181 vector_page_setprot(int prot) 6182 { 6183 struct l2_bucket *l2b; 6184 pt_entry_t *ptep; 6185 6186 #if defined(CPU_ARMV7) || defined(CPU_ARM11) 6187 /* 6188 * If we are using VBAR to use the vectors in the kernel, then it's 6189 * already mapped in the kernel text so no need to anything here. 6190 */ 6191 if (vector_page != ARM_VECTORS_LOW && vector_page != ARM_VECTORS_HIGH) { 6192 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 6193 return; 6194 } 6195 #endif 6196 6197 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 6198 KASSERT(l2b != NULL); 6199 6200 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 6201 6202 const pt_entry_t opte = *ptep; 6203 #ifdef ARM_MMU_EXTENDED 6204 const pt_entry_t npte = (opte & ~(L2_S_PROT_MASK|L2_XS_XN)) 6205 | L2_S_PROT(PTE_KERNEL, prot); 6206 #else 6207 const pt_entry_t npte = (opte & ~L2_S_PROT_MASK) 6208 | L2_S_PROT(PTE_KERNEL, prot); 6209 #endif 6210 l2pte_set(ptep, npte, opte); 6211 PTE_SYNC(ptep); 6212 cpu_tlb_flushD_SE(vector_page); 6213 cpu_cpwait(); 6214 } 6215 #endif 6216 6217 /* 6218 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 6219 * Returns true if the mapping exists, else false. 6220 * 6221 * NOTE: This function is only used by a couple of arm-specific modules. 6222 * It is not safe to take any pmap locks here, since we could be right 6223 * in the middle of debugging the pmap anyway... 6224 * 6225 * It is possible for this routine to return false even though a valid 6226 * mapping does exist. This is because we don't lock, so the metadata 6227 * state may be inconsistent. 6228 * 6229 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 6230 * a "section" mapping. 6231 */ 6232 bool 6233 pmap_get_pde_pte(pmap_t pm, vaddr_t va, pd_entry_t **pdp, pt_entry_t **ptp) 6234 { 6235 struct l2_dtable *l2; 6236 pd_entry_t *pdep, pde; 6237 pt_entry_t *ptep; 6238 u_short l1slot; 6239 6240 if (pm->pm_l1 == NULL) 6241 return false; 6242 6243 l1slot = l1pte_index(va); 6244 *pdp = pdep = pmap_l1_kva(pm) + l1slot; 6245 pde = *pdep; 6246 6247 if (l1pte_section_p(pde)) { 6248 *ptp = NULL; 6249 return true; 6250 } 6251 6252 l2 = pm->pm_l2[L2_IDX(l1slot)]; 6253 if (l2 == NULL || 6254 (ptep = l2->l2_bucket[L2_BUCKET(l1slot)].l2b_kva) == NULL) { 6255 return false; 6256 } 6257 6258 *ptp = &ptep[l2pte_index(va)]; 6259 return true; 6260 } 6261 6262 bool 6263 pmap_get_pde(pmap_t pm, vaddr_t va, pd_entry_t **pdp) 6264 { 6265 6266 if (pm->pm_l1 == NULL) 6267 return false; 6268 6269 *pdp = pmap_l1_kva(pm) + l1pte_index(va); 6270 6271 return true; 6272 } 6273 6274 /************************ Bootstrapping routines ****************************/ 6275 6276 #ifndef ARM_MMU_EXTENDED 6277 static void 6278 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 6279 { 6280 int i; 6281 6282 l1->l1_kva = l1pt; 6283 l1->l1_domain_use_count = 0; 6284 l1->l1_domain_first = 0; 6285 6286 for (i = 0; i < PMAP_DOMAINS; i++) 6287 l1->l1_domain_free[i] = i + 1; 6288 6289 /* 6290 * Copy the kernel's L1 entries to each new L1. 6291 */ 6292 if (pmap_initialized) 6293 memcpy(l1pt, pmap_l1_kva(pmap_kernel()), L1_TABLE_SIZE); 6294 6295 if (pmap_extract(pmap_kernel(), (vaddr_t)l1pt, 6296 &l1->l1_physaddr) == false) 6297 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 6298 6299 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 6300 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 6301 } 6302 #endif /* !ARM_MMU_EXTENDED */ 6303 6304 /* 6305 * pmap_bootstrap() is called from the board-specific initarm() routine 6306 * once the kernel L1/L2 descriptors tables have been set up. 6307 * 6308 * This is a somewhat convoluted process since pmap bootstrap is, effectively, 6309 * spread over a number of disparate files/functions. 6310 * 6311 * We are passed the following parameters 6312 * - vstart 6313 * 1MB-aligned start of managed kernel virtual memory. 6314 * - vend 6315 * 1MB-aligned end of managed kernel virtual memory. 6316 * 6317 * We use 'kernel_l1pt' to build the metadata (struct l1_ttable and 6318 * struct l2_dtable) necessary to track kernel mappings. 6319 */ 6320 #define PMAP_STATIC_L2_SIZE 16 6321 void 6322 pmap_bootstrap(vaddr_t vstart, vaddr_t vend) 6323 { 6324 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 6325 #ifndef ARM_MMU_EXTENDED 6326 static struct l1_ttable static_l1; 6327 struct l1_ttable *l1 = &static_l1; 6328 #endif 6329 struct l2_dtable *l2; 6330 struct l2_bucket *l2b; 6331 pd_entry_t *l1pt = (pd_entry_t *) kernel_l1pt.pv_va; 6332 pmap_t pm = pmap_kernel(); 6333 pt_entry_t *ptep; 6334 paddr_t pa; 6335 vsize_t size; 6336 int nptes, l2idx, l2next = 0; 6337 6338 #ifdef ARM_MMU_EXTENDED 6339 KASSERT(pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt); 6340 KASSERT(pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt); 6341 #endif 6342 6343 VPRINTF("kpm "); 6344 /* 6345 * Initialise the kernel pmap object 6346 */ 6347 curcpu()->ci_pmap_cur = pm; 6348 pm->pm_refs = 1; 6349 #ifdef ARM_MMU_EXTENDED 6350 pm->pm_l1 = l1pt; 6351 pm->pm_l1_pa = kernel_l1pt.pv_pa; 6352 VPRINTF("tlb0 "); 6353 pmap_tlb_info_init(&pmap_tlb0_info); 6354 #ifdef MULTIPROCESSOR 6355 VPRINTF("kcpusets "); 6356 pm->pm_onproc = kcpuset_running; 6357 pm->pm_active = kcpuset_running; 6358 #endif 6359 #else 6360 pm->pm_l1 = l1; 6361 #endif 6362 mutex_init(&pm->pm_lock, MUTEX_DEFAULT, IPL_VM); 6363 6364 6365 #if defined(EFI_RUNTIME) 6366 VPRINTF("efirt "); 6367 memset(&efirt_pmap, 0, sizeof(efirt_pmap)); 6368 struct pmap * const efipm = &efirt_pmap; 6369 struct pmap_asid_info * const efipai = PMAP_PAI(efipm, cpu_tlb_info(curcpu())); 6370 6371 efipai->pai_asid = KERNEL_PID; 6372 efipm->pm_refs = 1; 6373 efipm->pm_stats.wired_count = 0; 6374 efipm->pm_stats.resident_count = 1; 6375 efipm->pm_l1 = (pd_entry_t *)efirt_l1pt.pv_va; 6376 efipm->pm_l1_pa = efirt_l1pt.pv_pa; 6377 // Needed? 6378 #ifdef MULTIPROCESSOR 6379 kcpuset_create(&efipm->pm_active, true); 6380 kcpuset_create(&efipm->pm_onproc, true); 6381 #endif 6382 mutex_init(&efipm->pm_lock, MUTEX_DEFAULT, IPL_NONE); 6383 #endif 6384 6385 VPRINTF("locks "); 6386 /* 6387 * pmap_kenter_pa() and pmap_kremove() may be called from interrupt 6388 * context, so its locks have to be at IPL_VM 6389 */ 6390 mutex_init(&pmap_lock, MUTEX_DEFAULT, IPL_VM); 6391 mutex_init(&kpm_lock, MUTEX_DEFAULT, IPL_NONE); 6392 6393 VPRINTF("l1pt "); 6394 /* 6395 * Scan the L1 translation table created by initarm() and create 6396 * the required metadata for all valid mappings found in it. 6397 */ 6398 for (size_t l1slot = 0; 6399 l1slot < L1_TABLE_SIZE / sizeof(pd_entry_t); 6400 l1slot++) { 6401 pd_entry_t pde = l1pt[l1slot]; 6402 6403 /* 6404 * We're only interested in Coarse mappings. 6405 * pmap_extract() can deal with section mappings without 6406 * recourse to checking L2 metadata. 6407 */ 6408 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 6409 continue; 6410 6411 /* 6412 * Lookup the KVA of this L2 descriptor table 6413 */ 6414 pa = l1pte_pa(pde); 6415 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6416 if (ptep == NULL) { 6417 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 6418 (u_int)l1slot << L1_S_SHIFT, pa); 6419 } 6420 6421 /* 6422 * Fetch the associated L2 metadata structure. 6423 * Allocate a new one if necessary. 6424 */ 6425 if ((l2 = pm->pm_l2[L2_IDX(l1slot)]) == NULL) { 6426 if (l2next == PMAP_STATIC_L2_SIZE) 6427 panic("pmap_bootstrap: out of static L2s"); 6428 pm->pm_l2[L2_IDX(l1slot)] = l2 = &static_l2[l2next++]; 6429 } 6430 6431 /* 6432 * One more L1 slot tracked... 6433 */ 6434 l2->l2_occupancy++; 6435 6436 /* 6437 * Fill in the details of the L2 descriptor in the 6438 * appropriate bucket. 6439 */ 6440 l2b = &l2->l2_bucket[L2_BUCKET(l1slot)]; 6441 l2b->l2b_kva = ptep; 6442 l2b->l2b_pa = pa; 6443 l2b->l2b_l1slot = l1slot; 6444 6445 /* 6446 * Establish an initial occupancy count for this descriptor 6447 */ 6448 for (l2idx = 0; 6449 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 6450 l2idx++) { 6451 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 6452 l2b->l2b_occupancy++; 6453 } 6454 } 6455 6456 /* 6457 * Make sure the descriptor itself has the correct cache mode. 6458 * If not, fix it, but whine about the problem. Port-meisters 6459 * should consider this a clue to fix up their initarm() 6460 * function. :) 6461 */ 6462 if (pmap_set_pt_cache_mode(l1pt, (vaddr_t)ptep, 1)) { 6463 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6464 "L2 pte @ %p\n", ptep); 6465 } 6466 } 6467 6468 VPRINTF("cache(l1pt) "); 6469 /* 6470 * Ensure the primary (kernel) L1 has the correct cache mode for 6471 * a page table. Bitch if it is not correctly set. 6472 */ 6473 if (pmap_set_pt_cache_mode(l1pt, kernel_l1pt.pv_va, 6474 L1_TABLE_SIZE / L2_S_SIZE)) { 6475 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6476 "primary L1 @ 0x%lx\n", kernel_l1pt.pv_va); 6477 } 6478 #if defined(EFI_RUNTIME) 6479 if (pmap_set_pt_cache_mode(l1pt, efirt_l1pt.pv_va, 6480 L1_TABLE_SIZE / L2_S_SIZE)) { 6481 printf("pmap_bootstrap: WARNING! wrong cache mode for " 6482 "EFI RT L1 @ 0x%lx\n", efirt_l1pt.pv_va); 6483 } 6484 #endif 6485 6486 #ifdef PMAP_CACHE_VIVT 6487 cpu_dcache_wbinv_all(); 6488 cpu_tlb_flushID(); 6489 cpu_cpwait(); 6490 #endif 6491 6492 /* 6493 * now we allocate the "special" VAs which are used for tmp mappings 6494 * by the pmap (and other modules). we allocate the VAs by advancing 6495 * virtual_avail (note that there are no pages mapped at these VAs). 6496 * 6497 * Managed KVM space start from wherever initarm() tells us. 6498 */ 6499 virtual_avail = vstart; 6500 virtual_end = vend; 6501 6502 VPRINTF("specials "); 6503 6504 pmap_alloc_specials(&virtual_avail, 1, &memhook, NULL); 6505 6506 #ifdef PMAP_CACHE_VIPT 6507 /* 6508 * If we have a VIPT cache, we need one page/pte per possible alias 6509 * page so we won't violate cache aliasing rules. 6510 */ 6511 virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask; 6512 nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1; 6513 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6514 if (arm_pcache.icache_type != CACHE_TYPE_PIPT 6515 && arm_pcache.icache_way_size > nptes * L2_S_SIZE) { 6516 nptes = arm_pcache.icache_way_size >> L2_S_SHIFT; 6517 nptes = roundup(nptes, PAGE_SIZE / L2_S_SIZE); 6518 } 6519 #else 6520 nptes = PAGE_SIZE / L2_S_SIZE; 6521 #endif 6522 #ifdef MULTIPROCESSOR 6523 cnptes = nptes; 6524 nptes *= arm_cpu_max; 6525 #endif 6526 pmap_alloc_specials(&virtual_avail, nptes, &csrcp, &csrc_pte); 6527 pmap_set_pt_cache_mode(l1pt, (vaddr_t)csrc_pte, nptes); 6528 pmap_alloc_specials(&virtual_avail, nptes, &cdstp, &cdst_pte); 6529 pmap_set_pt_cache_mode(l1pt, (vaddr_t)cdst_pte, nptes); 6530 if (msgbufaddr == NULL) { 6531 pmap_alloc_specials(&virtual_avail, 6532 round_page(MSGBUFSIZE) / PAGE_SIZE, 6533 (void *)&msgbufaddr, NULL); 6534 } 6535 6536 /* 6537 * Allocate a range of kernel virtual address space to be used 6538 * for L2 descriptor tables and metadata allocation in 6539 * pmap_growkernel(). 6540 */ 6541 size = howmany(virtual_end - pmap_curmaxkvaddr, L1_S_SIZE); 6542 pmap_alloc_specials(&virtual_avail, 6543 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 6544 &pmap_kernel_l2ptp_kva, NULL); 6545 6546 size = howmany(size, L2_BUCKET_SIZE); 6547 pmap_alloc_specials(&virtual_avail, 6548 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 6549 &pmap_kernel_l2dtable_kva, NULL); 6550 6551 #ifndef ARM_MMU_EXTENDED 6552 /* 6553 * init the static-global locks and global pmap list. 6554 */ 6555 mutex_init(&l1_lru_lock, MUTEX_DEFAULT, IPL_VM); 6556 6557 /* 6558 * We can now initialise the first L1's metadata. 6559 */ 6560 SLIST_INIT(&l1_list); 6561 TAILQ_INIT(&l1_lru_list); 6562 pmap_init_l1(l1, l1pt); 6563 #endif /* ARM_MMU_EXTENDED */ 6564 6565 #ifndef ARM_HAS_VBAR 6566 /* Set up vector page L1 details, if necessary */ 6567 if (vector_page < KERNEL_BASE) { 6568 pm->pm_pl1vec = pmap_l1_kva(pm) + l1pte_index(vector_page); 6569 l2b = pmap_get_l2_bucket(pm, vector_page); 6570 KDASSERT(l2b != NULL); 6571 pm->pm_l1vec = l2b->l2b_pa | L1_C_PROTO | 6572 L1_C_DOM(pmap_domain(pm)); 6573 } else 6574 pm->pm_pl1vec = NULL; 6575 #endif 6576 6577 VPRINTF("pools "); 6578 /* 6579 * Initialize the pmap cache 6580 */ 6581 pool_cache_bootstrap(&pmap_cache, sizeof(struct pmap), 0, 0, 0, 6582 "pmappl", NULL, IPL_NONE, pmap_pmap_ctor, NULL, NULL); 6583 6584 /* 6585 * Initialize the pv pool. 6586 */ 6587 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvepl", 6588 &pmap_bootstrap_pv_allocator, IPL_NONE); 6589 6590 /* 6591 * Initialize the L2 dtable pool and cache. 6592 */ 6593 pool_cache_bootstrap(&pmap_l2dtable_cache, sizeof(struct l2_dtable), 0, 6594 0, 0, "l2dtblpl", NULL, IPL_NONE, pmap_l2dtable_ctor, NULL, NULL); 6595 6596 /* 6597 * Initialise the L2 descriptor table pool and cache 6598 */ 6599 pool_cache_bootstrap(&pmap_l2ptp_cache, L2_TABLE_SIZE_REAL, 6600 L2_TABLE_SIZE_REAL, 0, 0, "l2ptppl", NULL, IPL_NONE, 6601 pmap_l2ptp_ctor, NULL, NULL); 6602 6603 mutex_init(&memlock, MUTEX_DEFAULT, IPL_NONE); 6604 6605 cpu_dcache_wbinv_all(); 6606 } 6607 6608 static bool 6609 pmap_set_pt_cache_mode(pd_entry_t *kl1, vaddr_t va, size_t nptes) 6610 { 6611 #ifdef ARM_MMU_EXTENDED 6612 return false; 6613 #else 6614 if (pte_l1_s_cache_mode == pte_l1_s_cache_mode_pt 6615 && pte_l2_s_cache_mode == pte_l2_s_cache_mode_pt) 6616 return false; 6617 6618 const vaddr_t eva = va + nptes * PAGE_SIZE; 6619 int rv = 0; 6620 6621 while (va < eva) { 6622 /* 6623 * Make sure the descriptor itself has the correct cache mode 6624 */ 6625 pd_entry_t * const pdep = &kl1[l1pte_index(va)]; 6626 pd_entry_t pde = *pdep; 6627 6628 if (l1pte_section_p(pde)) { 6629 KASSERT((L1_S_CACHE_MASK & L1_S_V6_SUPER) == 0); 6630 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 6631 *pdep = (pde & ~L1_S_CACHE_MASK) | 6632 pte_l1_s_cache_mode_pt; 6633 PDE_SYNC(pdep); 6634 cpu_dcache_wbinv_range((vaddr_t)pdep, 6635 sizeof(*pdep)); 6636 rv = 1; 6637 } 6638 return rv; 6639 } 6640 vaddr_t pa = l1pte_pa(pde); 6641 pt_entry_t *ptep = (pt_entry_t *)kernel_pt_lookup(pa); 6642 if (ptep == NULL) 6643 panic("pmap_bootstrap: No PTP for va %#lx\n", va); 6644 6645 ptep += l2pte_index(va); 6646 const pt_entry_t opte = *ptep; 6647 if ((opte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 6648 const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK) 6649 | pte_l2_s_cache_mode_pt; 6650 l2pte_set(ptep, npte, opte); 6651 PTE_SYNC(ptep); 6652 cpu_dcache_wbinv_range((vaddr_t)ptep, sizeof(*ptep)); 6653 rv = 1; 6654 } 6655 va += PAGE_SIZE; 6656 } 6657 6658 return rv; 6659 #endif 6660 } 6661 6662 static void 6663 pmap_alloc_specials(vaddr_t *availp, int pages, vaddr_t *vap, pt_entry_t **ptep) 6664 { 6665 vaddr_t va = *availp; 6666 struct l2_bucket *l2b; 6667 6668 if (ptep) { 6669 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 6670 if (l2b == NULL) 6671 panic("pmap_alloc_specials: no l2b for 0x%lx", va); 6672 6673 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 6674 } 6675 6676 *vap = va; 6677 *availp = va + (PAGE_SIZE * pages); 6678 } 6679 6680 void 6681 pmap_init(void) 6682 { 6683 6684 /* 6685 * Set the available memory vars - These do not map to real memory 6686 * addresses and cannot as the physical memory is fragmented. 6687 * They are used by ps for %mem calculations. 6688 * One could argue whether this should be the entire memory or just 6689 * the memory that is useable in a user process. 6690 */ 6691 avail_start = ptoa(uvm_physseg_get_avail_start(uvm_physseg_get_first())); 6692 avail_end = ptoa(uvm_physseg_get_avail_end(uvm_physseg_get_last())); 6693 6694 /* 6695 * Now we need to free enough pv_entry structures to allow us to get 6696 * the kmem_map/kmem_object allocated and inited (done after this 6697 * function is finished). to do this we allocate one bootstrap page out 6698 * of kernel_map and use it to provide an initial pool of pv_entry 6699 * structures. we never free this page. 6700 */ 6701 pool_setlowat(&pmap_pv_pool, (PAGE_SIZE / sizeof(struct pv_entry)) * 2); 6702 6703 #ifdef ARM_MMU_EXTENDED 6704 /* 6705 * Initialise the L1 pool and cache. 6706 */ 6707 6708 pool_cache_bootstrap(&pmap_l1tt_cache, L1TT_SIZE, L1TT_SIZE, 6709 0, 0, "l1ttpl", &pmap_l1tt_allocator, IPL_NONE, pmap_l1tt_ctor, 6710 NULL, NULL); 6711 6712 int error __diagused = pmap_maxproc_set(maxproc); 6713 KASSERT(error == 0); 6714 6715 pmap_tlb_info_evcnt_attach(&pmap_tlb0_info); 6716 #endif 6717 6718 pmap_initialized = true; 6719 } 6720 6721 static vaddr_t last_bootstrap_page = 0; 6722 static void *free_bootstrap_pages = NULL; 6723 6724 static void * 6725 pmap_bootstrap_pv_page_alloc(struct pool *pp, int flags) 6726 { 6727 extern void *pool_page_alloc(struct pool *, int); 6728 vaddr_t new_page; 6729 void *rv; 6730 6731 if (pmap_initialized) 6732 return pool_page_alloc(pp, flags); 6733 6734 if (free_bootstrap_pages) { 6735 rv = free_bootstrap_pages; 6736 free_bootstrap_pages = *((void **)rv); 6737 return rv; 6738 } 6739 6740 KASSERT(kernel_map != NULL); 6741 new_page = uvm_km_alloc(kernel_map, PAGE_SIZE, 0, 6742 UVM_KMF_WIRED | ((flags & PR_WAITOK) ? 0 : UVM_KMF_NOWAIT)); 6743 6744 KASSERT(new_page > last_bootstrap_page); 6745 last_bootstrap_page = new_page; 6746 return (void *)new_page; 6747 } 6748 6749 static void 6750 pmap_bootstrap_pv_page_free(struct pool *pp, void *v) 6751 { 6752 extern void pool_page_free(struct pool *, void *); 6753 6754 if ((vaddr_t)v <= last_bootstrap_page) { 6755 *((void **)v) = free_bootstrap_pages; 6756 free_bootstrap_pages = v; 6757 return; 6758 } 6759 6760 if (pmap_initialized) { 6761 pool_page_free(pp, v); 6762 return; 6763 } 6764 } 6765 6766 6767 #if defined(ARM_MMU_EXTENDED) 6768 static void * 6769 pmap_l1tt_alloc(struct pool *pp, int flags) 6770 { 6771 struct pglist plist; 6772 vaddr_t va; 6773 6774 const int waitok = flags & PR_WAITOK; 6775 6776 int error = uvm_pglistalloc(L1TT_SIZE, 0, -1, L1TT_SIZE, 0, &plist, 1, 6777 waitok); 6778 if (error) 6779 panic("Cannot allocate L1TT physical pages, %d", error); 6780 6781 struct vm_page *pg = TAILQ_FIRST(&plist); 6782 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6783 6784 /* Allocate a L1 translation table VA */ 6785 va = uvm_km_alloc(kernel_map, L1TT_SIZE, L1TT_SIZE, UVM_KMF_VAONLY); 6786 if (va == 0) 6787 panic("Cannot allocate L1TT KVA"); 6788 6789 const vaddr_t eva = va + L1TT_SIZE; 6790 vaddr_t mva = va; 6791 while (pg && mva < eva) { 6792 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6793 6794 pmap_kenter_pa(mva, pa, 6795 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6796 6797 mva += PAGE_SIZE; 6798 pg = TAILQ_NEXT(pg, pageq.queue); 6799 } 6800 KASSERTMSG(pg == NULL && mva == eva, "pg %p mva %" PRIxVADDR 6801 " eva %" PRIxVADDR, pg, mva, eva); 6802 #else 6803 bool ok; 6804 paddr_t pa = VM_PAGE_TO_PHYS(pg); 6805 va = pmap_direct_mapped_phys(pa, &ok, 0); 6806 KASSERT(ok); 6807 KASSERT(va >= KERNEL_BASE); 6808 #endif 6809 6810 return (void *)va; 6811 } 6812 6813 static void 6814 pmap_l1tt_free(struct pool *pp, void *v) 6815 { 6816 vaddr_t va = (vaddr_t)v; 6817 6818 #if !defined( __HAVE_MM_MD_DIRECT_MAPPED_PHYS) 6819 uvm_km_free(kernel_map, va, L1TT_SIZE, UVM_KMF_WIRED); 6820 #else 6821 #if defined(KERNEL_BASE_VOFFSET) 6822 paddr_t pa = va - KERNEL_BASE_VOFFSET; 6823 #else 6824 paddr_t pa = va - KERNEL_BASE + physical_start; 6825 #endif 6826 const paddr_t epa = pa + L1TT_SIZE; 6827 6828 for (; pa < epa; pa += PAGE_SIZE) { 6829 struct vm_page *pg = PHYS_TO_VM_PAGE(pa); 6830 uvm_pagefree(pg); 6831 } 6832 #endif 6833 } 6834 #endif 6835 6836 /* 6837 * pmap_postinit() 6838 * 6839 * This routine is called after the vm and kmem subsystems have been 6840 * initialised. This allows the pmap code to perform any initialisation 6841 * that can only be done once the memory allocation is in place. 6842 */ 6843 void 6844 pmap_postinit(void) 6845 { 6846 #ifndef ARM_MMU_EXTENDED 6847 extern paddr_t physical_start, physical_end; 6848 struct l1_ttable *l1; 6849 struct pglist plist; 6850 struct vm_page *m; 6851 pd_entry_t *pdep; 6852 vaddr_t va, eva; 6853 u_int loop, needed; 6854 int error; 6855 #endif 6856 6857 pool_cache_setlowat(&pmap_l2ptp_cache, (PAGE_SIZE / L2_TABLE_SIZE_REAL) * 4); 6858 pool_cache_setlowat(&pmap_l2dtable_cache, 6859 (PAGE_SIZE / sizeof(struct l2_dtable)) * 2); 6860 6861 #ifndef ARM_MMU_EXTENDED 6862 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 6863 needed -= 1; 6864 6865 l1 = kmem_alloc(sizeof(*l1) * needed, KM_SLEEP); 6866 6867 for (loop = 0; loop < needed; loop++, l1++) { 6868 /* Allocate a L1 page table */ 6869 va = uvm_km_alloc(kernel_map, L1_TABLE_SIZE, 0, UVM_KMF_VAONLY); 6870 if (va == 0) 6871 panic("Cannot allocate L1 KVM"); 6872 6873 error = uvm_pglistalloc(L1_TABLE_SIZE, physical_start, 6874 physical_end, L1_TABLE_SIZE, 0, &plist, 1, 1); 6875 if (error) 6876 panic("Cannot allocate L1 physical pages"); 6877 6878 m = TAILQ_FIRST(&plist); 6879 eva = va + L1_TABLE_SIZE; 6880 pdep = (pd_entry_t *)va; 6881 6882 while (m && va < eva) { 6883 paddr_t pa = VM_PAGE_TO_PHYS(m); 6884 6885 pmap_kenter_pa(va, pa, 6886 VM_PROT_READ|VM_PROT_WRITE, PMAP_KMPAGE|PMAP_PTE); 6887 6888 va += PAGE_SIZE; 6889 m = TAILQ_NEXT(m, pageq.queue); 6890 } 6891 6892 #ifdef DIAGNOSTIC 6893 if (m) 6894 panic("pmap_alloc_l1pt: pglist not empty"); 6895 #endif /* DIAGNOSTIC */ 6896 6897 pmap_init_l1(l1, pdep); 6898 } 6899 6900 #ifdef DEBUG 6901 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 6902 needed); 6903 #endif 6904 #endif /* !ARM_MMU_EXTENDED */ 6905 } 6906 6907 /* 6908 * Note that the following routines are used by board-specific initialisation 6909 * code to configure the initial kernel page tables. 6910 * 6911 */ 6912 6913 /* 6914 * This list exists for the benefit of pmap_map_chunk(). It keeps track 6915 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 6916 * find them as necessary. 6917 * 6918 * Note that the data on this list MUST remain valid after initarm() returns, 6919 * as pmap_bootstrap() uses it to construct L2 table metadata. 6920 */ 6921 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 6922 6923 static vaddr_t 6924 kernel_pt_lookup(paddr_t pa) 6925 { 6926 pv_addr_t *pv; 6927 6928 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 6929 if (pv->pv_pa == (pa & ~PGOFSET)) 6930 return pv->pv_va | (pa & PGOFSET); 6931 } 6932 return 0; 6933 } 6934 6935 /* 6936 * pmap_map_section: 6937 * 6938 * Create a single section mapping. 6939 */ 6940 void 6941 pmap_map_section(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6942 { 6943 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6944 const size_t l1slot = l1pte_index(va); 6945 pd_entry_t fl; 6946 6947 KASSERT(((va | pa) & L1_S_OFFSET) == 0); 6948 6949 switch (cache) { 6950 case PTE_NOCACHE: 6951 fl = pte_l1_s_nocache_mode; 6952 break; 6953 6954 case PTE_CACHE: 6955 fl = pte_l1_s_cache_mode; 6956 break; 6957 6958 case PTE_PAGETABLE: 6959 fl = pte_l1_s_cache_mode_pt; 6960 break; 6961 6962 case PTE_DEV: 6963 default: 6964 fl = 0; 6965 break; 6966 } 6967 6968 const pd_entry_t npde = L1_S_PROTO | pa | 6969 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 6970 l1pte_setone(pdep + l1slot, npde); 6971 PDE_SYNC(pdep + l1slot); 6972 } 6973 6974 /* 6975 * pmap_map_entry: 6976 * 6977 * Create a single page mapping. 6978 */ 6979 void 6980 pmap_map_entry(vaddr_t l1pt, vaddr_t va, paddr_t pa, int prot, int cache) 6981 { 6982 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 6983 const size_t l1slot = l1pte_index(va); 6984 pt_entry_t npte; 6985 pt_entry_t *ptep; 6986 6987 KASSERT(((va | pa) & PGOFSET) == 0); 6988 6989 switch (cache) { 6990 case PTE_NOCACHE: 6991 npte = pte_l2_s_nocache_mode; 6992 break; 6993 6994 case PTE_CACHE: 6995 npte = pte_l2_s_cache_mode; 6996 break; 6997 6998 case PTE_PAGETABLE: 6999 npte = pte_l2_s_cache_mode_pt; 7000 break; 7001 7002 default: 7003 npte = 0; 7004 break; 7005 } 7006 7007 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 7008 panic("pmap_map_entry: no L2 table for VA 0x%08lx", va); 7009 7010 ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 7011 if (ptep == NULL) 7012 panic("pmap_map_entry: can't find L2 table for VA 0x%08lx", va); 7013 7014 npte |= L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot); 7015 #ifdef ARM_MMU_EXTENDED 7016 if (prot & VM_PROT_EXECUTE) { 7017 npte &= ~L2_XS_XN; 7018 } 7019 #endif 7020 ptep += l2pte_index(va); 7021 l2pte_set(ptep, npte, 0); 7022 PTE_SYNC(ptep); 7023 } 7024 7025 /* 7026 * pmap_link_l2pt: 7027 * 7028 * Link the L2 page table specified by "l2pv" into the L1 7029 * page table at the slot for "va". 7030 */ 7031 void 7032 pmap_link_l2pt(vaddr_t l1pt, vaddr_t va, pv_addr_t *l2pv) 7033 { 7034 pd_entry_t * const pdep = (pd_entry_t *) l1pt + l1pte_index(va); 7035 7036 KASSERT((va & ((L1_S_SIZE * (PAGE_SIZE / L2_T_SIZE)) - 1)) == 0); 7037 KASSERT((l2pv->pv_pa & PGOFSET) == 0); 7038 7039 const pd_entry_t npde = L1_C_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO 7040 | l2pv->pv_pa; 7041 7042 l1pte_set(pdep, npde); 7043 PDE_SYNC_RANGE(pdep, PAGE_SIZE / L2_T_SIZE); 7044 7045 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 7046 } 7047 7048 /* 7049 * pmap_map_chunk: 7050 * 7051 * Map a chunk of memory using the most efficient mappings 7052 * possible (section, large page, small page) into the 7053 * provided L1 and L2 tables at the specified virtual address. 7054 */ 7055 vsize_t 7056 pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size, 7057 int prot, int cache) 7058 { 7059 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7060 pt_entry_t f1, f2s, f2l; 7061 vsize_t resid; 7062 7063 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 7064 7065 if (l1pt == 0) 7066 panic("pmap_map_chunk: no L1 table provided"); 7067 7068 // VPRINTF("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 7069 // "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 7070 7071 switch (cache) { 7072 case PTE_NOCACHE: 7073 f1 = pte_l1_s_nocache_mode; 7074 f2l = pte_l2_l_nocache_mode; 7075 f2s = pte_l2_s_nocache_mode; 7076 break; 7077 7078 case PTE_CACHE: 7079 f1 = pte_l1_s_cache_mode; 7080 f2l = pte_l2_l_cache_mode; 7081 f2s = pte_l2_s_cache_mode; 7082 break; 7083 7084 case PTE_PAGETABLE: 7085 f1 = pte_l1_s_cache_mode_pt; 7086 f2l = pte_l2_l_cache_mode_pt; 7087 f2s = pte_l2_s_cache_mode_pt; 7088 break; 7089 7090 case PTE_DEV: 7091 default: 7092 f1 = 0; 7093 f2l = 0; 7094 f2s = 0; 7095 break; 7096 } 7097 7098 size = resid; 7099 7100 while (resid > 0) { 7101 const size_t l1slot = l1pte_index(va); 7102 #ifdef ARM_MMU_EXTENDED 7103 /* See if we can use a supersection mapping. */ 7104 if (L1_SS_PROTO && L1_SS_MAPPABLE_P(va, pa, resid)) { 7105 /* Supersection are always domain 0 */ 7106 const pd_entry_t npde = L1_SS_PROTO | pa 7107 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 7108 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 7109 | L1_S_PROT(PTE_KERNEL, prot) | f1; 7110 VPRINTF("sS"); 7111 l1pte_set(&pdep[l1slot], npde); 7112 PDE_SYNC_RANGE(&pdep[l1slot], L1_SS_SIZE / L1_S_SIZE); 7113 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 7114 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 7115 va += L1_SS_SIZE; 7116 pa += L1_SS_SIZE; 7117 resid -= L1_SS_SIZE; 7118 continue; 7119 } 7120 #endif 7121 /* See if we can use a section mapping. */ 7122 if (L1_S_MAPPABLE_P(va, pa, resid)) { 7123 const pd_entry_t npde = L1_S_PROTO | pa 7124 #ifdef ARM_MMU_EXTENDED 7125 | ((prot & VM_PROT_EXECUTE) ? 0 : L1_S_V6_XN) 7126 | (va & 0x80000000 ? 0 : L1_S_V6_nG) 7127 #endif 7128 | L1_S_PROT(PTE_KERNEL, prot) | f1 7129 | L1_S_DOM(PMAP_DOMAIN_KERNEL); 7130 VPRINTF("S"); 7131 l1pte_set(&pdep[l1slot], npde); 7132 PDE_SYNC(&pdep[l1slot]); 7133 // VPRINTF("\npmap_map_chunk: pa=0x%lx va=0x%lx resid=0x%08lx " 7134 // "npdep=%p pde=0x%x\n", pa, va, resid, &pdep[l1slot], npde); 7135 va += L1_S_SIZE; 7136 pa += L1_S_SIZE; 7137 resid -= L1_S_SIZE; 7138 continue; 7139 } 7140 7141 /* 7142 * Ok, we're going to use an L2 table. Make sure 7143 * one is actually in the corresponding L1 slot 7144 * for the current VA. 7145 */ 7146 if ((pdep[l1slot] & L1_TYPE_MASK) != L1_TYPE_C) 7147 panic("%s: no L2 table for VA %#lx", __func__, va); 7148 7149 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pdep[l1slot])); 7150 if (ptep == NULL) 7151 panic("%s: can't find L2 table for VA %#lx", __func__, 7152 va); 7153 7154 ptep += l2pte_index(va); 7155 7156 /* See if we can use a L2 large page mapping. */ 7157 if (L2_L_MAPPABLE_P(va, pa, resid)) { 7158 const pt_entry_t npte = L2_L_PROTO | pa 7159 #ifdef ARM_MMU_EXTENDED 7160 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_L_XN) 7161 | (va & 0x80000000 ? 0 : L2_XS_nG) 7162 #endif 7163 | L2_L_PROT(PTE_KERNEL, prot) | f2l; 7164 VPRINTF("L"); 7165 l2pte_set(ptep, npte, 0); 7166 PTE_SYNC_RANGE(ptep, L2_L_SIZE / L2_S_SIZE); 7167 va += L2_L_SIZE; 7168 pa += L2_L_SIZE; 7169 resid -= L2_L_SIZE; 7170 continue; 7171 } 7172 7173 VPRINTF("P"); 7174 /* Use a small page mapping. */ 7175 pt_entry_t npte = L2_S_PROTO | pa 7176 #ifdef ARM_MMU_EXTENDED 7177 | ((prot & VM_PROT_EXECUTE) ? 0 : L2_XS_XN) 7178 | (va & 0x80000000 ? 0 : L2_XS_nG) 7179 #endif 7180 | L2_S_PROT(PTE_KERNEL, prot) | f2s; 7181 #ifdef ARM_MMU_EXTENDED 7182 npte &= ((prot & VM_PROT_EXECUTE) ? ~L2_XS_XN : ~0); 7183 #endif 7184 l2pte_set(ptep, npte, 0); 7185 PTE_SYNC(ptep); 7186 va += PAGE_SIZE; 7187 pa += PAGE_SIZE; 7188 resid -= PAGE_SIZE; 7189 } 7190 VPRINTF("\n"); 7191 return size; 7192 } 7193 7194 /* 7195 * pmap_unmap_chunk: 7196 * 7197 * Unmap a chunk of memory that was previously pmap_map_chunk 7198 */ 7199 void 7200 pmap_unmap_chunk(vaddr_t l1pt, vaddr_t va, vsize_t size) 7201 { 7202 pd_entry_t * const pdep = (pd_entry_t *) l1pt; 7203 const size_t l1slot = l1pte_index(va); 7204 7205 KASSERT(size == L1_SS_SIZE || size == L1_S_SIZE); 7206 7207 l1pte_set(&pdep[l1slot], 0); 7208 PDE_SYNC_RANGE(&pdep[l1slot], size / L1_S_SIZE); 7209 7210 pmap_tlb_flush_SE(pmap_kernel(), va, PVF_REF); 7211 } 7212 7213 7214 vsize_t 7215 pmap_kenter_range(vaddr_t va, paddr_t pa, vsize_t size, vm_prot_t prot, 7216 u_int flags) 7217 { 7218 const vaddr_t root = pmap_devmap_root(); 7219 7220 int cache; 7221 switch (flags) { 7222 case PMAP_DEV: 7223 cache = PTE_DEV; 7224 break; 7225 case PMAP_NOCACHE: 7226 cache = PTE_NOCACHE; 7227 break; 7228 default: 7229 cache = PTE_CACHE; 7230 break; 7231 } 7232 7233 return pmap_map_chunk(root, va, pa, size, prot, cache); 7234 } 7235 7236 7237 /********************** PTE initialization routines **************************/ 7238 7239 /* 7240 * These routines are called when the CPU type is identified to set up 7241 * the PTE prototypes, cache modes, etc. 7242 * 7243 * The variables are always here, just in case modules need to reference 7244 * them (though, they shouldn't). 7245 */ 7246 7247 pt_entry_t pte_l1_s_nocache_mode; 7248 pt_entry_t pte_l1_s_cache_mode; 7249 pt_entry_t pte_l1_s_wc_mode; 7250 pt_entry_t pte_l1_s_cache_mode_pt; 7251 pt_entry_t pte_l1_s_cache_mask; 7252 7253 pt_entry_t pte_l2_l_nocache_mode; 7254 pt_entry_t pte_l2_l_cache_mode; 7255 pt_entry_t pte_l2_l_wc_mode; 7256 pt_entry_t pte_l2_l_cache_mode_pt; 7257 pt_entry_t pte_l2_l_cache_mask; 7258 7259 pt_entry_t pte_l2_s_nocache_mode; 7260 pt_entry_t pte_l2_s_cache_mode; 7261 pt_entry_t pte_l2_s_wc_mode; 7262 pt_entry_t pte_l2_s_cache_mode_pt; 7263 pt_entry_t pte_l2_s_cache_mask; 7264 7265 pt_entry_t pte_l1_s_prot_u; 7266 pt_entry_t pte_l1_s_prot_w; 7267 pt_entry_t pte_l1_s_prot_ro; 7268 pt_entry_t pte_l1_s_prot_mask; 7269 7270 pt_entry_t pte_l2_s_prot_u; 7271 pt_entry_t pte_l2_s_prot_w; 7272 pt_entry_t pte_l2_s_prot_ro; 7273 pt_entry_t pte_l2_s_prot_mask; 7274 7275 pt_entry_t pte_l2_l_prot_u; 7276 pt_entry_t pte_l2_l_prot_w; 7277 pt_entry_t pte_l2_l_prot_ro; 7278 pt_entry_t pte_l2_l_prot_mask; 7279 7280 pt_entry_t pte_l1_ss_proto; 7281 pt_entry_t pte_l1_s_proto; 7282 pt_entry_t pte_l1_c_proto; 7283 pt_entry_t pte_l2_s_proto; 7284 7285 void (*pmap_copy_page_func)(paddr_t, paddr_t); 7286 void (*pmap_zero_page_func)(paddr_t); 7287 7288 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 7289 void 7290 pmap_pte_init_generic(void) 7291 { 7292 7293 pte_l1_s_nocache_mode = 0; 7294 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7295 pte_l1_s_wc_mode = L1_S_B; 7296 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 7297 7298 pte_l2_l_nocache_mode = 0; 7299 pte_l2_l_cache_mode = L2_B|L2_C; 7300 pte_l2_l_wc_mode = L2_B; 7301 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 7302 7303 pte_l2_s_nocache_mode = 0; 7304 pte_l2_s_cache_mode = L2_B|L2_C; 7305 pte_l2_s_wc_mode = L2_B; 7306 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 7307 7308 /* 7309 * If we have a write-through cache, set B and C. If 7310 * we have a write-back cache, then we assume setting 7311 * only C will make those pages write-through (except for those 7312 * Cortex CPUs which can read the L1 caches). 7313 */ 7314 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop 7315 #if ARM_MMU_V7 > 0 7316 || CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid) 7317 #endif 7318 #if ARM_MMU_V6 > 0 7319 || CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid) /* arm116 errata 399234 */ 7320 #endif 7321 || false) { 7322 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7323 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7324 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7325 } else { 7326 pte_l1_s_cache_mode_pt = L1_S_C; /* write through */ 7327 pte_l2_l_cache_mode_pt = L2_C; /* write through */ 7328 pte_l2_s_cache_mode_pt = L2_C; /* write through */ 7329 } 7330 7331 pte_l1_s_prot_u = L1_S_PROT_U_generic; 7332 pte_l1_s_prot_w = L1_S_PROT_W_generic; 7333 pte_l1_s_prot_ro = L1_S_PROT_RO_generic; 7334 pte_l1_s_prot_mask = L1_S_PROT_MASK_generic; 7335 7336 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7337 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7338 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7339 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7340 7341 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7342 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7343 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7344 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7345 7346 pte_l1_ss_proto = L1_SS_PROTO_generic; 7347 pte_l1_s_proto = L1_S_PROTO_generic; 7348 pte_l1_c_proto = L1_C_PROTO_generic; 7349 pte_l2_s_proto = L2_S_PROTO_generic; 7350 7351 pmap_copy_page_func = pmap_copy_page_generic; 7352 pmap_zero_page_func = pmap_zero_page_generic; 7353 } 7354 7355 #if defined(CPU_ARM8) 7356 void 7357 pmap_pte_init_arm8(void) 7358 { 7359 7360 /* 7361 * ARM8 is compatible with generic, but we need to use 7362 * the page tables uncached. 7363 */ 7364 pmap_pte_init_generic(); 7365 7366 pte_l1_s_cache_mode_pt = 0; 7367 pte_l2_l_cache_mode_pt = 0; 7368 pte_l2_s_cache_mode_pt = 0; 7369 } 7370 #endif /* CPU_ARM8 */ 7371 7372 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 7373 void 7374 pmap_pte_init_arm9(void) 7375 { 7376 7377 /* 7378 * ARM9 is compatible with generic, but we want to use 7379 * write-through caching for now. 7380 */ 7381 pmap_pte_init_generic(); 7382 7383 pte_l1_s_cache_mode = L1_S_C; 7384 pte_l2_l_cache_mode = L2_C; 7385 pte_l2_s_cache_mode = L2_C; 7386 7387 pte_l1_s_wc_mode = L1_S_B; 7388 pte_l2_l_wc_mode = L2_B; 7389 pte_l2_s_wc_mode = L2_B; 7390 7391 pte_l1_s_cache_mode_pt = L1_S_C; 7392 pte_l2_l_cache_mode_pt = L2_C; 7393 pte_l2_s_cache_mode_pt = L2_C; 7394 } 7395 #endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */ 7396 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */ 7397 7398 #if defined(CPU_ARM10) 7399 void 7400 pmap_pte_init_arm10(void) 7401 { 7402 7403 /* 7404 * ARM10 is compatible with generic, but we want to use 7405 * write-through caching for now. 7406 */ 7407 pmap_pte_init_generic(); 7408 7409 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 7410 pte_l2_l_cache_mode = L2_B | L2_C; 7411 pte_l2_s_cache_mode = L2_B | L2_C; 7412 7413 pte_l1_s_cache_mode = L1_S_B; 7414 pte_l2_l_cache_mode = L2_B; 7415 pte_l2_s_cache_mode = L2_B; 7416 7417 pte_l1_s_cache_mode_pt = L1_S_C; 7418 pte_l2_l_cache_mode_pt = L2_C; 7419 pte_l2_s_cache_mode_pt = L2_C; 7420 7421 } 7422 #endif /* CPU_ARM10 */ 7423 7424 #if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH) 7425 void 7426 pmap_pte_init_arm11(void) 7427 { 7428 7429 /* 7430 * ARM11 is compatible with generic, but we want to use 7431 * write-through caching for now. 7432 */ 7433 pmap_pte_init_generic(); 7434 7435 pte_l1_s_cache_mode = L1_S_C; 7436 pte_l2_l_cache_mode = L2_C; 7437 pte_l2_s_cache_mode = L2_C; 7438 7439 pte_l1_s_wc_mode = L1_S_B; 7440 pte_l2_l_wc_mode = L2_B; 7441 pte_l2_s_wc_mode = L2_B; 7442 7443 pte_l1_s_cache_mode_pt = L1_S_C; 7444 pte_l2_l_cache_mode_pt = L2_C; 7445 pte_l2_s_cache_mode_pt = L2_C; 7446 } 7447 #endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */ 7448 7449 #if ARM_MMU_SA1 == 1 7450 void 7451 pmap_pte_init_sa1(void) 7452 { 7453 7454 /* 7455 * The StrongARM SA-1 cache does not have a write-through 7456 * mode. So, do the generic initialization, then reset 7457 * the page table cache mode to B=1,C=1, and note that 7458 * the PTEs need to be sync'd. 7459 */ 7460 pmap_pte_init_generic(); 7461 7462 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 7463 pte_l2_l_cache_mode_pt = L2_B|L2_C; 7464 pte_l2_s_cache_mode_pt = L2_B|L2_C; 7465 7466 pmap_needs_pte_sync = 1; 7467 } 7468 #endif /* ARM_MMU_SA1 == 1*/ 7469 7470 #if ARM_MMU_XSCALE == 1 7471 #if (ARM_NMMUS > 1) 7472 static u_int xscale_use_minidata; 7473 #endif 7474 7475 void 7476 pmap_pte_init_xscale(void) 7477 { 7478 uint32_t auxctl; 7479 int write_through = 0; 7480 7481 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 7482 pte_l1_s_wc_mode = L1_S_B; 7483 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 7484 7485 pte_l2_l_cache_mode = L2_B|L2_C; 7486 pte_l2_l_wc_mode = L2_B; 7487 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 7488 7489 pte_l2_s_cache_mode = L2_B|L2_C; 7490 pte_l2_s_wc_mode = L2_B; 7491 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 7492 7493 pte_l1_s_cache_mode_pt = L1_S_C; 7494 pte_l2_l_cache_mode_pt = L2_C; 7495 pte_l2_s_cache_mode_pt = L2_C; 7496 7497 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 7498 /* 7499 * The XScale core has an enhanced mode where writes that 7500 * miss the cache cause a cache line to be allocated. This 7501 * is significantly faster than the traditional, write-through 7502 * behavior of this case. 7503 */ 7504 pte_l1_s_cache_mode |= L1_S_XS_TEX(TEX_XSCALE_X); 7505 pte_l2_l_cache_mode |= L2_XS_L_TEX(TEX_XSCALE_X); 7506 pte_l2_s_cache_mode |= L2_XS_T_TEX(TEX_XSCALE_X); 7507 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 7508 7509 #ifdef XSCALE_CACHE_WRITE_THROUGH 7510 /* 7511 * Some versions of the XScale core have various bugs in 7512 * their cache units, the work-around for which is to run 7513 * the cache in write-through mode. Unfortunately, this 7514 * has a major (negative) impact on performance. So, we 7515 * go ahead and run fast-and-loose, in the hopes that we 7516 * don't line up the planets in a way that will trip the 7517 * bugs. 7518 * 7519 * However, we give you the option to be slow-but-correct. 7520 */ 7521 write_through = 1; 7522 #elif defined(XSCALE_CACHE_WRITE_BACK) 7523 /* force write back cache mode */ 7524 write_through = 0; 7525 #elif defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 7526 /* 7527 * Intel PXA2[15]0 processors are known to have a bug in 7528 * write-back cache on revision 4 and earlier (stepping 7529 * A[01] and B[012]). Fixed for C0 and later. 7530 */ 7531 { 7532 uint32_t id, type; 7533 7534 id = cpufunc_id(); 7535 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 7536 7537 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 7538 if ((id & CPU_ID_REVISION_MASK) < 5) { 7539 /* write through for stepping A0-1 and B0-2 */ 7540 write_through = 1; 7541 } 7542 } 7543 } 7544 #endif /* XSCALE_CACHE_WRITE_THROUGH */ 7545 7546 if (write_through) { 7547 pte_l1_s_cache_mode = L1_S_C; 7548 pte_l2_l_cache_mode = L2_C; 7549 pte_l2_s_cache_mode = L2_C; 7550 } 7551 7552 #if (ARM_NMMUS > 1) 7553 xscale_use_minidata = 1; 7554 #endif 7555 7556 pte_l1_s_prot_u = L1_S_PROT_U_xscale; 7557 pte_l1_s_prot_w = L1_S_PROT_W_xscale; 7558 pte_l1_s_prot_ro = L1_S_PROT_RO_xscale; 7559 pte_l1_s_prot_mask = L1_S_PROT_MASK_xscale; 7560 7561 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 7562 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 7563 pte_l2_s_prot_ro = L2_S_PROT_RO_xscale; 7564 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 7565 7566 pte_l2_l_prot_u = L2_L_PROT_U_xscale; 7567 pte_l2_l_prot_w = L2_L_PROT_W_xscale; 7568 pte_l2_l_prot_ro = L2_L_PROT_RO_xscale; 7569 pte_l2_l_prot_mask = L2_L_PROT_MASK_xscale; 7570 7571 pte_l1_ss_proto = L1_SS_PROTO_xscale; 7572 pte_l1_s_proto = L1_S_PROTO_xscale; 7573 pte_l1_c_proto = L1_C_PROTO_xscale; 7574 pte_l2_s_proto = L2_S_PROTO_xscale; 7575 7576 pmap_copy_page_func = pmap_copy_page_xscale; 7577 pmap_zero_page_func = pmap_zero_page_xscale; 7578 7579 /* 7580 * Disable ECC protection of page table access, for now. 7581 */ 7582 auxctl = armreg_auxctl_read(); 7583 auxctl &= ~XSCALE_AUXCTL_P; 7584 armreg_auxctl_write(auxctl); 7585 } 7586 7587 /* 7588 * xscale_setup_minidata: 7589 * 7590 * Set up the mini-data cache clean area. We require the 7591 * caller to allocate the right amount of physically and 7592 * virtually contiguous space. 7593 */ 7594 void 7595 xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa) 7596 { 7597 pd_entry_t *pde = (pd_entry_t *) l1pt; 7598 vsize_t size; 7599 uint32_t auxctl; 7600 7601 xscale_minidata_clean_addr = va; 7602 7603 /* Round it to page size. */ 7604 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 7605 7606 for (; size != 0; 7607 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 7608 const size_t l1slot = l1pte_index(va); 7609 pt_entry_t *ptep = (pt_entry_t *) kernel_pt_lookup(l1pte_pa(pde[l1slot])); 7610 if (ptep == NULL) 7611 panic("xscale_setup_minidata: can't find L2 table for " 7612 "VA 0x%08lx", va); 7613 7614 ptep += l2pte_index(va); 7615 pt_entry_t opte = *ptep; 7616 l2pte_set(ptep, 7617 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) 7618 | L2_C | L2_XS_T_TEX(TEX_XSCALE_X), opte); 7619 } 7620 7621 /* 7622 * Configure the mini-data cache for write-back with 7623 * read/write-allocate. 7624 * 7625 * NOTE: In order to reconfigure the mini-data cache, we must 7626 * make sure it contains no valid data! In order to do that, 7627 * we must issue a global data cache invalidate command! 7628 * 7629 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 7630 * THIS IS VERY IMPORTANT! 7631 */ 7632 7633 /* Invalidate data and mini-data. */ 7634 __asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 7635 auxctl = armreg_auxctl_read(); 7636 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 7637 armreg_auxctl_write(auxctl); 7638 } 7639 7640 /* 7641 * Change the PTEs for the specified kernel mappings such that they 7642 * will use the mini data cache instead of the main data cache. 7643 */ 7644 void 7645 pmap_uarea(vaddr_t va) 7646 { 7647 vaddr_t next_bucket, eva; 7648 7649 #if (ARM_NMMUS > 1) 7650 if (xscale_use_minidata == 0) 7651 return; 7652 #endif 7653 7654 eva = va + USPACE; 7655 7656 while (va < eva) { 7657 next_bucket = L2_NEXT_BUCKET_VA(va); 7658 if (next_bucket > eva) 7659 next_bucket = eva; 7660 7661 struct l2_bucket *l2b = pmap_get_l2_bucket(pmap_kernel(), va); 7662 KDASSERT(l2b != NULL); 7663 7664 pt_entry_t * const sptep = &l2b->l2b_kva[l2pte_index(va)]; 7665 pt_entry_t *ptep = sptep; 7666 7667 while (va < next_bucket) { 7668 const pt_entry_t opte = *ptep; 7669 if (!l2pte_minidata_p(opte)) { 7670 cpu_dcache_wbinv_range(va, PAGE_SIZE); 7671 cpu_tlb_flushD_SE(va); 7672 l2pte_set(ptep, opte & ~L2_B, opte); 7673 } 7674 ptep += PAGE_SIZE / L2_S_SIZE; 7675 va += PAGE_SIZE; 7676 } 7677 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 7678 } 7679 cpu_cpwait(); 7680 } 7681 #endif /* ARM_MMU_XSCALE == 1 */ 7682 7683 7684 #if defined(CPU_ARM11MPCORE) 7685 void 7686 pmap_pte_init_arm11mpcore(void) 7687 { 7688 7689 /* cache mode is controlled by 5 bits (B, C, TEX[2:0]) */ 7690 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6; 7691 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6; 7692 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7693 /* use extended small page (without APn, with TEX) */ 7694 pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6; 7695 #else 7696 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c; 7697 #endif 7698 7699 /* write-back, write-allocate */ 7700 pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7701 pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01); 7702 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7703 pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7704 #else 7705 /* no TEX. read-allocate */ 7706 pte_l2_s_cache_mode = L2_C | L2_B; 7707 #endif 7708 /* 7709 * write-back, write-allocate for page tables. 7710 */ 7711 pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01); 7712 pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01); 7713 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7714 pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01); 7715 #else 7716 pte_l2_s_cache_mode_pt = L2_C | L2_B; 7717 #endif 7718 7719 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7720 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7721 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7722 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7723 7724 #if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE) 7725 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7726 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7727 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7728 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7729 7730 #else 7731 /* with AP[0..3] */ 7732 pte_l2_s_prot_u = L2_S_PROT_U_generic; 7733 pte_l2_s_prot_w = L2_S_PROT_W_generic; 7734 pte_l2_s_prot_ro = L2_S_PROT_RO_generic; 7735 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 7736 #endif 7737 7738 #ifdef ARM11MPCORE_COMPAT_MMU 7739 /* with AP[0..3] */ 7740 pte_l2_l_prot_u = L2_L_PROT_U_generic; 7741 pte_l2_l_prot_w = L2_L_PROT_W_generic; 7742 pte_l2_l_prot_ro = L2_L_PROT_RO_generic; 7743 pte_l2_l_prot_mask = L2_L_PROT_MASK_generic; 7744 7745 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7746 pte_l1_s_proto = L1_S_PROTO_armv6; 7747 pte_l1_c_proto = L1_C_PROTO_armv6; 7748 pte_l2_s_proto = L2_S_PROTO_armv6c; 7749 #else 7750 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7751 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7752 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7753 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7754 7755 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7756 pte_l1_s_proto = L1_S_PROTO_armv6; 7757 pte_l1_c_proto = L1_C_PROTO_armv6; 7758 pte_l2_s_proto = L2_S_PROTO_armv6n; 7759 #endif 7760 7761 pmap_copy_page_func = pmap_copy_page_generic; 7762 pmap_zero_page_func = pmap_zero_page_generic; 7763 pmap_needs_pte_sync = 1; 7764 } 7765 #endif /* CPU_ARM11MPCORE */ 7766 7767 7768 #if ARM_MMU_V6 == 1 7769 void 7770 pmap_pte_init_armv6(void) 7771 { 7772 /* 7773 * The ARMv6-A MMU is mostly compatible with generic. If the 7774 * AP field is zero, that now means "no access" rather than 7775 * read-only. The prototypes are a little different because of 7776 * the XN bit. 7777 */ 7778 pmap_pte_init_generic(); 7779 7780 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7781 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7782 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7783 7784 #ifdef ARM11_COMPAT_MMU 7785 /* with AP[0..3] */ 7786 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7787 #else 7788 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6n; 7789 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6n; 7790 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6n; 7791 7792 pte_l1_ss_proto = L1_SS_PROTO_armv6; 7793 pte_l1_s_proto = L1_S_PROTO_armv6; 7794 pte_l1_c_proto = L1_C_PROTO_armv6; 7795 pte_l2_s_proto = L2_S_PROTO_armv6n; 7796 7797 pte_l1_s_prot_u = L1_S_PROT_U_armv6; 7798 pte_l1_s_prot_w = L1_S_PROT_W_armv6; 7799 pte_l1_s_prot_ro = L1_S_PROT_RO_armv6; 7800 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6; 7801 7802 pte_l2_l_prot_u = L2_L_PROT_U_armv6n; 7803 pte_l2_l_prot_w = L2_L_PROT_W_armv6n; 7804 pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n; 7805 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n; 7806 7807 pte_l2_s_prot_u = L2_S_PROT_U_armv6n; 7808 pte_l2_s_prot_w = L2_S_PROT_W_armv6n; 7809 pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n; 7810 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n; 7811 7812 #endif 7813 } 7814 #endif /* ARM_MMU_V6 */ 7815 7816 #if ARM_MMU_V7 == 1 7817 void 7818 pmap_pte_init_armv7(void) 7819 { 7820 /* 7821 * The ARMv7-A MMU is mostly compatible with generic. If the 7822 * AP field is zero, that now means "no access" rather than 7823 * read-only. The prototypes are a little different because of 7824 * the XN bit. 7825 */ 7826 pmap_pte_init_generic(); 7827 7828 pmap_needs_pte_sync = 1; 7829 7830 pte_l1_s_nocache_mode = L1_S_XS_TEX(1); 7831 pte_l2_l_nocache_mode = L2_XS_L_TEX(1); 7832 pte_l2_s_nocache_mode = L2_XS_T_TEX(1); 7833 7834 pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv7; 7835 pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv7; 7836 pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv7; 7837 7838 /* 7839 * If the core support coherent walk then updates to translation tables 7840 * do not require a clean to the point of unification to ensure 7841 * visibility by subsequent translation table walks. That means we can 7842 * map everything shareable and cached and the right thing will happen. 7843 */ 7844 if (__SHIFTOUT(armreg_mmfr3_read(), __BITS(23,20))) { 7845 pmap_needs_pte_sync = 0; 7846 7847 /* 7848 * write-back, no write-allocate, shareable for normal pages. 7849 */ 7850 pte_l1_s_cache_mode |= L1_S_V6_S; 7851 pte_l2_l_cache_mode |= L2_XS_S; 7852 pte_l2_s_cache_mode |= L2_XS_S; 7853 } 7854 7855 /* 7856 * Page tables are just all other memory. We can use write-back since 7857 * pmap_needs_pte_sync is 1 (or the MMU can read out of cache). 7858 */ 7859 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode; 7860 pte_l2_l_cache_mode_pt = pte_l2_l_cache_mode; 7861 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 7862 7863 /* 7864 * Check the Memory Model Features to see if this CPU supports 7865 * the TLBIASID coproc op. 7866 */ 7867 if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(16,19)) >= 2) { 7868 arm_has_tlbiasid_p = true; 7869 } else if (__SHIFTOUT(armreg_mmfr2_read(), __BITS(12,15)) >= 2) { 7870 arm_has_tlbiasid_p = true; 7871 } 7872 7873 /* 7874 * Check the MPIDR to see if this CPU supports MP extensions. 7875 */ 7876 #ifdef MULTIPROCESSOR 7877 arm_has_mpext_p = (armreg_mpidr_read() & (MPIDR_MP|MPIDR_U)) == MPIDR_MP; 7878 #else 7879 arm_has_mpext_p = false; 7880 #endif 7881 7882 pte_l1_s_prot_u = L1_S_PROT_U_armv7; 7883 pte_l1_s_prot_w = L1_S_PROT_W_armv7; 7884 pte_l1_s_prot_ro = L1_S_PROT_RO_armv7; 7885 pte_l1_s_prot_mask = L1_S_PROT_MASK_armv7; 7886 7887 pte_l2_s_prot_u = L2_S_PROT_U_armv7; 7888 pte_l2_s_prot_w = L2_S_PROT_W_armv7; 7889 pte_l2_s_prot_ro = L2_S_PROT_RO_armv7; 7890 pte_l2_s_prot_mask = L2_S_PROT_MASK_armv7; 7891 7892 pte_l2_l_prot_u = L2_L_PROT_U_armv7; 7893 pte_l2_l_prot_w = L2_L_PROT_W_armv7; 7894 pte_l2_l_prot_ro = L2_L_PROT_RO_armv7; 7895 pte_l2_l_prot_mask = L2_L_PROT_MASK_armv7; 7896 7897 pte_l1_ss_proto = L1_SS_PROTO_armv7; 7898 pte_l1_s_proto = L1_S_PROTO_armv7; 7899 pte_l1_c_proto = L1_C_PROTO_armv7; 7900 pte_l2_s_proto = L2_S_PROTO_armv7; 7901 7902 } 7903 #endif /* ARM_MMU_V7 */ 7904 7905 /* 7906 * return the PA of the current L1 table, for use when handling a crash dump 7907 */ 7908 uint32_t 7909 pmap_kernel_L1_addr(void) 7910 { 7911 #ifdef ARM_MMU_EXTENDED 7912 return pmap_kernel()->pm_l1_pa; 7913 #else 7914 return pmap_kernel()->pm_l1->l1_physaddr; 7915 #endif 7916 } 7917 7918 #if defined(DDB) 7919 /* 7920 * A couple of ddb-callable functions for dumping pmaps 7921 */ 7922 void pmap_dump(pmap_t); 7923 7924 static pt_entry_t ncptes[64]; 7925 static void pmap_dump_ncpg(pmap_t); 7926 7927 void 7928 pmap_dump(pmap_t pm) 7929 { 7930 struct l2_dtable *l2; 7931 struct l2_bucket *l2b; 7932 pt_entry_t *ptep, pte; 7933 vaddr_t l2_va, l2b_va, va; 7934 int i, j, k, occ, rows = 0; 7935 7936 if (pm == pmap_kernel()) 7937 printf("pmap_kernel (%p): ", pm); 7938 else 7939 printf("user pmap (%p): ", pm); 7940 7941 #ifdef ARM_MMU_EXTENDED 7942 printf("l1 at %p\n", pmap_l1_kva(pm)); 7943 #else 7944 printf("domain %d, l1 at %p\n", pmap_domain(pm), pmap_l1_kva(pm)); 7945 #endif 7946 7947 l2_va = 0; 7948 for (i = 0; i < L2_SIZE; i++, l2_va += 0x01000000) { 7949 l2 = pm->pm_l2[i]; 7950 7951 if (l2 == NULL || l2->l2_occupancy == 0) 7952 continue; 7953 7954 l2b_va = l2_va; 7955 for (j = 0; j < L2_BUCKET_SIZE; j++, l2b_va += 0x00100000) { 7956 l2b = &l2->l2_bucket[j]; 7957 7958 if (l2b->l2b_occupancy == 0 || l2b->l2b_kva == NULL) 7959 continue; 7960 7961 ptep = l2b->l2b_kva; 7962 7963 for (k = 0; k < 256 && ptep[k] == 0; k++) 7964 ; 7965 7966 k &= ~63; 7967 occ = l2b->l2b_occupancy; 7968 va = l2b_va + (k * 4096); 7969 for (; k < 256; k++, va += 0x1000) { 7970 char ch = ' '; 7971 if ((k % 64) == 0) { 7972 if ((rows % 8) == 0) { 7973 printf( 7974 " |0000 |8000 |10000 |18000 |20000 |28000 |30000 |38000\n"); 7975 } 7976 printf("%08lx: ", va); 7977 } 7978 7979 ncptes[k & 63] = 0; 7980 pte = ptep[k]; 7981 if (pte == 0) { 7982 ch = '.'; 7983 } else { 7984 occ--; 7985 switch (pte & 0x4c) { 7986 case 0x00: 7987 ch = 'N'; /* No cache No buff */ 7988 break; 7989 case 0x04: 7990 ch = 'B'; /* No cache buff */ 7991 break; 7992 case 0x08: 7993 ch = 'C'; /* Cache No buff */ 7994 break; 7995 case 0x0c: 7996 ch = 'F'; /* Cache Buff */ 7997 break; 7998 case 0x40: 7999 ch = 'D'; 8000 break; 8001 case 0x48: 8002 ch = 'm'; /* Xscale mini-data */ 8003 break; 8004 default: 8005 ch = '?'; 8006 break; 8007 } 8008 8009 if ((pte & L2_S_PROT_U) == L2_S_PROT_U) 8010 ch += 0x20; 8011 8012 if ((pte & 0xc) == 0) 8013 ncptes[k & 63] = pte; 8014 } 8015 8016 if ((k % 64) == 63) { 8017 rows++; 8018 printf("%c\n", ch); 8019 pmap_dump_ncpg(pm); 8020 if (occ == 0) 8021 break; 8022 } else 8023 printf("%c", ch); 8024 } 8025 } 8026 } 8027 } 8028 8029 static void 8030 pmap_dump_ncpg(pmap_t pm) 8031 { 8032 struct vm_page *pg; 8033 struct vm_page_md *md; 8034 struct pv_entry *pv; 8035 int i; 8036 8037 for (i = 0; i < 63; i++) { 8038 if (ncptes[i] == 0) 8039 continue; 8040 8041 pg = PHYS_TO_VM_PAGE(l2pte_pa(ncptes[i])); 8042 if (pg == NULL) 8043 continue; 8044 md = VM_PAGE_TO_MD(pg); 8045 8046 printf(" pa 0x%08lx: krw %d kro %d urw %d uro %d\n", 8047 VM_PAGE_TO_PHYS(pg), 8048 md->krw_mappings, md->kro_mappings, 8049 md->urw_mappings, md->uro_mappings); 8050 8051 SLIST_FOREACH(pv, &md->pvh_list, pv_link) { 8052 printf(" %c va 0x%08lx, flags 0x%x\n", 8053 (pm == pv->pv_pmap) ? '*' : ' ', 8054 pv->pv_va, pv->pv_flags); 8055 } 8056 } 8057 } 8058 #endif 8059 8060 #ifdef PMAP_STEAL_MEMORY 8061 void 8062 pmap_boot_pageadd(pv_addr_t *newpv) 8063 { 8064 pv_addr_t *pv, *npv; 8065 8066 if ((pv = SLIST_FIRST(&pmap_boot_freeq)) != NULL) { 8067 if (newpv->pv_pa < pv->pv_va) { 8068 KASSERT(newpv->pv_pa + newpv->pv_size <= pv->pv_pa); 8069 if (newpv->pv_pa + newpv->pv_size == pv->pv_pa) { 8070 newpv->pv_size += pv->pv_size; 8071 SLIST_REMOVE_HEAD(&pmap_boot_freeq, pv_list); 8072 } 8073 pv = NULL; 8074 } else { 8075 for (; (npv = SLIST_NEXT(pv, pv_list)) != NULL; 8076 pv = npv) { 8077 KASSERT(pv->pv_pa + pv->pv_size < npv->pv_pa); 8078 KASSERT(pv->pv_pa < newpv->pv_pa); 8079 if (newpv->pv_pa > npv->pv_pa) 8080 continue; 8081 if (pv->pv_pa + pv->pv_size == newpv->pv_pa) { 8082 pv->pv_size += newpv->pv_size; 8083 return; 8084 } 8085 if (newpv->pv_pa + newpv->pv_size < npv->pv_pa) 8086 break; 8087 newpv->pv_size += npv->pv_size; 8088 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8089 SLIST_REMOVE_AFTER(newpv, pv_list); 8090 return; 8091 } 8092 } 8093 } 8094 8095 if (pv) { 8096 SLIST_INSERT_AFTER(pv, newpv, pv_list); 8097 } else { 8098 SLIST_INSERT_HEAD(&pmap_boot_freeq, newpv, pv_list); 8099 } 8100 } 8101 8102 void 8103 pmap_boot_pagealloc(psize_t amount, psize_t mask, psize_t match, 8104 pv_addr_t *rpv) 8105 { 8106 pv_addr_t *pv, **pvp; 8107 8108 KASSERT(amount & PGOFSET); 8109 KASSERT((mask & PGOFSET) == 0); 8110 KASSERT((match & PGOFSET) == 0); 8111 KASSERT(amount != 0); 8112 8113 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8114 (pv = *pvp) != NULL; 8115 pvp = &SLIST_NEXT(pv, pv_list)) { 8116 pv_addr_t *newpv; 8117 psize_t off; 8118 /* 8119 * If this entry is too small to satisfy the request... 8120 */ 8121 KASSERT(pv->pv_size > 0); 8122 if (pv->pv_size < amount) 8123 continue; 8124 8125 for (off = 0; off <= mask; off += PAGE_SIZE) { 8126 if (((pv->pv_pa + off) & mask) == match 8127 && off + amount <= pv->pv_size) 8128 break; 8129 } 8130 if (off > mask) 8131 continue; 8132 8133 rpv->pv_va = pv->pv_va + off; 8134 rpv->pv_pa = pv->pv_pa + off; 8135 rpv->pv_size = amount; 8136 pv->pv_size -= amount; 8137 if (pv->pv_size == 0) { 8138 KASSERT(off == 0); 8139 KASSERT((vaddr_t) pv == rpv->pv_va); 8140 *pvp = SLIST_NEXT(pv, pv_list); 8141 } else if (off == 0) { 8142 KASSERT((vaddr_t) pv == rpv->pv_va); 8143 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8144 *newpv = *pv; 8145 newpv->pv_pa += amount; 8146 newpv->pv_va += amount; 8147 *pvp = newpv; 8148 } else if (off < pv->pv_size) { 8149 newpv = (pv_addr_t *) (rpv->pv_va + amount); 8150 *newpv = *pv; 8151 newpv->pv_size -= off; 8152 newpv->pv_pa += off + amount; 8153 newpv->pv_va += off + amount; 8154 8155 SLIST_NEXT(pv, pv_list) = newpv; 8156 pv->pv_size = off; 8157 } else { 8158 KASSERT((vaddr_t) pv != rpv->pv_va); 8159 } 8160 memset((void *)rpv->pv_va, 0, amount); 8161 return; 8162 } 8163 8164 if (!uvm_physseg_valid_p(uvm_physseg_get_first())) 8165 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8166 8167 for (pvp = &SLIST_FIRST(&pmap_boot_freeq); 8168 (pv = *pvp) != NULL; 8169 pvp = &SLIST_NEXT(pv, pv_list)) { 8170 if (SLIST_NEXT(pv, pv_list) == NULL) 8171 break; 8172 } 8173 KASSERT(mask == 0); 8174 8175 for (uvm_physseg_t ups = uvm_physseg_get_first(); 8176 uvm_physseg_valid_p(ups); 8177 ups = uvm_physseg_get_next(ups)) { 8178 8179 paddr_t spn = uvm_physseg_get_start(ups); 8180 paddr_t epn = uvm_physseg_get_end(ups); 8181 if (spn == atop(pv->pv_pa + pv->pv_size) 8182 && pv->pv_va + pv->pv_size <= ptoa(epn)) { 8183 rpv->pv_va = pv->pv_va; 8184 rpv->pv_pa = pv->pv_pa; 8185 rpv->pv_size = amount; 8186 *pvp = NULL; 8187 pmap_map_chunk(kernel_l1pt.pv_va, 8188 ptoa(spn) + (pv->pv_va - pv->pv_pa), 8189 ptoa(spn), 8190 amount - pv->pv_size, 8191 VM_PROT_READ|VM_PROT_WRITE, 8192 PTE_CACHE); 8193 8194 uvm_physseg_unplug(spn, atop(amount - pv->pv_size)); 8195 memset((void *)rpv->pv_va, 0, rpv->pv_size); 8196 return; 8197 } 8198 } 8199 8200 panic("pmap_boot_pagealloc: couldn't allocate memory"); 8201 } 8202 8203 vaddr_t 8204 pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp) 8205 { 8206 pv_addr_t pv; 8207 8208 pmap_boot_pagealloc(size, 0, 0, &pv); 8209 8210 return pv.pv_va; 8211 } 8212 #endif /* PMAP_STEAL_MEMORY */ 8213 8214 SYSCTL_SETUP(sysctl_machdep_pmap_setup, "sysctl machdep.kmpages setup") 8215 { 8216 sysctl_createv(clog, 0, NULL, NULL, 8217 CTLFLAG_PERMANENT, 8218 CTLTYPE_NODE, "machdep", NULL, 8219 NULL, 0, NULL, 0, 8220 CTL_MACHDEP, CTL_EOL); 8221 8222 sysctl_createv(clog, 0, NULL, NULL, 8223 CTLFLAG_PERMANENT, 8224 CTLTYPE_INT, "kmpages", 8225 SYSCTL_DESCR("count of pages allocated to kernel memory allocators"), 8226 NULL, 0, &pmap_kmpages, 0, 8227 CTL_MACHDEP, CTL_CREATE, CTL_EOL); 8228 } 8229 8230 #ifdef PMAP_NEED_ALLOC_POOLPAGE 8231 struct vm_page * 8232 arm_pmap_alloc_poolpage(int flags) 8233 { 8234 /* 8235 * On some systems, only some pages may be "coherent" for dma and we 8236 * want to prefer those for pool pages (think mbufs) but fallback to 8237 * any page if none is available. 8238 */ 8239 if (arm_poolpage_vmfreelist != VM_FREELIST_DEFAULT) { 8240 return uvm_pagealloc_strat(NULL, 0, NULL, flags, 8241 UVM_PGA_STRAT_FALLBACK, arm_poolpage_vmfreelist); 8242 } 8243 8244 return uvm_pagealloc(NULL, 0, NULL, flags); 8245 } 8246 #endif 8247 8248 #if defined(ARM_MMU_EXTENDED) && defined(MULTIPROCESSOR) 8249 void 8250 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci) 8251 { 8252 /* nothing */ 8253 } 8254 8255 int 8256 pic_ipi_shootdown(void *arg) 8257 { 8258 #if PMAP_TLB_NEED_SHOOTDOWN 8259 pmap_tlb_shootdown_process(); 8260 #endif 8261 return 1; 8262 } 8263 #endif /* ARM_MMU_EXTENDED && MULTIPROCESSOR */ 8264 8265 8266 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 8267 vaddr_t 8268 pmap_direct_mapped_phys(paddr_t pa, bool *ok_p, vaddr_t va) 8269 { 8270 bool ok = false; 8271 if (physical_start <= pa && pa < physical_end) { 8272 #ifdef KERNEL_BASE_VOFFSET 8273 const vaddr_t newva = pa + KERNEL_BASE_VOFFSET; 8274 #else 8275 const vaddr_t newva = KERNEL_BASE + pa - physical_start; 8276 #endif 8277 #ifdef ARM_MMU_EXTENDED 8278 if (newva >= KERNEL_BASE && newva < pmap_directlimit) { 8279 #endif 8280 va = newva; 8281 ok = true; 8282 #ifdef ARM_MMU_EXTENDED 8283 } 8284 #endif 8285 } 8286 KASSERT(ok_p); 8287 *ok_p = ok; 8288 return va; 8289 } 8290 8291 vaddr_t 8292 pmap_map_poolpage(paddr_t pa) 8293 { 8294 bool ok __diagused; 8295 vaddr_t va = pmap_direct_mapped_phys(pa, &ok, 0); 8296 KASSERTMSG(ok, "pa %#lx not direct mappable", pa); 8297 #if defined(PMAP_CACHE_VIPT) && !defined(ARM_MMU_EXTENDED) 8298 if (arm_cache_prefer_mask != 0) { 8299 struct vm_page * const pg = PHYS_TO_VM_PAGE(pa); 8300 struct vm_page_md * const md = VM_PAGE_TO_MD(pg); 8301 pmap_acquire_page_lock(md); 8302 pmap_vac_me_harder(md, pa, pmap_kernel(), va); 8303 pmap_release_page_lock(md); 8304 } 8305 #endif 8306 return va; 8307 } 8308 8309 paddr_t 8310 pmap_unmap_poolpage(vaddr_t va) 8311 { 8312 KASSERT(va >= KERNEL_BASE); 8313 #ifdef PMAP_CACHE_VIVT 8314 cpu_idcache_wbinv_range(va, PAGE_SIZE); 8315 #endif 8316 #if defined(KERNEL_BASE_VOFFSET) 8317 return va - KERNEL_BASE_VOFFSET; 8318 #else 8319 return va - KERNEL_BASE + physical_start; 8320 #endif 8321 } 8322 #endif /* __HAVE_MM_MD_DIRECT_MAPPED_PHYS */ 8323
Indexes created Sat Sep 20 22:09:52 GMT 2025