| /src/sys/external/bsd/drm2/include/linux/ |
| perf_event.h | 37 struct pmu { struct
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| arm-realview-pba8.dts | 43 pmu: pmu@0 { label
44 compatible = "arm,cortex-a8-pmu";
|
| arm-realview-eb-mp.dtsi | 105 /* PMU with one IRQ line per core */
106 pmu: pmu@0 { label
107 compatible = "arm,arm11mpcore-pmu";
|
| arm-realview-pbx-a9.dts | 100 pmu: pmu@0 { label
101 compatible = "arm,cortex-a9-pmu";
|
| bcm28155-ap.dts | 52 pmu: pmu@8 { label
90 &pmu {
|
| mstar-v7.dtsi | 44 pmu: pmu { label
45 compatible = "arm,cortex-a7-pmu";
|
| imx51.dtsi | 94 pmu: pmu { label
95 compatible = "arm,cortex-a8-pmu";
|
| meson8.dtsi | 162 pmu {
163 compatible = "arm,cortex-a9-pmu";
302 interrupt-names = "gp", "gpmmu", "pp", "pmu",
344 pmu: pmu@e0 { label
345 compatible = "amlogic,meson8-pmu", "syscon";
622 amlogic,ao-sysctrl = <&pmu>;
|
| meson8b.dtsi | 154 pmu {
155 compatible = "arm,cortex-a5-pmu";
271 interrupt-names = "gp", "gpmmu", "pp", "pmu",
306 pmu: pmu@e0 { label
307 compatible = "amlogic,meson8b-pmu", "syscon";
600 amlogic,ao-sysctrl = <&pmu>;
|
| omap4.dtsi | 220 * events are not supported for pmu. Note that 4460 does not use
232 pmu: pmu { label
233 compatible = "arm,cortex-a9-pmu";
|
| rk3xxx.dtsi | 253 pmu: pmu@20004000 { label
254 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| k3-am64.dtsi | 57 pmu: pmu { label
58 compatible = "arm,cortex-a53-pmu";
|
| k3-am65.dtsi | 58 pmu: pmu { label
59 compatible = "arm,cortex-a53-pmu";
|
| k3-j7200.dtsi | 116 pmu: pmu { label
117 compatible = "arm,cortex-a72-pmu";
|
| k3-j721e.dtsi | 117 pmu: pmu { label
118 compatible = "arm,cortex-a72-pmu";
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/ |
| nouveau_nvkm_subdev_pmu_gp10b.c | 32 #include <nvfw/pmu.h>
45 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); local in function:gp10b_pmu_acr_bootstrap_multiple_falcons
57 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
59 &pmu->subdev, msecs_to_jiffies(1000));
91 MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
92 MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
93 MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
|
| nouveau_nvkm_subdev_pmu_base.c | 37 struct nvkm_pmu *pmu = device->pmu; local in function:nvkm_pmu_fan_controlled
39 /* Internal PMU FW does not currently control fans in any way,
42 if (pmu && pmu->func->code.size)
45 /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi
53 nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
55 if (pmu && pmu->func->pgob
62 struct nvkm_pmu *pmu = container_of(work, typeof(*pmu), recv.work); local in function:nvkm_pmu_recv
78 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_intr
87 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_fini
133 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_preinit
140 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_init
150 struct nvkm_pmu *pmu = nvkm_pmu(subdev); local in function:nvkm_pmu_dtor
212 struct nvkm_pmu *pmu; local in function:nvkm_pmu_new_
[all...] |
| nouveau_nvkm_subdev_pmu_gm20b.c | 33 #include <nvfw/pmu.h>
47 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); local in function:gm20b_pmu_acr_bootstrap_falcon
57 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
59 &pmu->subdev, msecs_to_jiffies(1000));
142 struct nvkm_pmu *pmu = priv; local in function:gm20b_pmu_acr_init_wpr_callback
143 struct nvkm_subdev *subdev = &pmu->subdev;
152 complete_all(&pmu->wpr_ready);
157 gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu)
167 return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr
[all...] |
| nouveau_nvkm_subdev_pmu_gk20a.c | 56 gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state)
58 struct nvkm_clk *clk = pmu->base.subdev.device->clk;
64 gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state)
66 struct nvkm_clk *clk = pmu->base.subdev.device->clk;
72 gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu,
75 struct gk20a_pmu_dvfs_data *data = pmu->data;
76 struct nvkm_clk *clk = pmu->base.subdev.device->clk;
91 nvkm_trace(&pmu->base.subdev, "cur level = %d, new level = %d\n",
100 gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu,
103 struct nvkm_falcon *falcon = &pmu->base.falcon
121 struct gk20a_pmu *pmu = local in function:gk20a_pmu_dvfs_work
220 struct gk20a_pmu *pmu; local in function:gk20a_pmu_new
[all...] |
| nouveau_nvkm_subdev_pmu_memx.c | 12 struct nvkm_pmu *pmu; member in struct:nvkm_memx
25 struct nvkm_device *device = memx->pmu->subdev.device;
49 nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
51 struct nvkm_device *device = pmu->subdev.device;
56 ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
64 memx->pmu = pmu;
80 struct nvkm_pmu *pmu = memx->pmu; local in function:nvkm_memx_fini
81 struct nvkm_subdev *subdev = &pmu->subdev
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_pmu.c | 39 /* record to keep track of pmu entry per pmu type per device */
43 struct pmu pmu; member in struct:amdgpu_pmu_entry
55 /* test the event attr type check for PMU enumeration */
56 if (event->attr.type != event->pmu->type)
69 struct amdgpu_pmu_entry *pe = container_of(event->pmu,
71 pmu);
98 struct amdgpu_pmu_entry *pe = container_of(event->pmu,
100 pmu);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_gm200.c | 33 #include <subdev/bios/pmu.h>
37 pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
43 nvkm_wr32(device, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
46 nvkm_wr32(device, 0x10a188, (pmu + i) >> 8);
57 pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len)
63 nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu);
92 struct nvbios_pmuR pmu; local in function:pmu_load
94 if (!nvbios_pmuRm(bios, type, &pmu))
100 pmu_code(init, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false)
148 u32 pmu = pmu_args(init, args + 0x08, 0x08); local in function:gm200_devinit_post
156 u32 pmu = pmu_args(init, args + 0x08, 0x10); local in function:gm200_devinit_post
[all...] |
| /src/sys/arch/sparc64/dev/ |
| pckbc_ebus.c | 191 int pmu = 0; local in function:pckbc_ebus_attach
196 pmu = node;
201 if (pmu != 0) {
207 aprint_error(": unable to map PMU cmd register\n");
212 aprint_error(": unable to map PMU data register\n");
|
| /src/sys/external/mit/xen-include-public/dist/xen/include/public/ |
| pmu.h | 28 #include "arch-x86/pmu.h"
42 * @cmd == XENPMU_* (PMU operation)
46 #define XENPMU_mode_get 0 /* Also used for getting PMU version */
72 /* PMU modes:
73 * - XENPMU_MODE_OFF: No PMU virtualization
86 * PMU features:
102 * Shared PMU data between hypervisor and PV(H) domains.
104 * The hypervisor fills out this structure during PMU interrupt and sends an
108 * by both the hypervisor and the guest (see arch-$arch/pmu.h).
130 struct xen_pmu_arch pmu; member in struct:xen_pmu_data
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/apm/ |
| apm-shadowcat.dtsi | 206 pmu {
508 pmu: pmu@78810000 { label
509 compatible = "apm,xgene-pmu-v2";
520 compatible = "apm,xgene-pmu-l3c";
525 compatible = "apm,xgene-pmu-iob";
530 compatible = "apm,xgene-pmu-mcb";
536 compatible = "apm,xgene-pmu-mcb";
542 compatible = "apm,xgene-pmu-mc";
548 compatible = "apm,xgene-pmu-mc"
[all...] |
