1 /* $NetBSD: vga_pci.c,v 1.59 2022/09/25 17:52:25 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: vga_pci.c,v 1.59 2022/09/25 17:52:25 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciio.h> 42 43 #include <dev/ic/mc6845reg.h> 44 #include <dev/ic/pcdisplayvar.h> 45 #include <dev/ic/vgareg.h> 46 #include <dev/ic/vgavar.h> 47 #include <dev/pci/vga_pcivar.h> 48 49 #include <dev/isa/isareg.h> /* For legacy VGA address ranges */ 50 51 #include <dev/wscons/wsconsio.h> 52 #include <dev/wscons/wsdisplayvar.h> 53 #include <dev/pci/wsdisplay_pci.h> 54 55 #include "opt_vga.h" 56 57 #ifdef VGA_POST 58 # if defined(__i386__) || defined(__amd64__) 59 # include "acpica.h" 60 # endif 61 #include <x86/vga_post.h> 62 #endif 63 64 #define NBARS 6 /* number of PCI BARs */ 65 66 struct vga_bar { 67 bus_addr_t vb_base; 68 bus_size_t vb_size; 69 pcireg_t vb_type; 70 int vb_flags; 71 }; 72 73 struct vga_pci_softc { 74 struct vga_softc sc_vga; 75 76 pci_chipset_tag_t sc_pc; 77 pcitag_t sc_pcitag; 78 79 struct vga_bar sc_bars[NBARS]; 80 struct vga_bar sc_rom; 81 82 #ifdef VGA_POST 83 struct vga_post *sc_posth; 84 #endif 85 86 struct pci_attach_args sc_paa; 87 }; 88 89 static int vga_pci_match(device_t, cfdata_t, void *); 90 static void vga_pci_attach(device_t, device_t, void *); 91 static int vga_pci_rescan(device_t, const char *, const int *); 92 static int vga_pci_lookup_quirks(struct pci_attach_args *); 93 static bool vga_pci_resume(device_t dv, const pmf_qual_t *); 94 95 CFATTACH_DECL2_NEW(vga_pci, sizeof(struct vga_pci_softc), 96 vga_pci_match, vga_pci_attach, NULL, NULL, vga_pci_rescan, NULL); 97 98 static int vga_pci_ioctl(void *, u_long, void *, int, struct lwp *); 99 static paddr_t vga_pci_mmap(void *, off_t, int); 100 101 static const struct vga_funcs vga_pci_funcs = { 102 vga_pci_ioctl, 103 vga_pci_mmap, 104 }; 105 106 static const struct { 107 int id; 108 int quirks; 109 } vga_pci_quirks[] = { 110 {PCI_ID_CODE(PCI_VENDOR_SILMOTION, PCI_PRODUCT_SILMOTION_SM712), 111 VGA_QUIRK_NOFASTSCROLL}, 112 {PCI_ID_CODE(PCI_VENDOR_CYRIX, PCI_PRODUCT_CYRIX_CX5530_VIDEO), 113 VGA_QUIRK_NOFASTSCROLL}, 114 }; 115 116 static const struct { 117 int vid; 118 int quirks; 119 } vga_pci_vquirks[] = { 120 {PCI_VENDOR_ATI, VGA_QUIRK_ONEFONT}, 121 }; 122 123 static int 124 vga_pci_lookup_quirks(struct pci_attach_args *pa) 125 { 126 int i; 127 128 for (i = 0; i < sizeof(vga_pci_quirks) / sizeof (vga_pci_quirks[0]); 129 i++) { 130 if (vga_pci_quirks[i].id == pa->pa_id) 131 return (vga_pci_quirks[i].quirks); 132 } 133 for (i = 0; i < sizeof(vga_pci_vquirks) / sizeof (vga_pci_vquirks[0]); 134 i++) { 135 if (vga_pci_vquirks[i].vid == PCI_VENDOR(pa->pa_id)) 136 return (vga_pci_vquirks[i].quirks); 137 } 138 return (0); 139 } 140 141 static int 142 vga_pci_match(device_t parent, cfdata_t match, void *aux) 143 { 144 struct pci_attach_args *pa = aux; 145 int potential; 146 147 potential = 0; 148 149 /* 150 * If it's prehistoric/vga or display/vga, we might match. 151 * For the console device, this is just a sanity check. 152 */ 153 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PREHISTORIC && 154 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PREHISTORIC_VGA) 155 potential = 1; 156 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 157 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA) 158 potential = 1; 159 160 if (!potential) 161 return (0); 162 163 /* check whether it is disabled by firmware */ 164 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 165 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 166 != (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 167 return (0); 168 169 /* If it's the console, we have a winner! */ 170 if (vga_is_console(pa->pa_iot, WSDISPLAY_TYPE_PCIVGA)) 171 return (1); 172 173 /* 174 * If we might match, make sure that the card actually looks OK. 175 */ 176 if (!vga_common_probe(pa->pa_iot, pa->pa_memt)) 177 return (0); 178 179 return (1); 180 } 181 182 static void 183 vga_pci_attach(device_t parent, device_t self, void *aux) 184 { 185 struct vga_pci_softc *psc = device_private(self); 186 struct vga_softc *sc = &psc->sc_vga; 187 struct pci_attach_args *pa = aux; 188 int bar, reg; 189 190 sc->sc_dev = self; 191 psc->sc_pc = pa->pa_pc; 192 psc->sc_pcitag = pa->pa_tag; 193 psc->sc_paa = *pa; 194 195 pci_aprint_devinfo(pa, NULL); 196 197 /* 198 * Gather info about all the BARs. These are used to allow 199 * the X server to map the VGA device. 200 */ 201 for (bar = 0; bar < NBARS; bar++) { 202 reg = PCI_MAPREG_START + (bar * 4); 203 if (!pci_mapreg_probe(psc->sc_pc, psc->sc_pcitag, reg, 204 &psc->sc_bars[bar].vb_type)) { 205 /* there is no valid mapping register */ 206 continue; 207 } 208 if (PCI_MAPREG_TYPE(psc->sc_bars[bar].vb_type) == 209 PCI_MAPREG_TYPE_IO) { 210 /* Don't bother fetching I/O BARs. */ 211 continue; 212 } 213 #ifndef __LP64__ 214 if (PCI_MAPREG_MEM_TYPE(psc->sc_bars[bar].vb_type) == 215 PCI_MAPREG_MEM_TYPE_64BIT) { 216 /* XXX */ 217 aprint_error_dev(self, 218 "WARNING: ignoring 64-bit BAR @ 0x%02x\n", reg); 219 bar++; 220 continue; 221 } 222 #endif 223 if (pci_mapreg_info(psc->sc_pc, psc->sc_pcitag, reg, 224 psc->sc_bars[bar].vb_type, 225 &psc->sc_bars[bar].vb_base, 226 &psc->sc_bars[bar].vb_size, 227 &psc->sc_bars[bar].vb_flags)) 228 aprint_error_dev(self, 229 "WARNING: strange BAR @ 0x%02x\n", reg); 230 } 231 232 /* 233 * Disable INTx interrupts, there is no specific chipset driver for 234 * this PCI device. Else unhandled display adapter interrupts 235 * might freeze the CPU. 236 */ 237 pcireg_t cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 238 PCI_COMMAND_STATUS_REG); 239 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 240 cmd | PCI_COMMAND_INTERRUPT_DISABLE); 241 242 /* XXX Expansion ROM? */ 243 244 vga_common_attach(sc, pa->pa_iot, pa->pa_memt, WSDISPLAY_TYPE_PCIVGA, 245 vga_pci_lookup_quirks(pa), &vga_pci_funcs); 246 247 #ifdef VGA_POST 248 psc->sc_posth = vga_post_init(pa->pa_bus, pa->pa_device, 249 pa->pa_function); 250 if (psc->sc_posth == NULL) 251 aprint_error_dev(self, 252 "WARNING: could not prepare POST handler\n"); 253 #endif 254 255 /* 256 * XXX Do not use the generic PCI framework for now as 257 * XXX it would power down the device when the console 258 * XXX is still using it. 259 */ 260 if (!pmf_device_register(self, NULL, vga_pci_resume)) 261 aprint_error_dev(self, "couldn't establish power handler\n"); 262 config_found(self, aux, vga_drm_print, 263 CFARGS(.iattr = "drm")); 264 } 265 266 static int 267 vga_pci_rescan(device_t self, const char *ifattr, const int *locators) 268 { 269 struct vga_pci_softc *psc = device_private(self); 270 271 config_found(self, &psc->sc_paa, vga_drm_print, 272 CFARGS(.iattr = "drm")); 273 274 return 0; 275 } 276 277 static bool 278 vga_pci_resume(device_t dv, const pmf_qual_t *qual) 279 { 280 #if defined(VGA_POST) && NACPICA > 0 281 extern int acpi_md_vbios_reset; 282 #endif 283 struct vga_pci_softc *sc = device_private(dv); 284 285 vga_resume(&sc->sc_vga); 286 287 #if defined(VGA_POST) && NACPICA > 0 288 if (sc->sc_posth != NULL && acpi_md_vbios_reset == 2) 289 vga_post_call(sc->sc_posth); 290 #endif 291 292 return true; 293 } 294 295 int 296 vga_pci_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 297 pci_chipset_tag_t pc, int bus, int device, 298 int function) 299 { 300 301 return (vga_cnattach(iot, memt, WSDISPLAY_TYPE_PCIVGA, 0)); 302 } 303 304 int 305 vga_drm_print(void *aux, const char *pnp) 306 { 307 if (pnp) 308 aprint_normal("drm at %s", pnp); 309 return (UNCONF); 310 } 311 312 313 static int 314 vga_pci_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l) 315 { 316 struct vga_config *vc = v; 317 struct vga_pci_softc *psc = (void *) vc->softc; 318 319 switch (cmd) { 320 /* PCI config read/write passthrough. */ 321 case PCI_IOC_CFGREAD: 322 case PCI_IOC_CFGWRITE: 323 return pci_devioctl(psc->sc_pc, psc->sc_pcitag, 324 cmd, data, flag, l); 325 326 case WSDISPLAYIO_GET_BUSID: 327 return wsdisplayio_busid_pci(vc->softc->sc_dev, 328 psc->sc_pc, psc->sc_pcitag, data); 329 330 default: 331 return EPASSTHROUGH; 332 } 333 } 334 335 static paddr_t 336 vga_pci_mmap(void *v, off_t offset, int prot) 337 { 338 struct vga_config *vc = v; 339 struct vga_pci_softc *psc = (void *) vc->softc; 340 struct vga_bar *vb; 341 int bar; 342 343 for (bar = 0; bar < NBARS; bar++) { 344 vb = &psc->sc_bars[bar]; 345 if (vb->vb_size == 0) 346 continue; 347 if (offset >= vb->vb_base && 348 offset < (vb->vb_base + vb->vb_size)) { 349 /* XXX This the right thing to do with flags? */ 350 return (bus_space_mmap(vc->hdl.vh_memt, vb->vb_base, 351 (offset - vb->vb_base), prot, vb->vb_flags)); 352 } 353 } 354 355 /* XXX Expansion ROM? */ 356 357 /* 358 * Allow mmap access to the legacy ISA hole. This is where 359 * the legacy video BIOS will be located, and also where 360 * the legacy VGA display buffer is located. 361 * 362 * XXX Security implications, here? 363 */ 364 if (offset >= IOM_BEGIN && offset < IOM_END) 365 return (bus_space_mmap(vc->hdl.vh_memt, IOM_BEGIN, 366 (offset - IOM_BEGIN), prot, 0)); 367 368 #ifdef PCI_MAGIC_IO_RANGE 369 /* allow to map our IO space on non-x86 machines */ 370 if ((offset >= PCI_MAGIC_IO_RANGE) && 371 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 372 return bus_space_mmap(vc->hdl.vh_iot, 373 offset - PCI_MAGIC_IO_RANGE, 374 0, prot, BUS_SPACE_MAP_LINEAR); 375 } 376 #endif 377 378 /* Range not found. */ 379 return (-1); 380 } 381
Indexes created Sun Sep 21 20:09:37 GMT 2025