1 /* $NetBSD: bus_defs.h,v 1.5 2022/03/10 00:14:16 riastradh Exp $ */ 2 /* $OpenBSD: bus.h,v 1.1 1997/10/13 10:53:42 pefo Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 36 * Copyright (c) 1996 Jason R. Thorpe. All rights reserved. 37 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * Copyright (c) 1997 Per Fogelstrom. All rights reserved. 68 * Copyright (c) 1996 Niklas Hallqvist. All rights reserved. 69 * 70 * Redistribution and use in source and binary forms, with or without 71 * modification, are permitted provided that the following conditions 72 * are met: 73 * 1. Redistributions of source code must retain the above copyright 74 * notice, this list of conditions and the following disclaimer. 75 * 2. Redistributions in binary form must reproduce the above copyright 76 * notice, this list of conditions and the following disclaimer in the 77 * documentation and/or other materials provided with the distribution. 78 * 3. All advertising materials mentioning features or use of this software 79 * must display the following acknowledgement: 80 * This product includes software developed by Christopher G. Demetriou 81 * for the NetBSD Project. 82 * 4. The name of the author may not be used to endorse or promote products 83 * derived from this software without specific prior written permission 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 86 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 87 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 88 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 89 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 90 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 91 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 92 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 93 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 94 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 95 */ 96 97 #ifndef _POWERPC_BUS_DEFS_H_ 98 #define _POWERPC_BUS_DEFS_H_ 99 100 #ifdef _KERNEL_OPT 101 #include "opt_ppcarch.h" 102 #endif 103 104 #ifndef BUS_DMA_DONTCACHE 105 #if defined(PPC_IBM4XX) || defined(PPC_BOOKE) 106 #define BUS_DMA_DONTCACHE (BUS_DMA_COHERENT|BUS_DMA_NOCACHE) 107 #endif 108 #endif 109 110 /* 111 * Bus access types. 112 */ 113 typedef uintptr_t bus_addr_t; 114 typedef uintptr_t bus_size_t; 115 116 #define PRIxBUSADDR PRIxPTR 117 #define PRIxBUSSIZE PRIxPTR 118 #define PRIuBUSSIZE PRIuPTR 119 120 #ifndef __HAVE_LOCAL_BUS_SPACE 121 typedef uintptr_t bus_space_handle_t; 122 123 #define PRIxBSH PRIxPTR 124 125 typedef const struct powerpc_bus_space *bus_space_tag_t; 126 127 struct extent; 128 129 struct powerpc_bus_space_scalar { 130 uint8_t (*pbss_read_1)(bus_space_tag_t, bus_space_handle_t, 131 bus_size_t); 132 uint16_t (*pbss_read_2)(bus_space_tag_t, bus_space_handle_t, 133 bus_size_t); 134 uint32_t (*pbss_read_4)(bus_space_tag_t, bus_space_handle_t, 135 bus_size_t); 136 uint64_t (*pbss_read_8)(bus_space_tag_t, bus_space_handle_t, 137 bus_size_t); 138 139 void (*pbss_write_1)(bus_space_tag_t, bus_space_handle_t, bus_size_t, 140 uint8_t); 141 void (*pbss_write_2)(bus_space_tag_t, bus_space_handle_t, bus_size_t, 142 uint16_t); 143 void (*pbss_write_4)(bus_space_tag_t, bus_space_handle_t, bus_size_t, 144 uint32_t); 145 void (*pbss_write_8)(bus_space_tag_t, bus_space_handle_t, bus_size_t, 146 uint64_t); 147 }; 148 149 struct powerpc_bus_space_group { 150 void (*pbsg_read_1)(bus_space_tag_t, bus_space_handle_t, 151 bus_size_t, uint8_t *, size_t); 152 void (*pbsg_read_2)(bus_space_tag_t, bus_space_handle_t, 153 bus_size_t, uint16_t *, size_t); 154 void (*pbsg_read_4)(bus_space_tag_t, bus_space_handle_t, 155 bus_size_t, uint32_t *, size_t); 156 void (*pbsg_read_8)(bus_space_tag_t, bus_space_handle_t, 157 bus_size_t, uint64_t *, size_t); 158 159 void (*pbsg_write_1)(bus_space_tag_t, bus_space_handle_t, 160 bus_size_t, const uint8_t *, size_t); 161 void (*pbsg_write_2)(bus_space_tag_t, bus_space_handle_t, 162 bus_size_t, const uint16_t *, size_t); 163 void (*pbsg_write_4)(bus_space_tag_t, bus_space_handle_t, 164 bus_size_t, const uint32_t *, size_t); 165 void (*pbsg_write_8)(bus_space_tag_t, bus_space_handle_t, 166 bus_size_t, const uint64_t *, size_t); 167 }; 168 169 struct powerpc_bus_space_set { 170 void (*pbss_set_1)(bus_space_tag_t, bus_space_handle_t, 171 bus_size_t, uint8_t, size_t); 172 void (*pbss_set_2)(bus_space_tag_t, bus_space_handle_t, 173 bus_size_t, uint16_t, size_t); 174 void (*pbss_set_4)(bus_space_tag_t, bus_space_handle_t, 175 bus_size_t, uint32_t, size_t); 176 void (*pbss_set_8)(bus_space_tag_t, bus_space_handle_t, 177 bus_size_t, uint64_t, size_t); 178 }; 179 180 struct powerpc_bus_space_copy { 181 void (*pbsc_copy_1)(bus_space_tag_t, bus_space_handle_t, 182 bus_size_t, bus_space_handle_t, bus_size_t, size_t); 183 void (*pbsc_copy_2)(bus_space_tag_t, bus_space_handle_t, 184 bus_size_t, bus_space_handle_t, bus_size_t, size_t); 185 void (*pbsc_copy_4)(bus_space_tag_t, bus_space_handle_t, 186 bus_size_t, bus_space_handle_t, bus_size_t, size_t); 187 void (*pbsc_copy_8)(bus_space_tag_t, bus_space_handle_t, 188 bus_size_t, bus_space_handle_t, bus_size_t, size_t); 189 }; 190 191 struct powerpc_bus_space { 192 int pbs_flags; 193 #define _BUS_SPACE_BIG_ENDIAN 0x00000100 194 #define _BUS_SPACE_LITTLE_ENDIAN 0x00000000 195 #define _BUS_SPACE_IO_TYPE 0x00000200 196 #define _BUS_SPACE_MEM_TYPE 0x00000000 197 #define _BUS_SPACE_STRIDE_MASK 0x0000001f 198 bus_addr_t pbs_offset; /* offset to real start */ 199 bus_addr_t pbs_base; /* extent base */ 200 bus_addr_t pbs_limit; /* extent limit */ 201 struct extent *pbs_extent; 202 203 paddr_t (*pbs_mmap)(bus_space_tag_t, bus_addr_t, off_t, int, int); 204 int (*pbs_map)(bus_space_tag_t, bus_addr_t, bus_size_t, int, 205 bus_space_handle_t *); 206 void (*pbs_unmap)(bus_space_tag_t, bus_space_handle_t, bus_size_t); 207 int (*pbs_alloc)(bus_space_tag_t, bus_addr_t, bus_addr_t, bus_size_t, 208 bus_size_t align, bus_size_t, int, bus_addr_t *, 209 bus_space_handle_t *); 210 void (*pbs_free)(bus_space_tag_t, bus_space_handle_t, bus_size_t); 211 int (*pbs_subregion)(bus_space_tag_t, bus_space_handle_t, bus_size_t, 212 bus_size_t, bus_space_handle_t *); 213 214 struct powerpc_bus_space_scalar pbs_scalar; 215 struct powerpc_bus_space_scalar pbs_scalar_stream; 216 const struct powerpc_bus_space_group *pbs_multi; 217 const struct powerpc_bus_space_group *pbs_multi_stream; 218 const struct powerpc_bus_space_group *pbs_region; 219 const struct powerpc_bus_space_group *pbs_region_stream; 220 const struct powerpc_bus_space_set *pbs_set; 221 const struct powerpc_bus_space_set *pbs_set_stream; 222 const struct powerpc_bus_space_copy *pbs_copy; 223 224 void (*pbs_barrier)(bus_space_tag_t, bus_space_handle_t, bus_size_t, 225 bus_size_t, int); 226 }; 227 228 #define _BUS_SPACE_STRIDE(t, o) \ 229 ((o) << ((t)->pbs_flags & _BUS_SPACE_STRIDE_MASK)) 230 #define _BUS_SPACE_UNSTRIDE(t, o) \ 231 ((o) >> ((t)->pbs_flags & _BUS_SPACE_STRIDE_MASK)) 232 233 #define BUS_SPACE_MAP_CACHEABLE 0x01 234 #define BUS_SPACE_MAP_LINEAR 0x02 235 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 236 237 int bus_space_init(struct powerpc_bus_space *, const char *, void *, size_t); 238 void bus_space_mallocok(void); 239 240 /* 241 * Access methods for bus resources 242 */ 243 244 #define __BUS_SPACE_HAS_STREAM_METHODS 245 246 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 247 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 248 249 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 250 251 #endif /* !__HAVE_LOCAL_BUS_SPACE */ 252 253 /* 254 * Bus DMA methods. 255 */ 256 257 /* 258 * Flags used in various bus DMA methods. 259 */ 260 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 261 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 262 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 263 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 264 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 265 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 266 #define BUS_DMA_BUS2 0x020 267 #define BUS_DMA_BUS3 0x040 268 #define BUS_DMA_BUS4 0x080 269 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 270 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 271 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 272 273 #ifndef BUS_DMA_DONTCACHE 274 #define BUS_DMA_DONTCACHE BUS_DMA_NOCACHE 275 #endif 276 277 /* Forwards needed by prototypes below. */ 278 struct proc; 279 struct mbuf; 280 struct uio; 281 282 /* 283 * Operations performed by bus_dmamap_sync(). 284 */ 285 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 286 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 287 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 288 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 289 290 typedef struct powerpc_bus_dma_tag *bus_dma_tag_t; 291 typedef struct powerpc_bus_dmamap *bus_dmamap_t; 292 293 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 294 295 /* 296 * bus_dma_segment_t 297 * 298 * Describes a single contiguous DMA transaction. Values 299 * are suitable for programming into DMA registers. 300 */ 301 struct powerpc_bus_dma_segment { 302 bus_addr_t ds_addr; /* DMA address */ 303 bus_size_t ds_len; /* length of transfer */ 304 }; 305 typedef struct powerpc_bus_dma_segment bus_dma_segment_t; 306 307 /* 308 * bus_dma_tag_t 309 * 310 * A machine-dependent opaque type describing the implementation of 311 * DMA for a given bus. 312 */ 313 314 struct powerpc_bus_dma_tag { 315 /* 316 * The `bounce threshold' is checked while we are loading 317 * the DMA map. If the physical address of the segment 318 * exceeds the threshold, an error will be returned. The 319 * caller can then take whatever action is necessary to 320 * bounce the transfer. If this value is 0, it will be 321 * ignored. 322 */ 323 bus_addr_t _bounce_thresh; 324 325 /* 326 * DMA mapping methods. 327 */ 328 int (*_dmamap_create) (bus_dma_tag_t, bus_size_t, int, 329 bus_size_t, bus_size_t, int, bus_dmamap_t *); 330 void (*_dmamap_destroy) (bus_dma_tag_t, bus_dmamap_t); 331 int (*_dmamap_load) (bus_dma_tag_t, bus_dmamap_t, void *, 332 bus_size_t, struct proc *, int); 333 int (*_dmamap_load_mbuf) (bus_dma_tag_t, bus_dmamap_t, 334 struct mbuf *, int); 335 int (*_dmamap_load_uio) (bus_dma_tag_t, bus_dmamap_t, 336 struct uio *, int); 337 int (*_dmamap_load_raw) (bus_dma_tag_t, bus_dmamap_t, 338 bus_dma_segment_t *, int, bus_size_t, int); 339 void (*_dmamap_unload) (bus_dma_tag_t, bus_dmamap_t); 340 void (*_dmamap_sync) (bus_dma_tag_t, bus_dmamap_t, 341 bus_addr_t, bus_size_t, int); 342 343 /* 344 * DMA memory utility functions. 345 */ 346 int (*_dmamem_alloc) (bus_dma_tag_t, bus_size_t, bus_size_t, 347 bus_size_t, bus_dma_segment_t *, int, int *, int); 348 void (*_dmamem_free) (bus_dma_tag_t, 349 bus_dma_segment_t *, int); 350 int (*_dmamem_map) (bus_dma_tag_t, bus_dma_segment_t *, 351 int, size_t, void **, int); 352 void (*_dmamem_unmap) (bus_dma_tag_t, void *, size_t); 353 paddr_t (*_dmamem_mmap) (bus_dma_tag_t, bus_dma_segment_t *, 354 int, off_t, int, int); 355 356 #ifndef PHYS_TO_BUS_MEM 357 bus_addr_t (*_dma_phys_to_bus_mem)(bus_dma_tag_t, bus_addr_t); 358 #define PHYS_TO_BUS_MEM(t, addr) (*(t)->_dma_phys_to_bus_mem)((t), (addr)) 359 #endif 360 #ifndef BUS_MEM_TO_PHYS 361 bus_addr_t (*_dma_bus_mem_to_phys)(bus_dma_tag_t, bus_addr_t); 362 #define BUS_MEM_TO_PHYS(t, addr) (*(t)->_dma_bus_mem_to_phys)((t), (addr)) 363 #endif 364 }; 365 366 /* 367 * bus_dmamap_t 368 * 369 * Describes a DMA mapping. 370 */ 371 struct powerpc_bus_dmamap { 372 /* 373 * PRIVATE MEMBERS: not for use my machine-independent code. 374 */ 375 bus_size_t _dm_size; /* largest DMA transfer mappable */ 376 int _dm_segcnt; /* number of segs this map can map */ 377 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 378 bus_size_t _dm_boundary; /* don't cross this */ 379 bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */ 380 int _dm_flags; /* misc. flags */ 381 382 void *_dm_cookie; /* cookie for bus-specific functions */ 383 384 /* 385 * PUBLIC MEMBERS: these are used by machine-independent code. 386 */ 387 bus_size_t dm_maxsegsz; /* largest possible segment */ 388 bus_size_t dm_mapsize; /* size of the mapping */ 389 int dm_nsegs; /* # valid segments in mapping */ 390 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 391 }; 392 393 #endif /* _POWERPC_BUS_DEFS_H_ */ 394
Indexes created Sat Sep 20 22:09:52 GMT 2025