| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr.c | 138 struct pp_smu_funcs_rv *pp_smu = NULL; local in function:rv1_update_clocks
145 ASSERT(clk_mgr->pp_smu);
150 pp_smu = &clk_mgr->pp_smu->rv_funcs;
163 if (pp_smu->set_display_count)
164 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
204 if (pp_smu->set_hard_min_fclk_by_freq &&
205 pp_smu->set_hard_min_dcfclk_by_freq &
237 struct pp_smu_funcs_rv *pp_smu = NULL; local in function:rv1_enable_pme_wa
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 158 struct pp_smu_funcs_nv *pp_smu = NULL; local in function:dcn2_update_clocks
180 if (dc->res_pool->pp_smu)
181 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
187 if (pp_smu && pp_smu->set_display_count)
188 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
193 if (pp_smu && pp_smu->set_voltage_by_freq
345 struct pp_smu_funcs_nv *pp_smu = NULL; local in function:dcn2_enable_pme_wa
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 475 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; local in function:rn_notify_wm_ranges
481 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
482 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
702 struct pp_smu_funcs *pp_smu,
711 clk_mgr->pp_smu = pp_smu;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_pp_smu.h | 50 struct pp_smu { struct
99 struct pp_smu pp_smu; member in struct:pp_smu_funcs_rv
105 void (*set_display_count)(struct pp_smu *pp, int count);
114 void (*set_wm_ranges)(struct pp_smu *pp,
120 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
126 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
131 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
136 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
139 void (*set_pme_wa_enable)(struct pp_smu *pp)
170 struct pp_smu pp_smu; member in struct:pp_smu_funcs_nv
267 struct pp_smu pp_smu; member in struct:pp_smu_funcs_rn
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr_internal.h | 200 struct pp_smu_funcs *pp_smu; member in struct:clk_mgr_internal
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_resource.c | 920 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); local in function:dcn10_pp_smu_create
922 if (!pp_smu)
923 return pp_smu;
925 dm_pp_get_funcs(ctx, pp_smu);
926 return pp_smu;
1011 kfree(pool->base.pp_smu);
1464 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1470 if (pool->base.pp_smu != NULL
1471 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 670 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
973 if (pool->base.pp_smu != NULL)
974 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1390 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1396 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1405 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); local in function:dcn21_pp_smu_create
1407 if (!pp_smu)
1408 return pp_smu;
1411 pp_smu->ctx.ver = PP_SMU_VER_RN
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 171 struct pp_smu_funcs *pp_smu; member in struct:resource_pool
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 1283 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1418 if (pool->base.pp_smu != NULL)
1419 dcn20_pp_smu_destroy(&pool->base.pp_smu);
3119 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); local in function:dcn20_pp_smu_create
3121 if (!pp_smu)
3122 return pp_smu;
3124 dm_pp_get_funcs(ctx, pp_smu);
3126 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3127 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs))
[all...] |
