| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_prediv.c | 43 struct sunxi_ccu_prediv *prediv = &clk->u.prediv; local in function:sunxi_ccu_prediv_get_rate
59 val = CCU_READ(sc, prediv->reg);
60 if (prediv->prediv)
61 pre = __SHIFTOUT(val, prediv->prediv);
64 if (prediv->div)
65 div = __SHIFTOUT(val, prediv->div);
68 sel = __SHIFTOUT(val, prediv->sel)
100 struct sunxi_ccu_prediv *prediv = &clk->u.prediv; local in function:sunxi_ccu_prediv_set_parent
129 struct sunxi_ccu_prediv *prediv = &clk->u.prediv; local in function:sunxi_ccu_prediv_get_parent
[all...] |
| sunxi_hdmiphy.c | 309 u_int init_index, b_out, prediv; local in function:sun8i_h3_hdmiphy_config
329 prediv = val & PLL_CFG2_PREDIV;
333 PHY_WRITE(sc, PLL_CFG2, (inittab->pll_cfg2 & ~PLL_CFG2_PREDIV) | prediv);
369 u_int prediv, best_prediv, best_rate; local in function:sunxi_hdmiphy_set_rate
378 for (prediv = 0; prediv <= __SHIFTOUT_MASK(PLL_CFG2_PREDIV); prediv++) {
379 const u_int tmp_rate = parent_rate / (prediv + 1);
383 best_prediv = prediv;
|
| sunxi_ccu.h | 268 uint32_t prediv; member in struct:sunxi_ccu_prediv
298 .u.prediv.reg = (_reg), \
299 .u.prediv.parents = (_parents), \
300 .u.prediv.nparents = __arraycount(_parents), \
301 .u.prediv.prediv = (_prediv), \
302 .u.prediv.prediv_sel = (_prediv_sel), \
303 .u.prediv.prediv_fixed = (_prediv_fixed), \
304 .u.prediv.div = (_div), \
305 .u.prediv.sel = (_sel),
372 uint32_t prediv; member in struct:sunxi_ccu_fractional
453 struct sunxi_ccu_prediv prediv; member in union:sunxi_ccu_clk::__anonaec1cae4010a
[all...] |
| /src/sys/arch/arm/nxp/ |
| imx_ccm_composite.c | 132 for (u_int prediv = 1; prediv <= __SHIFTOUT_MASK(TARGET_ROOT_PRE_PODF) + 1; prediv++) { local in function:imx_ccm_composite_set_rate
134 const u_int cur_rate = prate / prediv / postdiv;
139 best_prediv = prediv;
145 best_prediv = prediv;
|
