1 /* $NetBSD: amdgpu_display_rq_dlg_helpers.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_display_rq_dlg_helpers.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $"); 30 31 #include "display_rq_dlg_helpers.h" 32 #include "dml_logger.h" 33 34 void print__rq_params_st(struct display_mode_lib *mode_lib, display_rq_params_st rq_param) 35 { 36 dml_print("DML_RQ_DLG_CALC: ***************************\n"); 37 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST\n"); 38 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 39 print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_l); 40 dml_print("DML_RQ_DLG_CALC: <CHROMA> ===\n"); 41 print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_c); 42 43 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 44 print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_l); 45 dml_print("DML_RQ_DLG_CALC: <CHROMA>\n"); 46 print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_c); 47 48 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 49 print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_l); 50 dml_print("DML_RQ_DLG_CALC: <CHROMA>\n"); 51 print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_c); 52 dml_print("DML_RQ_DLG_CALC: ***************************\n"); 53 } 54 55 void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, display_data_rq_sizing_params_st rq_sizing) 56 { 57 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 58 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n"); 59 dml_print("DML_RQ_DLG_CALC: chunk_bytes = %0d\n", rq_sizing.chunk_bytes); 60 dml_print("DML_RQ_DLG_CALC: min_chunk_bytes = %0d\n", rq_sizing.min_chunk_bytes); 61 dml_print("DML_RQ_DLG_CALC: meta_chunk_bytes = %0d\n", rq_sizing.meta_chunk_bytes); 62 dml_print( 63 "DML_RQ_DLG_CALC: min_meta_chunk_bytes = %0d\n", 64 rq_sizing.min_meta_chunk_bytes); 65 dml_print("DML_RQ_DLG_CALC: mpte_group_bytes = %0d\n", rq_sizing.mpte_group_bytes); 66 dml_print("DML_RQ_DLG_CALC: dpte_group_bytes = %0d\n", rq_sizing.dpte_group_bytes); 67 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 68 } 69 70 void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param) 71 { 72 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 73 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n"); 74 dml_print( 75 "DML_RQ_DLG_CALC: swath_width_ub = %0d\n", 76 rq_dlg_param.swath_width_ub); 77 dml_print( 78 "DML_RQ_DLG_CALC: swath_height = %0d\n", 79 rq_dlg_param.swath_height); 80 dml_print( 81 "DML_RQ_DLG_CALC: req_per_swath_ub = %0d\n", 82 rq_dlg_param.req_per_swath_ub); 83 dml_print( 84 "DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = %0d\n", 85 rq_dlg_param.meta_pte_bytes_per_frame_ub); 86 dml_print( 87 "DML_RQ_DLG_CALC: dpte_req_per_row_ub = %0d\n", 88 rq_dlg_param.dpte_req_per_row_ub); 89 dml_print( 90 "DML_RQ_DLG_CALC: dpte_groups_per_row_ub = %0d\n", 91 rq_dlg_param.dpte_groups_per_row_ub); 92 dml_print( 93 "DML_RQ_DLG_CALC: dpte_row_height = %0d\n", 94 rq_dlg_param.dpte_row_height); 95 dml_print( 96 "DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = %0d\n", 97 rq_dlg_param.dpte_bytes_per_row_ub); 98 dml_print( 99 "DML_RQ_DLG_CALC: meta_chunks_per_row_ub = %0d\n", 100 rq_dlg_param.meta_chunks_per_row_ub); 101 dml_print( 102 "DML_RQ_DLG_CALC: meta_req_per_row_ub = %0d\n", 103 rq_dlg_param.meta_req_per_row_ub); 104 dml_print( 105 "DML_RQ_DLG_CALC: meta_row_height = %0d\n", 106 rq_dlg_param.meta_row_height); 107 dml_print( 108 "DML_RQ_DLG_CALC: meta_bytes_per_row_ub = %0d\n", 109 rq_dlg_param.meta_bytes_per_row_ub); 110 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 111 } 112 113 void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, display_data_rq_misc_params_st rq_misc_param) 114 { 115 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 116 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n"); 117 dml_print( 118 "DML_RQ_DLG_CALC: full_swath_bytes = %0d\n", 119 rq_misc_param.full_swath_bytes); 120 dml_print( 121 "DML_RQ_DLG_CALC: stored_swath_bytes = %0d\n", 122 rq_misc_param.stored_swath_bytes); 123 dml_print("DML_RQ_DLG_CALC: blk256_width = %0d\n", rq_misc_param.blk256_width); 124 dml_print("DML_RQ_DLG_CALC: blk256_height = %0d\n", rq_misc_param.blk256_height); 125 dml_print("DML_RQ_DLG_CALC: req_width = %0d\n", rq_misc_param.req_width); 126 dml_print("DML_RQ_DLG_CALC: req_height = %0d\n", rq_misc_param.req_height); 127 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 128 } 129 130 void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param) 131 { 132 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 133 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n"); 134 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 135 print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_l); 136 dml_print("DML_RQ_DLG_CALC: <CHROMA>\n"); 137 print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_c); 138 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 139 } 140 141 void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param) 142 { 143 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 144 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n"); 145 dml_print("DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f\n", dlg_sys_param.t_mclk_wm_us); 146 dml_print("DML_RQ_DLG_CALC: t_urg_wm_us = %3.2f\n", dlg_sys_param.t_urg_wm_us); 147 dml_print("DML_RQ_DLG_CALC: t_sr_wm_us = %3.2f\n", dlg_sys_param.t_sr_wm_us); 148 dml_print("DML_RQ_DLG_CALC: t_extra_us = %3.2f\n", dlg_sys_param.t_extra_us); 149 dml_print( 150 "DML_RQ_DLG_CALC: t_srx_delay_us = %3.2f\n", 151 dlg_sys_param.t_srx_delay_us); 152 dml_print( 153 "DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = %3.2f\n", 154 dlg_sys_param.deepsleep_dcfclk_mhz); 155 dml_print( 156 "DML_RQ_DLG_CALC: total_flip_bw = %3.2f\n", 157 dlg_sys_param.total_flip_bw); 158 dml_print( 159 "DML_RQ_DLG_CALC: total_flip_bytes = %i\n", 160 dlg_sys_param.total_flip_bytes); 161 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 162 } 163 164 void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st rq_regs) 165 { 166 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 167 dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n"); 168 dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs.chunk_size); 169 dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs.min_chunk_size); 170 dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs.meta_chunk_size); 171 dml_print( 172 "DML_RQ_DLG_CALC: min_meta_chunk_size = 0x%0x\n", 173 rq_regs.min_meta_chunk_size); 174 dml_print("DML_RQ_DLG_CALC: dpte_group_size = 0x%0x\n", rq_regs.dpte_group_size); 175 dml_print("DML_RQ_DLG_CALC: mpte_group_size = 0x%0x\n", rq_regs.mpte_group_size); 176 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs.swath_height); 177 dml_print( 178 "DML_RQ_DLG_CALC: pte_row_height_linear = 0x%0x\n", 179 rq_regs.pte_row_height_linear); 180 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 181 } 182 183 void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs) 184 { 185 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 186 dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST\n"); 187 dml_print("DML_RQ_DLG_CALC: <LUMA>\n"); 188 print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l); 189 dml_print("DML_RQ_DLG_CALC: <CHROMA>\n"); 190 print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_c); 191 dml_print("DML_RQ_DLG_CALC: drq_expansion_mode = 0x%0x\n", rq_regs.drq_expansion_mode); 192 dml_print("DML_RQ_DLG_CALC: prq_expansion_mode = 0x%0x\n", rq_regs.prq_expansion_mode); 193 dml_print("DML_RQ_DLG_CALC: mrq_expansion_mode = 0x%0x\n", rq_regs.mrq_expansion_mode); 194 dml_print("DML_RQ_DLG_CALC: crq_expansion_mode = 0x%0x\n", rq_regs.crq_expansion_mode); 195 dml_print("DML_RQ_DLG_CALC: plane1_base_address = 0x%0x\n", rq_regs.plane1_base_address); 196 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 197 } 198 199 void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs) 200 { 201 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 202 dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n"); 203 dml_print( 204 "DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x%0x\n", 205 dlg_regs.refcyc_h_blank_end); 206 dml_print( 207 "DML_RQ_DLG_CALC: dlg_vblank_end = 0x%0x\n", 208 dlg_regs.dlg_vblank_end); 209 dml_print( 210 "DML_RQ_DLG_CALC: min_dst_y_next_start = 0x%0x\n", 211 dlg_regs.min_dst_y_next_start); 212 dml_print( 213 "DML_RQ_DLG_CALC: refcyc_per_htotal = 0x%0x\n", 214 dlg_regs.refcyc_per_htotal); 215 dml_print( 216 "DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x%0x\n", 217 dlg_regs.refcyc_x_after_scaler); 218 dml_print( 219 "DML_RQ_DLG_CALC: dst_y_after_scaler = 0x%0x\n", 220 dlg_regs.dst_y_after_scaler); 221 dml_print( 222 "DML_RQ_DLG_CALC: dst_y_prefetch = 0x%0x\n", 223 dlg_regs.dst_y_prefetch); 224 dml_print( 225 "DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x%0x\n", 226 dlg_regs.dst_y_per_vm_vblank); 227 dml_print( 228 "DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x%0x\n", 229 dlg_regs.dst_y_per_row_vblank); 230 dml_print( 231 "DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x%0x\n", 232 dlg_regs.dst_y_per_vm_flip); 233 dml_print( 234 "DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x%0x\n", 235 dlg_regs.dst_y_per_row_flip); 236 dml_print( 237 "DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x%0x\n", 238 dlg_regs.ref_freq_to_pix_freq); 239 dml_print( 240 "DML_RQ_DLG_CALC: vratio_prefetch = 0x%0x\n", 241 dlg_regs.vratio_prefetch); 242 dml_print( 243 "DML_RQ_DLG_CALC: vratio_prefetch_c = 0x%0x\n", 244 dlg_regs.vratio_prefetch_c); 245 dml_print( 246 "DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x%0x\n", 247 dlg_regs.refcyc_per_pte_group_vblank_l); 248 dml_print( 249 "DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x%0x\n", 250 dlg_regs.refcyc_per_pte_group_vblank_c); 251 dml_print( 252 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x%0x\n", 253 dlg_regs.refcyc_per_meta_chunk_vblank_l); 254 dml_print( 255 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x%0x\n", 256 dlg_regs.refcyc_per_meta_chunk_vblank_c); 257 dml_print( 258 "DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x%0x\n", 259 dlg_regs.refcyc_per_pte_group_flip_l); 260 dml_print( 261 "DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x%0x\n", 262 dlg_regs.refcyc_per_pte_group_flip_c); 263 dml_print( 264 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x%0x\n", 265 dlg_regs.refcyc_per_meta_chunk_flip_l); 266 dml_print( 267 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x%0x\n", 268 dlg_regs.refcyc_per_meta_chunk_flip_c); 269 dml_print( 270 "DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x%0x\n", 271 dlg_regs.dst_y_per_pte_row_nom_l); 272 dml_print( 273 "DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x%0x\n", 274 dlg_regs.dst_y_per_pte_row_nom_c); 275 dml_print( 276 "DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x%0x\n", 277 dlg_regs.refcyc_per_pte_group_nom_l); 278 dml_print( 279 "DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x%0x\n", 280 dlg_regs.refcyc_per_pte_group_nom_c); 281 dml_print( 282 "DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x%0x\n", 283 dlg_regs.dst_y_per_meta_row_nom_l); 284 dml_print( 285 "DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x%0x\n", 286 dlg_regs.dst_y_per_meta_row_nom_c); 287 dml_print( 288 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x%0x\n", 289 dlg_regs.refcyc_per_meta_chunk_nom_l); 290 dml_print( 291 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x%0x\n", 292 dlg_regs.refcyc_per_meta_chunk_nom_c); 293 dml_print( 294 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x%0x\n", 295 dlg_regs.refcyc_per_line_delivery_pre_l); 296 dml_print( 297 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x%0x\n", 298 dlg_regs.refcyc_per_line_delivery_pre_c); 299 dml_print( 300 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x%0x\n", 301 dlg_regs.refcyc_per_line_delivery_l); 302 dml_print( 303 "DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x%0x\n", 304 dlg_regs.refcyc_per_line_delivery_c); 305 dml_print( 306 "DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x%0x\n", 307 dlg_regs.chunk_hdl_adjust_cur0); 308 dml_print( 309 "DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x%0x\n", 310 dlg_regs.dst_y_offset_cur1); 311 dml_print( 312 "DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x%0x\n", 313 dlg_regs.chunk_hdl_adjust_cur1); 314 dml_print( 315 "DML_RQ_DLG_CALC: vready_after_vcount0 = 0x%0x\n", 316 dlg_regs.vready_after_vcount0); 317 dml_print( 318 "DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x%0x\n", 319 dlg_regs.dst_y_delta_drq_limit); 320 dml_print( 321 "DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x%0x\n", 322 dlg_regs.xfc_reg_transfer_delay); 323 dml_print( 324 "DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x%0x\n", 325 dlg_regs.xfc_reg_precharge_delay); 326 dml_print( 327 "DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x%0x\n", 328 dlg_regs.xfc_reg_remote_surface_flip_latency); 329 dml_print( 330 "DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x%0x\n", 331 dlg_regs.refcyc_per_vm_dmdata); 332 333 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 334 } 335 336 void print__ttu_regs_st(struct display_mode_lib *mode_lib, display_ttu_regs_st ttu_regs) 337 { 338 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 339 dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n"); 340 dml_print( 341 "DML_RQ_DLG_CALC: qos_level_low_wm = 0x%0x\n", 342 ttu_regs.qos_level_low_wm); 343 dml_print( 344 "DML_RQ_DLG_CALC: qos_level_high_wm = 0x%0x\n", 345 ttu_regs.qos_level_high_wm); 346 dml_print( 347 "DML_RQ_DLG_CALC: min_ttu_vblank = 0x%0x\n", 348 ttu_regs.min_ttu_vblank); 349 dml_print( 350 "DML_RQ_DLG_CALC: qos_level_flip = 0x%0x\n", 351 ttu_regs.qos_level_flip); 352 dml_print( 353 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x%0x\n", 354 ttu_regs.refcyc_per_req_delivery_pre_l); 355 dml_print( 356 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x%0x\n", 357 ttu_regs.refcyc_per_req_delivery_l); 358 dml_print( 359 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x%0x\n", 360 ttu_regs.refcyc_per_req_delivery_pre_c); 361 dml_print( 362 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x%0x\n", 363 ttu_regs.refcyc_per_req_delivery_c); 364 dml_print( 365 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x%0x\n", 366 ttu_regs.refcyc_per_req_delivery_cur0); 367 dml_print( 368 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x%0x\n", 369 ttu_regs.refcyc_per_req_delivery_pre_cur0); 370 dml_print( 371 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x%0x\n", 372 ttu_regs.refcyc_per_req_delivery_cur1); 373 dml_print( 374 "DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x%0x\n", 375 ttu_regs.refcyc_per_req_delivery_pre_cur1); 376 dml_print( 377 "DML_RQ_DLG_CALC: qos_level_fixed_l = 0x%0x\n", 378 ttu_regs.qos_level_fixed_l); 379 dml_print( 380 "DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x%0x\n", 381 ttu_regs.qos_ramp_disable_l); 382 dml_print( 383 "DML_RQ_DLG_CALC: qos_level_fixed_c = 0x%0x\n", 384 ttu_regs.qos_level_fixed_c); 385 dml_print( 386 "DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x%0x\n", 387 ttu_regs.qos_ramp_disable_c); 388 dml_print( 389 "DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x%0x\n", 390 ttu_regs.qos_level_fixed_cur0); 391 dml_print( 392 "DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x%0x\n", 393 ttu_regs.qos_ramp_disable_cur0); 394 dml_print( 395 "DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x%0x\n", 396 ttu_regs.qos_level_fixed_cur1); 397 dml_print( 398 "DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x%0x\n", 399 ttu_regs.qos_ramp_disable_cur1); 400 dml_print("DML_RQ_DLG_CALC: =====================================\n"); 401 } 402
Indexes created Sat Sep 27 14:09:57 GMT 2025