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      1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
      2 //
      3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
      4 // See https://llvm.org/LICENSE.txt for license information.
      5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
      6 //
      7 //===----------------------------------------------------------------------===//
      8 //
      9 // This file contains the Hexagon implementation of the TargetRegisterInfo
     10 // class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
     15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
     16 
     17 #include "llvm/CodeGen/TargetRegisterInfo.h"
     18 
     19 #define GET_REGINFO_HEADER
     20 #include "HexagonGenRegisterInfo.inc"
     21 
     22 namespace llvm {
     23 
     24 namespace Hexagon {
     25   // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
     26   enum { ps_sub_lo = 0, ps_sub_hi = 1 };
     27 }
     28 
     29 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
     30 public:
     31   HexagonRegisterInfo(unsigned HwMode);
     32 
     33   /// Code Generation virtual methods...
     34   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
     35         const override;
     36   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
     37         CallingConv::ID) const override;
     38 
     39   BitVector getReservedRegs(const MachineFunction &MF) const override;
     40 
     41   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
     42         unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
     43 
     44   /// Returns true since we may need scavenging for a temporary register
     45   /// when generating hardware loop instructions.
     46   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     47     return true;
     48   }
     49 
     50   /// Returns true. Spill code for predicate registers might need an extra
     51   /// register.
     52   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     53     return true;
     54   }
     55 
     56   /// Returns true if the frame pointer is valid.
     57   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
     58 
     59   bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
     60         unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
     61         const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
     62 
     63   // Debug information queries.
     64   unsigned getRARegister() const;
     65   Register getFrameRegister(const MachineFunction &MF) const override;
     66   unsigned getFrameRegister() const;
     67   unsigned getStackRegister() const;
     68 
     69   unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
     70         unsigned GenIdx) const;
     71 
     72   const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
     73         const TargetRegisterClass *RC) const;
     74 
     75   unsigned getFirstCallerSavedNonParamReg() const;
     76 
     77   const TargetRegisterClass *
     78   getPointerRegClass(const MachineFunction &MF,
     79                      unsigned Kind = 0) const override;
     80 
     81   bool isEHReturnCalleeSaveReg(unsigned Reg) const;
     82 };
     83 
     84 } // end namespace llvm
     85 
     86 #endif
     87