1 /* $NetBSD: amdgpu_psp_v3_1.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Author: Huang Rui 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_psp_v3_1.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $"); 30 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <linux/pci.h> 34 35 #include "amdgpu.h" 36 #include "amdgpu_psp.h" 37 #include "amdgpu_ucode.h" 38 #include "soc15_common.h" 39 #include "psp_v3_1.h" 40 41 #include "mp/mp_9_0_offset.h" 42 #include "mp/mp_9_0_sh_mask.h" 43 #include "gc/gc_9_0_offset.h" 44 #include "sdma0/sdma0_4_0_offset.h" 45 #include "nbio/nbio_6_1_offset.h" 46 47 #include "oss/osssys_4_0_offset.h" 48 #include "oss/osssys_4_0_sh_mask.h" 49 50 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 54 55 56 #define smnMP1_FIRMWARE_FLAGS 0x3010028 57 58 static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; 59 60 static bool psp_v3_1_support_vmr_ring(struct psp_context *psp); 61 static int psp_v3_1_ring_stop(struct psp_context *psp, 62 enum psp_ring_type ring_type); 63 64 static int psp_v3_1_init_microcode(struct psp_context *psp) 65 { 66 struct amdgpu_device *adev = psp->adev; 67 const char *chip_name; 68 char fw_name[30]; 69 int err = 0; 70 const struct psp_firmware_header_v1_0 *hdr; 71 72 DRM_DEBUG("\n"); 73 74 switch (adev->asic_type) { 75 case CHIP_VEGA10: 76 chip_name = "vega10"; 77 break; 78 case CHIP_VEGA12: 79 chip_name = "vega12"; 80 break; 81 default: BUG(); 82 } 83 84 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 85 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 86 if (err) 87 goto out; 88 89 err = amdgpu_ucode_validate(adev->psp.sos_fw); 90 if (err) 91 goto out; 92 93 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 94 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 95 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 96 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 97 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 98 le32_to_cpu(hdr->sos_size_bytes); 99 adev->psp.sys_start_addr = (const uint8_t *)hdr + 100 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 101 adev->psp.sos_start_addr = (const uint8_t *)adev->psp.sys_start_addr + 102 le32_to_cpu(hdr->sos_offset_bytes); 103 104 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 105 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 106 if (err) 107 goto out; 108 109 err = amdgpu_ucode_validate(adev->psp.asd_fw); 110 if (err) 111 goto out; 112 113 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 114 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 115 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 116 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 117 adev->psp.asd_start_addr = (const uint8_t *)hdr + 118 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 119 120 return 0; 121 out: 122 if (err) { 123 dev_err(adev->dev, 124 "psp v3.1: Failed to load firmware \"%s\"\n", 125 fw_name); 126 release_firmware(adev->psp.sos_fw); 127 adev->psp.sos_fw = NULL; 128 release_firmware(adev->psp.asd_fw); 129 adev->psp.asd_fw = NULL; 130 } 131 132 return err; 133 } 134 135 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 136 { 137 int ret; 138 uint32_t psp_gfxdrv_command_reg = 0; 139 struct amdgpu_device *adev = psp->adev; 140 uint32_t sol_reg; 141 142 /* Check sOS sign of life register to confirm sys driver and sOS 143 * are already been loaded. 144 */ 145 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 146 if (sol_reg) 147 return 0; 148 149 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 150 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 151 0x80000000, 0x80000000, false); 152 if (ret) 153 return ret; 154 155 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 156 157 /* Copy PSP System Driver binary to memory */ 158 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 159 160 /* Provide the sys driver to bootloader */ 161 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 162 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 163 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 164 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 165 psp_gfxdrv_command_reg); 166 167 /* there might be handshake issue with hardware which needs delay */ 168 mdelay(20); 169 170 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 171 0x80000000, 0x80000000, false); 172 173 return ret; 174 } 175 176 static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver) 177 { 178 int i; 179 180 if (ver == adev->psp.sos_fw_version) 181 return true; 182 183 /* 184 * Double check if the latest four legacy versions. 185 * If yes, it is still the right version. 186 */ 187 for (i = 0; i < ARRAY_SIZE(sos_old_versions); i++) { 188 if (sos_old_versions[i] == adev->psp.sos_fw_version) 189 return true; 190 } 191 192 return false; 193 } 194 195 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 196 { 197 int ret; 198 unsigned int psp_gfxdrv_command_reg = 0; 199 struct amdgpu_device *adev = psp->adev; 200 uint32_t sol_reg, ver; 201 202 /* Check sOS sign of life register to confirm sys driver and sOS 203 * are already been loaded. 204 */ 205 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 206 if (sol_reg) { 207 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 208 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 209 return 0; 210 } 211 212 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 213 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 214 0x80000000, 0x80000000, false); 215 if (ret) 216 return ret; 217 218 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 219 220 /* Copy Secure OS binary to PSP memory */ 221 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 222 223 /* Provide the PSP secure OS to bootloader */ 224 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 225 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 226 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 227 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 228 psp_gfxdrv_command_reg); 229 230 /* there might be handshake issue with hardware which needs delay */ 231 mdelay(20); 232 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 233 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 234 0, true); 235 236 ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 237 if (!psp_v3_1_match_version(adev, ver)) 238 DRM_WARN("SOS version doesn't match\n"); 239 240 return ret; 241 } 242 243 static int psp_v3_1_ring_init(struct psp_context *psp, 244 enum psp_ring_type ring_type) 245 { 246 int ret = 0; 247 struct psp_ring *ring; 248 struct amdgpu_device *adev = psp->adev; 249 250 ring = &psp->km_ring; 251 252 ring->ring_type = ring_type; 253 254 /* allocate 4k Page of Local Frame Buffer memory for ring */ 255 ring->ring_size = 0x1000; 256 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 257 AMDGPU_GEM_DOMAIN_VRAM, 258 &adev->firmware.rbuf, 259 &ring->ring_mem_mc_addr, 260 (void **)&ring->ring_mem); 261 if (ret) { 262 ring->ring_size = 0; 263 return ret; 264 } 265 266 return 0; 267 } 268 269 static void psp_v3_1_reroute_ih(struct psp_context *psp) 270 { 271 struct amdgpu_device *adev = psp->adev; 272 uint32_t tmp; 273 274 /* Change IH ring for VMC */ 275 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 276 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 277 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 278 279 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 280 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 281 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 282 283 mdelay(20); 284 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 285 0x80000000, 0x8000FFFF, false); 286 287 /* Change IH ring for UMC */ 288 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 289 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 290 291 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 292 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 293 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 294 295 mdelay(20); 296 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 297 0x80000000, 0x8000FFFF, false); 298 } 299 300 static int psp_v3_1_ring_create(struct psp_context *psp, 301 enum psp_ring_type ring_type) 302 { 303 int ret = 0; 304 unsigned int psp_ring_reg = 0; 305 struct psp_ring *ring = &psp->km_ring; 306 struct amdgpu_device *adev = psp->adev; 307 308 psp_v3_1_reroute_ih(psp); 309 310 if (psp_v3_1_support_vmr_ring(psp)) { 311 ret = psp_v3_1_ring_stop(psp, ring_type); 312 if (ret) { 313 DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n"); 314 return ret; 315 } 316 317 /* Write low address of the ring to C2PMSG_102 */ 318 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 319 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 320 /* Write high address of the ring to C2PMSG_103 */ 321 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 322 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 323 /* No size initialization for sriov */ 324 /* Write the ring initialization command to C2PMSG_101 */ 325 psp_ring_reg = ring_type; 326 psp_ring_reg = psp_ring_reg << 16; 327 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); 328 329 /* there might be hardware handshake issue which needs delay */ 330 mdelay(20); 331 332 /* Wait for response flag (bit 31) in C2PMSG_101 */ 333 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 334 mmMP0_SMN_C2PMSG_101), 0x80000000, 335 0x8000FFFF, false); 336 } else { 337 338 /* Write low address of the ring to C2PMSG_69 */ 339 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 340 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 341 /* Write high address of the ring to C2PMSG_70 */ 342 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 343 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 344 /* Write size of ring to C2PMSG_71 */ 345 psp_ring_reg = ring->ring_size; 346 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 347 /* Write the ring initialization command to C2PMSG_64 */ 348 psp_ring_reg = ring_type; 349 psp_ring_reg = psp_ring_reg << 16; 350 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 351 352 /* there might be hardware handshake issue which needs delay */ 353 mdelay(20); 354 355 /* Wait for response flag (bit 31) in C2PMSG_64 */ 356 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 357 mmMP0_SMN_C2PMSG_64), 0x80000000, 358 0x8000FFFF, false); 359 360 } 361 return ret; 362 } 363 364 static int psp_v3_1_ring_stop(struct psp_context *psp, 365 enum psp_ring_type ring_type) 366 { 367 int ret = 0; 368 unsigned int psp_ring_reg = 0; 369 struct amdgpu_device *adev = psp->adev; 370 371 if (psp_v3_1_support_vmr_ring(psp)) { 372 /* Write the Destroy GPCOM ring command to C2PMSG_101 */ 373 psp_ring_reg = GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING; 374 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); 375 376 /* there might be handshake issue which needs delay */ 377 mdelay(20); 378 379 /* Wait for response flag (bit 31) in C2PMSG_101 */ 380 ret = psp_wait_for(psp, 381 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 382 0x80000000, 0x80000000, false); 383 } else { 384 /* Write the ring destroy command to C2PMSG_64 */ 385 psp_ring_reg = 3 << 16; 386 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 387 388 /* there might be handshake issue which needs delay */ 389 mdelay(20); 390 391 /* Wait for response flag (bit 31) in C2PMSG_64 */ 392 ret = psp_wait_for(psp, 393 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 394 0x80000000, 0x80000000, false); 395 } 396 397 return ret; 398 } 399 400 static int psp_v3_1_ring_destroy(struct psp_context *psp, 401 enum psp_ring_type ring_type) 402 { 403 int ret = 0; 404 struct psp_ring *ring = &psp->km_ring; 405 struct amdgpu_device *adev = psp->adev; 406 407 ret = psp_v3_1_ring_stop(psp, ring_type); 408 if (ret) 409 DRM_ERROR("Fail to stop psp ring\n"); 410 411 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 412 &ring->ring_mem_mc_addr, 413 (void **)&ring->ring_mem); 414 415 return ret; 416 } 417 418 static int 419 psp_v3_1_sram_map(struct amdgpu_device *adev, 420 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 421 unsigned int *sram_data_reg_offset, 422 enum AMDGPU_UCODE_ID ucode_id) 423 { 424 int ret = 0; 425 426 switch(ucode_id) { 427 /* TODO: needs to confirm */ 428 #if 0 429 case AMDGPU_UCODE_ID_SMC: 430 *sram_offset = 0; 431 *sram_addr_reg_offset = 0; 432 *sram_data_reg_offset = 0; 433 break; 434 #endif 435 436 case AMDGPU_UCODE_ID_CP_CE: 437 *sram_offset = 0x0; 438 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 439 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 440 break; 441 442 case AMDGPU_UCODE_ID_CP_PFP: 443 *sram_offset = 0x0; 444 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 445 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 446 break; 447 448 case AMDGPU_UCODE_ID_CP_ME: 449 *sram_offset = 0x0; 450 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 451 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 452 break; 453 454 case AMDGPU_UCODE_ID_CP_MEC1: 455 *sram_offset = 0x10000; 456 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 457 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 458 break; 459 460 case AMDGPU_UCODE_ID_CP_MEC2: 461 *sram_offset = 0x10000; 462 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 463 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 464 break; 465 466 case AMDGPU_UCODE_ID_RLC_G: 467 *sram_offset = 0x2000; 468 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 469 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 470 break; 471 472 case AMDGPU_UCODE_ID_SDMA0: 473 *sram_offset = 0x0; 474 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 475 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 476 break; 477 478 /* TODO: needs to confirm */ 479 #if 0 480 case AMDGPU_UCODE_ID_SDMA1: 481 *sram_offset = ; 482 *sram_addr_reg_offset = ; 483 break; 484 485 case AMDGPU_UCODE_ID_UVD: 486 *sram_offset = ; 487 *sram_addr_reg_offset = ; 488 break; 489 490 case AMDGPU_UCODE_ID_VCE: 491 *sram_offset = ; 492 *sram_addr_reg_offset = ; 493 break; 494 #endif 495 496 case AMDGPU_UCODE_ID_MAXIMUM: 497 default: 498 ret = -EINVAL; 499 break; 500 } 501 502 return ret; 503 } 504 505 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 506 struct amdgpu_firmware_info *ucode, 507 enum AMDGPU_UCODE_ID ucode_type) 508 { 509 int err = 0; 510 unsigned int fw_sram_reg_val = 0; 511 unsigned int fw_sram_addr_reg_offset = 0; 512 unsigned int fw_sram_data_reg_offset = 0; 513 unsigned int ucode_size; 514 uint32_t *ucode_mem = NULL; 515 struct amdgpu_device *adev = psp->adev; 516 517 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 518 &fw_sram_data_reg_offset, ucode_type); 519 if (err) 520 return false; 521 522 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 523 524 ucode_size = ucode->ucode_size; 525 ucode_mem = (uint32_t *)ucode->kaddr; 526 while (ucode_size) { 527 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 528 529 if (*ucode_mem != fw_sram_reg_val) 530 return false; 531 532 ucode_mem++; 533 /* 4 bytes */ 534 ucode_size -= 4; 535 } 536 537 return true; 538 } 539 540 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 541 { 542 struct amdgpu_device *adev = psp->adev; 543 uint32_t reg; 544 545 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); 546 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 547 } 548 549 static int psp_v3_1_mode1_reset(struct psp_context *psp) 550 { 551 int ret; 552 uint32_t offset; 553 struct amdgpu_device *adev = psp->adev; 554 555 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 556 557 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 558 559 if (ret) { 560 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 561 return -EINVAL; 562 } 563 564 /*send the mode 1 reset command*/ 565 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 566 567 msleep(500); 568 569 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 570 571 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 572 573 if (ret) { 574 DRM_INFO("psp mode 1 reset failed!\n"); 575 return -EINVAL; 576 } 577 578 DRM_INFO("psp mode1 reset succeed \n"); 579 580 return 0; 581 } 582 583 static bool psp_v3_1_support_vmr_ring(struct psp_context *psp) 584 { 585 if (amdgpu_sriov_vf(psp->adev)) 586 return true; 587 588 return false; 589 } 590 591 static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp) 592 { 593 uint32_t data; 594 struct amdgpu_device *adev = psp->adev; 595 596 if (psp_v3_1_support_vmr_ring(psp)) 597 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 598 else 599 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 600 return data; 601 } 602 603 static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value) 604 { 605 struct amdgpu_device *adev = psp->adev; 606 607 if (psp_v3_1_support_vmr_ring(psp)) { 608 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 609 /* send interrupt to PSP for SRIOV ring write pointer update */ 610 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 611 GFX_CTRL_CMD_ID_CONSUME_CMD); 612 } else 613 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 614 } 615 616 static const struct psp_funcs psp_v3_1_funcs = { 617 .init_microcode = psp_v3_1_init_microcode, 618 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 619 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 620 .ring_init = psp_v3_1_ring_init, 621 .ring_create = psp_v3_1_ring_create, 622 .ring_stop = psp_v3_1_ring_stop, 623 .ring_destroy = psp_v3_1_ring_destroy, 624 .compare_sram_data = psp_v3_1_compare_sram_data, 625 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 626 .mode1_reset = psp_v3_1_mode1_reset, 627 .support_vmr_ring = psp_v3_1_support_vmr_ring, 628 .ring_get_wptr = psp_v3_1_ring_get_wptr, 629 .ring_set_wptr = psp_v3_1_ring_set_wptr, 630 }; 631 632 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 633 { 634 psp->funcs = &psp_v3_1_funcs; 635 } 636
Indexes created Sun Sep 21 16:09:51 GMT 2025