1 /* $NetBSD: hw_shared.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DAL_HW_SHARED_H__ 29 #define __DAL_HW_SHARED_H__ 30 31 #include "os_types.h" 32 #include "fixed31_32.h" 33 #include "dc_hw_types.h" 34 35 /****************************************************************************** 36 * Data types shared between different Virtual HW blocks 37 ******************************************************************************/ 38 39 #define MAX_AUDIOS 7 40 #define MAX_PIPES 6 41 #define MAX_DWB_PIPES 1 42 43 struct gamma_curve { 44 uint32_t offset; 45 uint32_t segments_num; 46 }; 47 48 struct curve_points { 49 struct fixed31_32 x; 50 struct fixed31_32 y; 51 struct fixed31_32 offset; 52 struct fixed31_32 slope; 53 54 uint32_t custom_float_x; 55 uint32_t custom_float_y; 56 uint32_t custom_float_offset; 57 uint32_t custom_float_slope; 58 }; 59 60 struct curve_points3 { 61 struct curve_points red; 62 struct curve_points green; 63 struct curve_points blue; 64 }; 65 66 struct pwl_result_data { 67 struct fixed31_32 red; 68 struct fixed31_32 green; 69 struct fixed31_32 blue; 70 71 struct fixed31_32 delta_red; 72 struct fixed31_32 delta_green; 73 struct fixed31_32 delta_blue; 74 75 uint32_t red_reg; 76 uint32_t green_reg; 77 uint32_t blue_reg; 78 79 uint32_t delta_red_reg; 80 uint32_t delta_green_reg; 81 uint32_t delta_blue_reg; 82 }; 83 84 struct dc_rgb { 85 uint32_t red; 86 uint32_t green; 87 uint32_t blue; 88 }; 89 90 struct tetrahedral_17x17x17 { 91 struct dc_rgb lut0[1229]; 92 struct dc_rgb lut1[1228]; 93 struct dc_rgb lut2[1228]; 94 struct dc_rgb lut3[1228]; 95 }; 96 struct tetrahedral_9x9x9 { 97 struct dc_rgb lut0[183]; 98 struct dc_rgb lut1[182]; 99 struct dc_rgb lut2[182]; 100 struct dc_rgb lut3[182]; 101 }; 102 103 struct tetrahedral_params { 104 union { 105 struct tetrahedral_17x17x17 tetrahedral_17; 106 struct tetrahedral_9x9x9 tetrahedral_9; 107 }; 108 bool use_tetrahedral_9; 109 bool use_12bits; 110 111 }; 112 113 /* arr_curve_points - regamma regions/segments specification 114 * arr_points - beginning and end point specified separately (only one on DCE) 115 * corner_points - beginning and end point for all 3 colors (DCN) 116 * rgb_resulted - final curve 117 */ 118 struct pwl_params { 119 struct gamma_curve arr_curve_points[34]; 120 union { 121 struct curve_points arr_points[2]; 122 struct curve_points3 corner_points[2]; 123 }; 124 struct pwl_result_data rgb_resulted[256 + 3]; 125 uint32_t hw_points_num; 126 }; 127 128 /* move to dpp 129 * while we are moving functionality out of opp to dpp to align 130 * HW programming to HW IP, we define these struct in hw_shared 131 * so we can still compile while refactoring 132 */ 133 134 enum lb_pixel_depth { 135 /* do not change the values because it is used as bit vector */ 136 LB_PIXEL_DEPTH_18BPP = 1, 137 LB_PIXEL_DEPTH_24BPP = 2, 138 LB_PIXEL_DEPTH_30BPP = 4, 139 LB_PIXEL_DEPTH_36BPP = 8 140 }; 141 142 enum graphics_csc_adjust_type { 143 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, 144 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ 145 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ 146 }; 147 148 enum ipp_degamma_mode { 149 IPP_DEGAMMA_MODE_BYPASS, 150 IPP_DEGAMMA_MODE_HW_sRGB, 151 IPP_DEGAMMA_MODE_HW_xvYCC, 152 IPP_DEGAMMA_MODE_USER_PWL 153 }; 154 155 enum ipp_output_format { 156 IPP_OUTPUT_FORMAT_12_BIT_FIX, 157 IPP_OUTPUT_FORMAT_16_BIT_BYPASS, 158 IPP_OUTPUT_FORMAT_FLOAT 159 }; 160 161 enum expansion_mode { 162 EXPANSION_MODE_DYNAMIC, 163 EXPANSION_MODE_ZERO 164 }; 165 166 struct default_adjustment { 167 enum lb_pixel_depth lb_color_depth; 168 enum dc_color_space out_color_space; 169 enum dc_color_space in_color_space; 170 enum dc_color_depth color_depth; 171 enum pixel_format surface_pixel_format; 172 enum graphics_csc_adjust_type csc_adjust_type; 173 bool force_hw_default; 174 }; 175 176 177 struct out_csc_color_matrix { 178 enum dc_color_space color_space; 179 uint16_t regval[12]; 180 }; 181 182 enum gamut_remap_select { 183 GAMUT_REMAP_BYPASS = 0, 184 GAMUT_REMAP_COEFF, 185 GAMUT_REMAP_COMA_COEFF, 186 GAMUT_REMAP_COMB_COEFF 187 }; 188 189 enum opp_regamma { 190 OPP_REGAMMA_BYPASS = 0, 191 OPP_REGAMMA_SRGB, 192 OPP_REGAMMA_XVYCC, 193 OPP_REGAMMA_USER 194 }; 195 196 enum optc_dsc_mode { 197 OPTC_DSC_DISABLED = 0, 198 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ 199 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ 200 }; 201 202 struct dc_bias_and_scale { 203 uint16_t scale_red; 204 uint16_t bias_red; 205 uint16_t scale_green; 206 uint16_t bias_green; 207 uint16_t scale_blue; 208 uint16_t bias_blue; 209 }; 210 211 enum test_pattern_dyn_range { 212 TEST_PATTERN_DYN_RANGE_VESA = 0, 213 TEST_PATTERN_DYN_RANGE_CEA 214 }; 215 216 enum test_pattern_mode { 217 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, 218 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, 219 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, 220 TEST_PATTERN_MODE_VERTICALBARS, 221 TEST_PATTERN_MODE_HORIZONTALBARS, 222 TEST_PATTERN_MODE_SINGLERAMP_RGB, 223 TEST_PATTERN_MODE_DUALRAMP_RGB, 224 TEST_PATTERN_MODE_XR_BIAS_RGB 225 }; 226 227 enum test_pattern_color_format { 228 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, 229 TEST_PATTERN_COLOR_FORMAT_BPC_8, 230 TEST_PATTERN_COLOR_FORMAT_BPC_10, 231 TEST_PATTERN_COLOR_FORMAT_BPC_12 232 }; 233 234 enum controller_dp_test_pattern { 235 CONTROLLER_DP_TEST_PATTERN_D102 = 0, 236 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, 237 CONTROLLER_DP_TEST_PATTERN_PRBS7, 238 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, 239 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, 240 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, 241 CONTROLLER_DP_TEST_PATTERN_COLORRAMP, 242 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 243 CONTROLLER_DP_TEST_PATTERN_RESERVED_8, 244 CONTROLLER_DP_TEST_PATTERN_RESERVED_9, 245 CONTROLLER_DP_TEST_PATTERN_RESERVED_A, 246 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, 247 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR 248 }; 249 250 enum controller_dp_color_space { 251 CONTROLLER_DP_COLOR_SPACE_RGB, 252 CONTROLLER_DP_COLOR_SPACE_YCBCR601, 253 CONTROLLER_DP_COLOR_SPACE_YCBCR709, 254 CONTROLLER_DP_COLOR_SPACE_UDEFINED 255 }; 256 257 enum dc_lut_mode { 258 LUT_BYPASS, 259 LUT_RAM_A, 260 LUT_RAM_B 261 }; 262 #endif /* __DAL_HW_SHARED_H__ */ 263
Indexes created Sun Sep 21 15:09:59 GMT 2025