| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| 10742.s | 13 r0 = p5; define
14 dbga(r0.h, 0x1234);
15 dbga(r0.l, 0x1000);
|
| add_imm7.s | 6 r0 = 0 define
7 ASTAT = r0;
|
| ashift.s | 7 r0 = \in (Z); define
9 r2.h = ASHIFT R0.L BY R2.L \opt;
|
| zeroflagrnd.s | 7 ASTAT=R0;
9 R0.L = -32768;
10 R0.H = -1;
11 R0.L = R0 (RND);
12 DBGA ( R0.L , 0 );
14 _DBG R0;
15 //R0 = ASTAT;
16 //DBG R0;
17 //DBGA ( R0.L , 0x1 )
19 r0 = cc; define
22 r0 = cc; define
25 r0 = cc; define
28 r0 = cc; define
31 r0 = cc; define
34 r0 = cc; define
[all...] |
| 10622.s | 15 r0 = i2; define
17 dbga(r0.l, 0x1238);
18 dbga(r0.h, 0xff90);
|
| add_shift.S | 40 r0 = 1; define
41 r0 <<= 31; // r0 should be 0x80000000
44 _dbg r0;
45 r1 = r0;
47 r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflow
|
| cmpacc.s | 12 r0 = 0; define
13 A1.w=r0;
27 astat=r0;
31 r0 = 0; define
32 A0.w=r0;
43 astat=r0;
|
| cmpdreg.S | 7 r0 = 0; define
8 ASTAT = R0;
10 r0.h =0x8000;
13 cc = r1==r0;
20 r0.l = 0xffff;
21 r0.h =0x7fff;
24 cc = r1==r0;
31 r0.l = 0;
32 r0.h =0x8000;
35 cc = r1==r0;
[all...] |
| divq.s | 12 * r0 = dividend, or numerator
15 * r0 = quotient (16-bits)
18 imm32 r0 \num
21 r0 <<= 1; /* Left shift dividend by 1 needed for integer division */
25 divs (r0, r1);
30 divq (r0, r1);
33 r0 = r0.l (x); define
36 CC = r0 == r1
|
| issue121.s | 6 R0 = 0;
7 ASTAT = R0;
8 R0.L = 32767;
9 R0.H = 32767;
12 R0.L = R0 + R1 (RND12);
14 _DBG R0;
22 r0 = cc; define
23 dbga( r0.l, 1);
25 r0 = cc define
28 r0 = cc; define
31 r0 = cc; define
34 r0 = cc; define
37 r0 = cc; define
[all...] |
| issue83.s | 7 R0.H = -32768;
8 R0.L = 0;
9 R0 >>= 0x1;
11 _DBG R0;
18 r0 = cc; define
19 dbga( r0.l, 0);
21 r0 = cc; define
22 dbga( r0.l, 0);
24 r0 = cc; define
25 dbga( r0.l, 0)
27 r0 = cc; define
30 r0 = cc; define
33 r0 = cc; define
46 r0 = cc; define
49 r0 = cc; define
52 r0 = cc; define
55 r0 = cc; define
58 r0 = cc; define
61 r0 = cc; define
75 r0 = cc; define
78 r0 = cc; define
81 r0 = cc; define
84 r0 = cc; define
87 r0 = cc; define
90 r0 = cc; define
[all...] |
| sri.s | 8 r0 = 0; define
17 R0 = A0.w;
18 [ I1 ++ ] = R0;
|
| tar10622.s | 15 r0 = i2; define
17 dbga(r0.l, 0x1238);
18 dbga(r0.h, 0xff90);
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| 10742.s | 13 r0 = p5; define
14 dbga(r0.h, 0x1234);
15 dbga(r0.l, 0x1000);
|
| add_imm7.s | 6 r0 = 0 define
7 ASTAT = r0;
|
| ashift.s | 7 r0 = \in (Z); define
9 r2.h = ASHIFT R0.L BY R2.L \opt;
|
| zeroflagrnd.s | 7 ASTAT=R0;
9 R0.L = -32768;
10 R0.H = -1;
11 R0.L = R0 (RND);
12 DBGA ( R0.L , 0 );
14 _DBG R0;
15 //R0 = ASTAT;
16 //DBG R0;
17 //DBGA ( R0.L , 0x1 )
19 r0 = cc; define
22 r0 = cc; define
25 r0 = cc; define
28 r0 = cc; define
31 r0 = cc; define
34 r0 = cc; define
[all...] |
| 10622.s | 15 r0 = i2; define
17 dbga(r0.l, 0x1238);
18 dbga(r0.h, 0xff90);
|
| add_shift.S | 40 r0 = 1; define
41 r0 <<= 31; // r0 should be 0x80000000
44 _dbg r0;
45 r1 = r0;
47 r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflow
|
| cmpacc.s | 12 r0 = 0; define
13 A1.w=r0;
27 astat=r0;
31 r0 = 0; define
32 A0.w=r0;
43 astat=r0;
|
| cmpdreg.S | 7 r0 = 0; define
8 ASTAT = R0;
10 r0.h =0x8000;
13 cc = r1==r0;
20 r0.l = 0xffff;
21 r0.h =0x7fff;
24 cc = r1==r0;
31 r0.l = 0;
32 r0.h =0x8000;
35 cc = r1==r0;
[all...] |
| divq.s | 12 * r0 = dividend, or numerator
15 * r0 = quotient (16-bits)
18 imm32 r0 \num
21 r0 <<= 1; /* Left shift dividend by 1 needed for integer division */
25 divs (r0, r1);
30 divq (r0, r1);
33 r0 = r0.l (x); define
36 CC = r0 == r1
|
| issue121.s | 6 R0 = 0;
7 ASTAT = R0;
8 R0.L = 32767;
9 R0.H = 32767;
12 R0.L = R0 + R1 (RND12);
14 _DBG R0;
22 r0 = cc; define
23 dbga( r0.l, 1);
25 r0 = cc define
28 r0 = cc; define
31 r0 = cc; define
34 r0 = cc; define
37 r0 = cc; define
[all...] |
| issue83.s | 7 R0.H = -32768;
8 R0.L = 0;
9 R0 >>= 0x1;
11 _DBG R0;
18 r0 = cc; define
19 dbga( r0.l, 0);
21 r0 = cc; define
22 dbga( r0.l, 0);
24 r0 = cc; define
25 dbga( r0.l, 0)
27 r0 = cc; define
30 r0 = cc; define
33 r0 = cc; define
46 r0 = cc; define
49 r0 = cc; define
52 r0 = cc; define
55 r0 = cc; define
58 r0 = cc; define
61 r0 = cc; define
75 r0 = cc; define
78 r0 = cc; define
81 r0 = cc; define
84 r0 = cc; define
87 r0 = cc; define
90 r0 = cc; define
[all...] |
| sri.s | 8 r0 = 0; define
17 R0 = A0.w;
18 [ I1 ++ ] = R0;
|
