1 /* $NetBSD: radeon_r300.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_r300.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $"); 33 34 #include <linux/pci.h> 35 #include <linux/seq_file.h> 36 #include <linux/slab.h> 37 38 #include <drm/drm.h> 39 #include <drm/drm_crtc_helper.h> 40 #include <drm/drm_debugfs.h> 41 #include <drm/drm_device.h> 42 #include <drm/drm_file.h> 43 #include <drm/radeon_drm.h> 44 45 #include "r100_track.h" 46 #include "r300_reg_safe.h" 47 #include "r300d.h" 48 #include "radeon.h" 49 #include "radeon_asic.h" 50 #include "radeon_reg.h" 51 #include "rv350d.h" 52 53 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 54 * 55 * GPU Errata: 56 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 57 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 58 * However, scheduling such write to the ring seems harmless, i suspect 59 * the CP read collide with the flush somehow, or maybe the MC, hard to 60 * tell. (Jerome Glisse) 61 */ 62 63 /* 64 * Indirect registers accessor 65 */ 66 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 67 { 68 unsigned long flags; 69 uint32_t r; 70 71 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 72 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 73 r = RREG32(RADEON_PCIE_DATA); 74 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 75 return r; 76 } 77 78 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 79 { 80 unsigned long flags; 81 82 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 83 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 84 WREG32(RADEON_PCIE_DATA, (v)); 85 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 86 } 87 88 /* 89 * rv370,rv380 PCIE GART 90 */ 91 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 92 93 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 94 { 95 uint32_t tmp; 96 int i; 97 98 /* Workaround HW bug do flush 2 times */ 99 for (i = 0; i < 2; i++) { 100 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 101 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 102 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 103 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 104 } 105 mb(); 106 } 107 108 #define R300_PTE_UNSNOOPED (1 << 0) 109 #define R300_PTE_WRITEABLE (1 << 2) 110 #define R300_PTE_READABLE (1 << 3) 111 112 uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) 113 { 114 addr = (lower_32_bits(addr) >> 8) | 115 ((upper_32_bits(addr) & 0xff) << 24); 116 if (flags & RADEON_GART_PAGE_READ) 117 addr |= R300_PTE_READABLE; 118 if (flags & RADEON_GART_PAGE_WRITE) 119 addr |= R300_PTE_WRITEABLE; 120 if (!(flags & RADEON_GART_PAGE_SNOOP)) 121 addr |= R300_PTE_UNSNOOPED; 122 return addr; 123 } 124 125 #ifdef __NetBSD__ 126 /* 127 * XXX Can't use bus_space here because this is all mapped through the 128 * radeon_bo abstraction. Can't assume we're x86 because this is 129 * AMD/ATI Radeon, not Intel. 130 */ 131 132 # define __iomem volatile 133 # define writel fake_writel 134 135 static inline void 136 fake_writel(uint32_t v, void __iomem *ptr) 137 { 138 139 membar_producer(); 140 *(uint32_t __iomem *)ptr = v; 141 } 142 #endif 143 144 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 145 uint64_t entry) 146 { 147 void __iomem *ptr = rdev->gart.ptr; 148 149 /* on x86 we want this to be CPU endian, on powerpc 150 * on powerpc without HW swappers, it'll get swapped on way 151 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 152 writel(entry, (uint8_t __iomem *)ptr + (i * 4)); 153 } 154 155 #ifdef __NetBSD__ 156 # undef __iomem 157 # undef writel 158 #endif 159 160 int rv370_pcie_gart_init(struct radeon_device *rdev) 161 { 162 int r; 163 164 if (rdev->gart.robj) { 165 WARN(1, "RV370 PCIE GART already initialized\n"); 166 return 0; 167 } 168 /* Initialize common gart structure */ 169 r = radeon_gart_init(rdev); 170 if (r) 171 return r; 172 r = rv370_debugfs_pcie_gart_info_init(rdev); 173 if (r) 174 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 175 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 176 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 177 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 178 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 179 return radeon_gart_table_vram_alloc(rdev); 180 } 181 182 int rv370_pcie_gart_enable(struct radeon_device *rdev) 183 { 184 uint32_t table_addr; 185 uint32_t tmp; 186 int r; 187 188 if (rdev->gart.robj == NULL) { 189 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 190 return -EINVAL; 191 } 192 r = radeon_gart_table_vram_pin(rdev); 193 if (r) 194 return r; 195 /* discard memory request outside of configured range */ 196 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 197 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 198 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 199 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 200 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 201 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 202 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 203 table_addr = rdev->gart.table_addr; 204 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 205 /* FIXME: setup default page */ 206 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 207 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 208 /* Clear error */ 209 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 210 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 211 tmp |= RADEON_PCIE_TX_GART_EN; 212 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 213 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 214 rv370_pcie_gart_tlb_flush(rdev); 215 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 216 (unsigned)(rdev->mc.gtt_size >> 20), 217 (unsigned long long)table_addr); 218 rdev->gart.ready = true; 219 return 0; 220 } 221 222 void rv370_pcie_gart_disable(struct radeon_device *rdev) 223 { 224 u32 tmp; 225 226 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 227 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 228 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 229 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 230 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 231 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 232 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 233 radeon_gart_table_vram_unpin(rdev); 234 } 235 236 void rv370_pcie_gart_fini(struct radeon_device *rdev) 237 { 238 radeon_gart_fini(rdev); 239 rv370_pcie_gart_disable(rdev); 240 radeon_gart_table_vram_free(rdev); 241 } 242 243 void r300_fence_ring_emit(struct radeon_device *rdev, 244 struct radeon_fence *fence) 245 { 246 struct radeon_ring *ring = &rdev->ring[fence->ring]; 247 248 /* Who ever call radeon_fence_emit should call ring_lock and ask 249 * for enough space (today caller are ib schedule and buffer move) */ 250 /* Write SC register so SC & US assert idle */ 251 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 252 radeon_ring_write(ring, 0); 253 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 254 radeon_ring_write(ring, 0); 255 /* Flush 3D cache */ 256 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 257 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 258 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 259 radeon_ring_write(ring, R300_ZC_FLUSH); 260 /* Wait until IDLE & CLEAN */ 261 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 262 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 263 RADEON_WAIT_2D_IDLECLEAN | 264 RADEON_WAIT_DMA_GUI_IDLE)); 265 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 266 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 267 RADEON_HDP_READ_BUFFER_INVALIDATE); 268 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 269 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 270 /* Emit fence sequence & fire IRQ */ 271 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 272 radeon_ring_write(ring, fence->seq); 273 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 274 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 275 } 276 277 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 278 { 279 unsigned gb_tile_config; 280 int r; 281 282 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 283 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 284 switch(rdev->num_gb_pipes) { 285 case 2: 286 gb_tile_config |= R300_PIPE_COUNT_R300; 287 break; 288 case 3: 289 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 290 break; 291 case 4: 292 gb_tile_config |= R300_PIPE_COUNT_R420; 293 break; 294 case 1: 295 default: 296 gb_tile_config |= R300_PIPE_COUNT_RV350; 297 break; 298 } 299 300 r = radeon_ring_lock(rdev, ring, 64); 301 if (r) { 302 return; 303 } 304 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 305 radeon_ring_write(ring, 306 RADEON_ISYNC_ANY2D_IDLE3D | 307 RADEON_ISYNC_ANY3D_IDLE2D | 308 RADEON_ISYNC_WAIT_IDLEGUI | 309 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 310 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 311 radeon_ring_write(ring, gb_tile_config); 312 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 313 radeon_ring_write(ring, 314 RADEON_WAIT_2D_IDLECLEAN | 315 RADEON_WAIT_3D_IDLECLEAN); 316 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 317 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 318 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 319 radeon_ring_write(ring, 0); 320 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 321 radeon_ring_write(ring, 0); 322 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 323 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 324 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 325 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 326 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 327 radeon_ring_write(ring, 328 RADEON_WAIT_2D_IDLECLEAN | 329 RADEON_WAIT_3D_IDLECLEAN); 330 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 331 radeon_ring_write(ring, 0); 332 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 333 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 334 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 335 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 336 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 337 radeon_ring_write(ring, 338 ((6 << R300_MS_X0_SHIFT) | 339 (6 << R300_MS_Y0_SHIFT) | 340 (6 << R300_MS_X1_SHIFT) | 341 (6 << R300_MS_Y1_SHIFT) | 342 (6 << R300_MS_X2_SHIFT) | 343 (6 << R300_MS_Y2_SHIFT) | 344 (6 << R300_MSBD0_Y_SHIFT) | 345 (6 << R300_MSBD0_X_SHIFT))); 346 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 347 radeon_ring_write(ring, 348 ((6 << R300_MS_X3_SHIFT) | 349 (6 << R300_MS_Y3_SHIFT) | 350 (6 << R300_MS_X4_SHIFT) | 351 (6 << R300_MS_Y4_SHIFT) | 352 (6 << R300_MS_X5_SHIFT) | 353 (6 << R300_MS_Y5_SHIFT) | 354 (6 << R300_MSBD1_SHIFT))); 355 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 356 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 357 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 358 radeon_ring_write(ring, 359 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 360 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 361 radeon_ring_write(ring, 362 R300_GEOMETRY_ROUND_NEAREST | 363 R300_COLOR_ROUND_NEAREST); 364 radeon_ring_unlock_commit(rdev, ring, false); 365 } 366 367 static void r300_errata(struct radeon_device *rdev) 368 { 369 rdev->pll_errata = 0; 370 371 if (rdev->family == CHIP_R300 && 372 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 373 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 374 } 375 } 376 377 int r300_mc_wait_for_idle(struct radeon_device *rdev) 378 { 379 unsigned i; 380 uint32_t tmp; 381 382 for (i = 0; i < rdev->usec_timeout; i++) { 383 /* read MC_STATUS */ 384 tmp = RREG32(RADEON_MC_STATUS); 385 if (tmp & R300_MC_IDLE) { 386 return 0; 387 } 388 udelay(1); 389 } 390 return -1; 391 } 392 393 static void r300_gpu_init(struct radeon_device *rdev) 394 { 395 uint32_t gb_tile_config, tmp; 396 397 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 398 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 399 /* r300,r350 */ 400 rdev->num_gb_pipes = 2; 401 } else { 402 /* rv350,rv370,rv380,r300 AD, r350 AH */ 403 rdev->num_gb_pipes = 1; 404 } 405 rdev->num_z_pipes = 1; 406 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 407 switch (rdev->num_gb_pipes) { 408 case 2: 409 gb_tile_config |= R300_PIPE_COUNT_R300; 410 break; 411 case 3: 412 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 413 break; 414 case 4: 415 gb_tile_config |= R300_PIPE_COUNT_R420; 416 break; 417 default: 418 case 1: 419 gb_tile_config |= R300_PIPE_COUNT_RV350; 420 break; 421 } 422 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 423 424 if (r100_gui_wait_for_idle(rdev)) { 425 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 426 } 427 428 tmp = RREG32(R300_DST_PIPE_CONFIG); 429 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 430 431 WREG32(R300_RB2D_DSTCACHE_MODE, 432 R300_DC_AUTOFLUSH_ENABLE | 433 R300_DC_DC_DISABLE_IGNORE_PE); 434 435 if (r100_gui_wait_for_idle(rdev)) { 436 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 437 } 438 if (r300_mc_wait_for_idle(rdev)) { 439 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); 440 } 441 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized\n", 442 rdev->num_gb_pipes, rdev->num_z_pipes); 443 } 444 445 int r300_asic_reset(struct radeon_device *rdev, bool hard) 446 { 447 struct r100_mc_save save; 448 u32 status, tmp; 449 int ret = 0; 450 451 status = RREG32(R_000E40_RBBM_STATUS); 452 if (!G_000E40_GUI_ACTIVE(status)) { 453 return 0; 454 } 455 r100_mc_stop(rdev, &save); 456 status = RREG32(R_000E40_RBBM_STATUS); 457 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 458 /* stop CP */ 459 WREG32(RADEON_CP_CSQ_CNTL, 0); 460 tmp = RREG32(RADEON_CP_RB_CNTL); 461 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 462 WREG32(RADEON_CP_RB_RPTR_WR, 0); 463 WREG32(RADEON_CP_RB_WPTR, 0); 464 WREG32(RADEON_CP_RB_CNTL, tmp); 465 /* save PCI state */ 466 pci_save_state(rdev->pdev); 467 /* disable bus mastering */ 468 r100_bm_disable(rdev); 469 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 470 S_0000F0_SOFT_RESET_GA(1)); 471 RREG32(R_0000F0_RBBM_SOFT_RESET); 472 mdelay(500); 473 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 474 mdelay(1); 475 status = RREG32(R_000E40_RBBM_STATUS); 476 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 477 /* resetting the CP seems to be problematic sometimes it end up 478 * hard locking the computer, but it's necessary for successful 479 * reset more test & playing is needed on R3XX/R4XX to find a 480 * reliable (if any solution) 481 */ 482 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 483 RREG32(R_0000F0_RBBM_SOFT_RESET); 484 mdelay(500); 485 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 486 mdelay(1); 487 status = RREG32(R_000E40_RBBM_STATUS); 488 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 489 /* restore PCI & busmastering */ 490 pci_restore_state(rdev->pdev); 491 r100_enable_bm(rdev); 492 /* Check if GPU is idle */ 493 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 494 dev_err(rdev->dev, "failed to reset GPU\n"); 495 ret = -1; 496 } else 497 dev_info(rdev->dev, "GPU reset succeed\n"); 498 r100_mc_resume(rdev, &save); 499 return ret; 500 } 501 502 /* 503 * r300,r350,rv350,rv380 VRAM info 504 */ 505 void r300_mc_init(struct radeon_device *rdev) 506 { 507 u64 base; 508 u32 tmp; 509 510 /* DDR for all card after R300 & IGP */ 511 rdev->mc.vram_is_ddr = true; 512 tmp = RREG32(RADEON_MEM_CNTL); 513 tmp &= R300_MEM_NUM_CHANNELS_MASK; 514 switch (tmp) { 515 case 0: rdev->mc.vram_width = 64; break; 516 case 1: rdev->mc.vram_width = 128; break; 517 case 2: rdev->mc.vram_width = 256; break; 518 default: rdev->mc.vram_width = 128; break; 519 } 520 r100_vram_init_sizes(rdev); 521 base = rdev->mc.aper_base; 522 if (rdev->flags & RADEON_IS_IGP) 523 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 524 radeon_vram_location(rdev, &rdev->mc, base); 525 rdev->mc.gtt_base_align = 0; 526 if (!(rdev->flags & RADEON_IS_AGP)) 527 radeon_gtt_location(rdev, &rdev->mc); 528 radeon_update_bandwidth_info(rdev); 529 } 530 531 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 532 { 533 uint32_t link_width_cntl, mask; 534 535 if (rdev->flags & RADEON_IS_IGP) 536 return; 537 538 if (!(rdev->flags & RADEON_IS_PCIE)) 539 return; 540 541 /* FIXME wait for idle */ 542 543 switch (lanes) { 544 case 0: 545 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 546 break; 547 case 1: 548 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 549 break; 550 case 2: 551 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 552 break; 553 case 4: 554 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 555 break; 556 case 8: 557 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 558 break; 559 case 12: 560 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 561 break; 562 case 16: 563 default: 564 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 565 break; 566 } 567 568 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 569 570 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 571 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 572 return; 573 574 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 575 RADEON_PCIE_LC_RECONFIG_NOW | 576 RADEON_PCIE_LC_RECONFIG_LATER | 577 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 578 link_width_cntl |= mask; 579 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 580 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 581 RADEON_PCIE_LC_RECONFIG_NOW)); 582 583 /* wait for lane set to complete */ 584 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 585 while (link_width_cntl == 0xffffffff) 586 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 587 588 } 589 590 int rv370_get_pcie_lanes(struct radeon_device *rdev) 591 { 592 u32 link_width_cntl; 593 594 if (rdev->flags & RADEON_IS_IGP) 595 return 0; 596 597 if (!(rdev->flags & RADEON_IS_PCIE)) 598 return 0; 599 600 /* FIXME wait for idle */ 601 602 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 603 604 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 605 case RADEON_PCIE_LC_LINK_WIDTH_X0: 606 return 0; 607 case RADEON_PCIE_LC_LINK_WIDTH_X1: 608 return 1; 609 case RADEON_PCIE_LC_LINK_WIDTH_X2: 610 return 2; 611 case RADEON_PCIE_LC_LINK_WIDTH_X4: 612 return 4; 613 case RADEON_PCIE_LC_LINK_WIDTH_X8: 614 return 8; 615 case RADEON_PCIE_LC_LINK_WIDTH_X16: 616 default: 617 return 16; 618 } 619 } 620 621 #if defined(CONFIG_DEBUG_FS) 622 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 623 { 624 struct drm_info_node *node = (struct drm_info_node *) m->private; 625 struct drm_device *dev = node->minor->dev; 626 struct radeon_device *rdev = dev->dev_private; 627 uint32_t tmp; 628 629 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 630 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 631 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 632 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 633 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 634 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 635 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 636 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 637 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 638 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 639 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 640 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 641 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 642 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 643 return 0; 644 } 645 646 static struct drm_info_list rv370_pcie_gart_info_list[] = { 647 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 648 }; 649 #endif 650 651 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 652 { 653 #if defined(CONFIG_DEBUG_FS) 654 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 655 #else 656 return 0; 657 #endif 658 } 659 660 static int r300_packet0_check(struct radeon_cs_parser *p, 661 struct radeon_cs_packet *pkt, 662 unsigned idx, unsigned reg) 663 { 664 struct radeon_bo_list *reloc; 665 struct r100_cs_track *track; 666 volatile uint32_t *ib; 667 uint32_t tmp, tile_flags = 0; 668 unsigned i; 669 int r; 670 u32 idx_value; 671 672 ib = p->ib.ptr; 673 track = (struct r100_cs_track *)p->track; 674 idx_value = radeon_get_ib_value(p, idx); 675 676 switch(reg) { 677 case AVIVO_D1MODE_VLINE_START_END: 678 case RADEON_CRTC_GUI_TRIG_VLINE: 679 r = r100_cs_packet_parse_vline(p); 680 if (r) { 681 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 682 idx, reg); 683 radeon_cs_dump_packet(p, pkt); 684 return r; 685 } 686 break; 687 case RADEON_DST_PITCH_OFFSET: 688 case RADEON_SRC_PITCH_OFFSET: 689 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 690 if (r) 691 return r; 692 break; 693 case R300_RB3D_COLOROFFSET0: 694 case R300_RB3D_COLOROFFSET1: 695 case R300_RB3D_COLOROFFSET2: 696 case R300_RB3D_COLOROFFSET3: 697 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 698 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 699 if (r) { 700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 701 idx, reg); 702 radeon_cs_dump_packet(p, pkt); 703 return r; 704 } 705 track->cb[i].robj = reloc->robj; 706 track->cb[i].offset = idx_value; 707 track->cb_dirty = true; 708 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 709 break; 710 case R300_ZB_DEPTHOFFSET: 711 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 712 if (r) { 713 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 714 idx, reg); 715 radeon_cs_dump_packet(p, pkt); 716 return r; 717 } 718 track->zb.robj = reloc->robj; 719 track->zb.offset = idx_value; 720 track->zb_dirty = true; 721 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 722 break; 723 case R300_TX_OFFSET_0: 724 case R300_TX_OFFSET_0+4: 725 case R300_TX_OFFSET_0+8: 726 case R300_TX_OFFSET_0+12: 727 case R300_TX_OFFSET_0+16: 728 case R300_TX_OFFSET_0+20: 729 case R300_TX_OFFSET_0+24: 730 case R300_TX_OFFSET_0+28: 731 case R300_TX_OFFSET_0+32: 732 case R300_TX_OFFSET_0+36: 733 case R300_TX_OFFSET_0+40: 734 case R300_TX_OFFSET_0+44: 735 case R300_TX_OFFSET_0+48: 736 case R300_TX_OFFSET_0+52: 737 case R300_TX_OFFSET_0+56: 738 case R300_TX_OFFSET_0+60: 739 i = (reg - R300_TX_OFFSET_0) >> 2; 740 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 741 if (r) { 742 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 743 idx, reg); 744 radeon_cs_dump_packet(p, pkt); 745 return r; 746 } 747 748 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 749 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 750 ((idx_value & ~31) + (u32)reloc->gpu_offset); 751 } else { 752 if (reloc->tiling_flags & RADEON_TILING_MACRO) 753 tile_flags |= R300_TXO_MACRO_TILE; 754 if (reloc->tiling_flags & RADEON_TILING_MICRO) 755 tile_flags |= R300_TXO_MICRO_TILE; 756 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 757 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 758 759 tmp = idx_value + ((u32)reloc->gpu_offset); 760 tmp |= tile_flags; 761 ib[idx] = tmp; 762 } 763 track->textures[i].robj = reloc->robj; 764 track->tex_dirty = true; 765 break; 766 /* Tracked registers */ 767 case 0x2084: 768 /* VAP_VF_CNTL */ 769 track->vap_vf_cntl = idx_value; 770 break; 771 case 0x20B4: 772 /* VAP_VTX_SIZE */ 773 track->vtx_size = idx_value & 0x7F; 774 break; 775 case 0x2134: 776 /* VAP_VF_MAX_VTX_INDX */ 777 track->max_indx = idx_value & 0x00FFFFFFUL; 778 break; 779 case 0x2088: 780 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 781 if (p->rdev->family < CHIP_RV515) 782 goto fail; 783 track->vap_alt_nverts = idx_value & 0xFFFFFF; 784 break; 785 case 0x43E4: 786 /* SC_SCISSOR1 */ 787 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 788 if (p->rdev->family < CHIP_RV515) { 789 track->maxy -= 1440; 790 } 791 track->cb_dirty = true; 792 track->zb_dirty = true; 793 break; 794 case 0x4E00: 795 /* RB3D_CCTL */ 796 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 797 p->rdev->cmask_filp != p->filp) { 798 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 799 return -EINVAL; 800 } 801 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 802 track->cb_dirty = true; 803 break; 804 case 0x4E38: 805 case 0x4E3C: 806 case 0x4E40: 807 case 0x4E44: 808 /* RB3D_COLORPITCH0 */ 809 /* RB3D_COLORPITCH1 */ 810 /* RB3D_COLORPITCH2 */ 811 /* RB3D_COLORPITCH3 */ 812 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 813 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 814 if (r) { 815 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 816 idx, reg); 817 radeon_cs_dump_packet(p, pkt); 818 return r; 819 } 820 821 if (reloc->tiling_flags & RADEON_TILING_MACRO) 822 tile_flags |= R300_COLOR_TILE_ENABLE; 823 if (reloc->tiling_flags & RADEON_TILING_MICRO) 824 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 825 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 826 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 827 828 tmp = idx_value & ~(0x7 << 16); 829 tmp |= tile_flags; 830 ib[idx] = tmp; 831 } 832 i = (reg - 0x4E38) >> 2; 833 track->cb[i].pitch = idx_value & 0x3FFE; 834 switch (((idx_value >> 21) & 0xF)) { 835 case 9: 836 case 11: 837 case 12: 838 track->cb[i].cpp = 1; 839 break; 840 case 3: 841 case 4: 842 case 13: 843 case 15: 844 track->cb[i].cpp = 2; 845 break; 846 case 5: 847 if (p->rdev->family < CHIP_RV515) { 848 DRM_ERROR("Invalid color buffer format (%d)!\n", 849 ((idx_value >> 21) & 0xF)); 850 return -EINVAL; 851 } 852 /* Fall through. */ 853 case 6: 854 track->cb[i].cpp = 4; 855 break; 856 case 10: 857 track->cb[i].cpp = 8; 858 break; 859 case 7: 860 track->cb[i].cpp = 16; 861 break; 862 default: 863 DRM_ERROR("Invalid color buffer format (%d) !\n", 864 ((idx_value >> 21) & 0xF)); 865 return -EINVAL; 866 } 867 track->cb_dirty = true; 868 break; 869 case 0x4F00: 870 /* ZB_CNTL */ 871 if (idx_value & 2) { 872 track->z_enabled = true; 873 } else { 874 track->z_enabled = false; 875 } 876 track->zb_dirty = true; 877 break; 878 case 0x4F10: 879 /* ZB_FORMAT */ 880 switch ((idx_value & 0xF)) { 881 case 0: 882 case 1: 883 track->zb.cpp = 2; 884 break; 885 case 2: 886 track->zb.cpp = 4; 887 break; 888 default: 889 DRM_ERROR("Invalid z buffer format (%d) !\n", 890 (idx_value & 0xF)); 891 return -EINVAL; 892 } 893 track->zb_dirty = true; 894 break; 895 case 0x4F24: 896 /* ZB_DEPTHPITCH */ 897 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 898 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 899 if (r) { 900 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 901 idx, reg); 902 radeon_cs_dump_packet(p, pkt); 903 return r; 904 } 905 906 if (reloc->tiling_flags & RADEON_TILING_MACRO) 907 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 908 if (reloc->tiling_flags & RADEON_TILING_MICRO) 909 tile_flags |= R300_DEPTHMICROTILE_TILED; 910 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 911 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 912 913 tmp = idx_value & ~(0x7 << 16); 914 tmp |= tile_flags; 915 ib[idx] = tmp; 916 } 917 track->zb.pitch = idx_value & 0x3FFC; 918 track->zb_dirty = true; 919 break; 920 case 0x4104: 921 /* TX_ENABLE */ 922 for (i = 0; i < 16; i++) { 923 bool enabled; 924 925 enabled = !!(idx_value & (1 << i)); 926 track->textures[i].enabled = enabled; 927 } 928 track->tex_dirty = true; 929 break; 930 case 0x44C0: 931 case 0x44C4: 932 case 0x44C8: 933 case 0x44CC: 934 case 0x44D0: 935 case 0x44D4: 936 case 0x44D8: 937 case 0x44DC: 938 case 0x44E0: 939 case 0x44E4: 940 case 0x44E8: 941 case 0x44EC: 942 case 0x44F0: 943 case 0x44F4: 944 case 0x44F8: 945 case 0x44FC: 946 /* TX_FORMAT1_[0-15] */ 947 i = (reg - 0x44C0) >> 2; 948 tmp = (idx_value >> 25) & 0x3; 949 track->textures[i].tex_coord_type = tmp; 950 switch ((idx_value & 0x1F)) { 951 case R300_TX_FORMAT_X8: 952 case R300_TX_FORMAT_Y4X4: 953 case R300_TX_FORMAT_Z3Y3X2: 954 track->textures[i].cpp = 1; 955 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 956 break; 957 case R300_TX_FORMAT_X16: 958 case R300_TX_FORMAT_FL_I16: 959 case R300_TX_FORMAT_Y8X8: 960 case R300_TX_FORMAT_Z5Y6X5: 961 case R300_TX_FORMAT_Z6Y5X5: 962 case R300_TX_FORMAT_W4Z4Y4X4: 963 case R300_TX_FORMAT_W1Z5Y5X5: 964 case R300_TX_FORMAT_D3DMFT_CxV8U8: 965 case R300_TX_FORMAT_B8G8_B8G8: 966 case R300_TX_FORMAT_G8R8_G8B8: 967 track->textures[i].cpp = 2; 968 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 969 break; 970 case R300_TX_FORMAT_Y16X16: 971 case R300_TX_FORMAT_FL_I16A16: 972 case R300_TX_FORMAT_Z11Y11X10: 973 case R300_TX_FORMAT_Z10Y11X11: 974 case R300_TX_FORMAT_W8Z8Y8X8: 975 case R300_TX_FORMAT_W2Z10Y10X10: 976 case 0x17: 977 case R300_TX_FORMAT_FL_I32: 978 case 0x1e: 979 track->textures[i].cpp = 4; 980 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 981 break; 982 case R300_TX_FORMAT_W16Z16Y16X16: 983 case R300_TX_FORMAT_FL_R16G16B16A16: 984 case R300_TX_FORMAT_FL_I32A32: 985 track->textures[i].cpp = 8; 986 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 987 break; 988 case R300_TX_FORMAT_FL_R32G32B32A32: 989 track->textures[i].cpp = 16; 990 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 991 break; 992 case R300_TX_FORMAT_DXT1: 993 track->textures[i].cpp = 1; 994 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 995 break; 996 case R300_TX_FORMAT_ATI2N: 997 if (p->rdev->family < CHIP_R420) { 998 DRM_ERROR("Invalid texture format %u\n", 999 (idx_value & 0x1F)); 1000 return -EINVAL; 1001 } 1002 /* The same rules apply as for DXT3/5. */ 1003 /* Fall through. */ 1004 case R300_TX_FORMAT_DXT3: 1005 case R300_TX_FORMAT_DXT5: 1006 track->textures[i].cpp = 1; 1007 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1008 break; 1009 default: 1010 DRM_ERROR("Invalid texture format %u\n", 1011 (idx_value & 0x1F)); 1012 return -EINVAL; 1013 } 1014 track->tex_dirty = true; 1015 break; 1016 case 0x4400: 1017 case 0x4404: 1018 case 0x4408: 1019 case 0x440C: 1020 case 0x4410: 1021 case 0x4414: 1022 case 0x4418: 1023 case 0x441C: 1024 case 0x4420: 1025 case 0x4424: 1026 case 0x4428: 1027 case 0x442C: 1028 case 0x4430: 1029 case 0x4434: 1030 case 0x4438: 1031 case 0x443C: 1032 /* TX_FILTER0_[0-15] */ 1033 i = (reg - 0x4400) >> 2; 1034 tmp = idx_value & 0x7; 1035 if (tmp == 2 || tmp == 4 || tmp == 6) { 1036 track->textures[i].roundup_w = false; 1037 } 1038 tmp = (idx_value >> 3) & 0x7; 1039 if (tmp == 2 || tmp == 4 || tmp == 6) { 1040 track->textures[i].roundup_h = false; 1041 } 1042 track->tex_dirty = true; 1043 break; 1044 case 0x4500: 1045 case 0x4504: 1046 case 0x4508: 1047 case 0x450C: 1048 case 0x4510: 1049 case 0x4514: 1050 case 0x4518: 1051 case 0x451C: 1052 case 0x4520: 1053 case 0x4524: 1054 case 0x4528: 1055 case 0x452C: 1056 case 0x4530: 1057 case 0x4534: 1058 case 0x4538: 1059 case 0x453C: 1060 /* TX_FORMAT2_[0-15] */ 1061 i = (reg - 0x4500) >> 2; 1062 tmp = idx_value & 0x3FFF; 1063 track->textures[i].pitch = tmp + 1; 1064 if (p->rdev->family >= CHIP_RV515) { 1065 tmp = ((idx_value >> 15) & 1) << 11; 1066 track->textures[i].width_11 = tmp; 1067 tmp = ((idx_value >> 16) & 1) << 11; 1068 track->textures[i].height_11 = tmp; 1069 1070 /* ATI1N */ 1071 if (idx_value & (1 << 14)) { 1072 /* The same rules apply as for DXT1. */ 1073 track->textures[i].compress_format = 1074 R100_TRACK_COMP_DXT1; 1075 } 1076 } else if (idx_value & (1 << 14)) { 1077 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1078 return -EINVAL; 1079 } 1080 track->tex_dirty = true; 1081 break; 1082 case 0x4480: 1083 case 0x4484: 1084 case 0x4488: 1085 case 0x448C: 1086 case 0x4490: 1087 case 0x4494: 1088 case 0x4498: 1089 case 0x449C: 1090 case 0x44A0: 1091 case 0x44A4: 1092 case 0x44A8: 1093 case 0x44AC: 1094 case 0x44B0: 1095 case 0x44B4: 1096 case 0x44B8: 1097 case 0x44BC: 1098 /* TX_FORMAT0_[0-15] */ 1099 i = (reg - 0x4480) >> 2; 1100 tmp = idx_value & 0x7FF; 1101 track->textures[i].width = tmp + 1; 1102 tmp = (idx_value >> 11) & 0x7FF; 1103 track->textures[i].height = tmp + 1; 1104 tmp = (idx_value >> 26) & 0xF; 1105 track->textures[i].num_levels = tmp; 1106 tmp = idx_value & (1 << 31); 1107 track->textures[i].use_pitch = !!tmp; 1108 tmp = (idx_value >> 22) & 0xF; 1109 track->textures[i].txdepth = tmp; 1110 track->tex_dirty = true; 1111 break; 1112 case R300_ZB_ZPASS_ADDR: 1113 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1114 if (r) { 1115 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1116 idx, reg); 1117 radeon_cs_dump_packet(p, pkt); 1118 return r; 1119 } 1120 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1121 break; 1122 case 0x4e0c: 1123 /* RB3D_COLOR_CHANNEL_MASK */ 1124 track->color_channel_mask = idx_value; 1125 track->cb_dirty = true; 1126 break; 1127 case 0x43a4: 1128 /* SC_HYPERZ_EN */ 1129 /* r300c emits this register - we need to disable hyperz for it 1130 * without complaining */ 1131 if (p->rdev->hyperz_filp != p->filp) { 1132 if (idx_value & 0x1) 1133 ib[idx] = idx_value & ~1; 1134 } 1135 break; 1136 case 0x4f1c: 1137 /* ZB_BW_CNTL */ 1138 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1139 track->cb_dirty = true; 1140 track->zb_dirty = true; 1141 if (p->rdev->hyperz_filp != p->filp) { 1142 if (idx_value & (R300_HIZ_ENABLE | 1143 R300_RD_COMP_ENABLE | 1144 R300_WR_COMP_ENABLE | 1145 R300_FAST_FILL_ENABLE)) 1146 goto fail; 1147 } 1148 break; 1149 case 0x4e04: 1150 /* RB3D_BLENDCNTL */ 1151 track->blend_read_enable = !!(idx_value & (1 << 2)); 1152 track->cb_dirty = true; 1153 break; 1154 case R300_RB3D_AARESOLVE_OFFSET: 1155 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1156 if (r) { 1157 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1158 idx, reg); 1159 radeon_cs_dump_packet(p, pkt); 1160 return r; 1161 } 1162 track->aa.robj = reloc->robj; 1163 track->aa.offset = idx_value; 1164 track->aa_dirty = true; 1165 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1166 break; 1167 case R300_RB3D_AARESOLVE_PITCH: 1168 track->aa.pitch = idx_value & 0x3FFE; 1169 track->aa_dirty = true; 1170 break; 1171 case R300_RB3D_AARESOLVE_CTL: 1172 track->aaresolve = idx_value & 0x1; 1173 track->aa_dirty = true; 1174 break; 1175 case 0x4f30: /* ZB_MASK_OFFSET */ 1176 case 0x4f34: /* ZB_ZMASK_PITCH */ 1177 case 0x4f44: /* ZB_HIZ_OFFSET */ 1178 case 0x4f54: /* ZB_HIZ_PITCH */ 1179 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1180 goto fail; 1181 break; 1182 case 0x4028: 1183 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1184 goto fail; 1185 /* GB_Z_PEQ_CONFIG */ 1186 if (p->rdev->family >= CHIP_RV350) 1187 break; 1188 goto fail; 1189 break; 1190 case 0x4be8: 1191 /* valid register only on RV530 */ 1192 if (p->rdev->family == CHIP_RV530) 1193 break; 1194 /* fallthrough do not move */ 1195 default: 1196 goto fail; 1197 } 1198 return 0; 1199 fail: 1200 pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1201 reg, idx, idx_value); 1202 return -EINVAL; 1203 } 1204 1205 static int r300_packet3_check(struct radeon_cs_parser *p, 1206 struct radeon_cs_packet *pkt) 1207 { 1208 struct radeon_bo_list *reloc; 1209 struct r100_cs_track *track; 1210 volatile uint32_t *ib; 1211 unsigned idx; 1212 int r; 1213 1214 ib = p->ib.ptr; 1215 idx = pkt->idx + 1; 1216 track = (struct r100_cs_track *)p->track; 1217 switch(pkt->opcode) { 1218 case PACKET3_3D_LOAD_VBPNTR: 1219 r = r100_packet3_load_vbpntr(p, pkt, idx); 1220 if (r) 1221 return r; 1222 break; 1223 case PACKET3_INDX_BUFFER: 1224 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1225 if (r) { 1226 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1227 radeon_cs_dump_packet(p, pkt); 1228 return r; 1229 } 1230 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1231 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1232 if (r) { 1233 return r; 1234 } 1235 break; 1236 /* Draw packet */ 1237 case PACKET3_3D_DRAW_IMMD: 1238 /* Number of dwords is vtx_size * (num_vertices - 1) 1239 * PRIM_WALK must be equal to 3 vertex data in embedded 1240 * in cmd stream */ 1241 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1242 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1243 return -EINVAL; 1244 } 1245 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1246 track->immd_dwords = pkt->count - 1; 1247 r = r100_cs_track_check(p->rdev, track); 1248 if (r) { 1249 return r; 1250 } 1251 break; 1252 case PACKET3_3D_DRAW_IMMD_2: 1253 /* Number of dwords is vtx_size * (num_vertices - 1) 1254 * PRIM_WALK must be equal to 3 vertex data in embedded 1255 * in cmd stream */ 1256 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1257 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1258 return -EINVAL; 1259 } 1260 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1261 track->immd_dwords = pkt->count; 1262 r = r100_cs_track_check(p->rdev, track); 1263 if (r) { 1264 return r; 1265 } 1266 break; 1267 case PACKET3_3D_DRAW_VBUF: 1268 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1269 r = r100_cs_track_check(p->rdev, track); 1270 if (r) { 1271 return r; 1272 } 1273 break; 1274 case PACKET3_3D_DRAW_VBUF_2: 1275 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1276 r = r100_cs_track_check(p->rdev, track); 1277 if (r) { 1278 return r; 1279 } 1280 break; 1281 case PACKET3_3D_DRAW_INDX: 1282 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1283 r = r100_cs_track_check(p->rdev, track); 1284 if (r) { 1285 return r; 1286 } 1287 break; 1288 case PACKET3_3D_DRAW_INDX_2: 1289 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1290 r = r100_cs_track_check(p->rdev, track); 1291 if (r) { 1292 return r; 1293 } 1294 break; 1295 case PACKET3_3D_CLEAR_HIZ: 1296 case PACKET3_3D_CLEAR_ZMASK: 1297 if (p->rdev->hyperz_filp != p->filp) 1298 return -EINVAL; 1299 break; 1300 case PACKET3_3D_CLEAR_CMASK: 1301 if (p->rdev->cmask_filp != p->filp) 1302 return -EINVAL; 1303 break; 1304 case PACKET3_NOP: 1305 break; 1306 default: 1307 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1308 return -EINVAL; 1309 } 1310 return 0; 1311 } 1312 1313 int r300_cs_parse(struct radeon_cs_parser *p) 1314 { 1315 struct radeon_cs_packet pkt; 1316 struct r100_cs_track *track; 1317 int r; 1318 1319 track = kzalloc(sizeof(*track), GFP_KERNEL); 1320 if (track == NULL) 1321 return -ENOMEM; 1322 r100_cs_track_clear(p->rdev, track); 1323 p->track = track; 1324 do { 1325 r = radeon_cs_packet_parse(p, &pkt, p->idx); 1326 if (r) { 1327 return r; 1328 } 1329 p->idx += pkt.count + 2; 1330 switch (pkt.type) { 1331 case RADEON_PACKET_TYPE0: 1332 r = r100_cs_parse_packet0(p, &pkt, 1333 p->rdev->config.r300.reg_safe_bm, 1334 p->rdev->config.r300.reg_safe_bm_size, 1335 &r300_packet0_check); 1336 break; 1337 case RADEON_PACKET_TYPE2: 1338 break; 1339 case RADEON_PACKET_TYPE3: 1340 r = r300_packet3_check(p, &pkt); 1341 break; 1342 default: 1343 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1344 return -EINVAL; 1345 } 1346 if (r) { 1347 return r; 1348 } 1349 } while (p->idx < p->chunk_ib->length_dw); 1350 return 0; 1351 } 1352 1353 void r300_set_reg_safe(struct radeon_device *rdev) 1354 { 1355 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1356 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1357 } 1358 1359 void r300_mc_program(struct radeon_device *rdev) 1360 { 1361 struct r100_mc_save save; 1362 int r; 1363 1364 r = r100_debugfs_mc_info_init(rdev); 1365 if (r) { 1366 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1367 } 1368 1369 /* Stops all mc clients */ 1370 r100_mc_stop(rdev, &save); 1371 if (rdev->flags & RADEON_IS_AGP) { 1372 WREG32(R_00014C_MC_AGP_LOCATION, 1373 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1374 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1375 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1376 WREG32(R_00015C_AGP_BASE_2, 1377 upper_32_bits(rdev->mc.agp_base) & 0xff); 1378 } else { 1379 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1380 WREG32(R_000170_AGP_BASE, 0); 1381 WREG32(R_00015C_AGP_BASE_2, 0); 1382 } 1383 /* Wait for mc idle */ 1384 if (r300_mc_wait_for_idle(rdev)) 1385 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1386 /* Program MC, should be a 32bits limited address space */ 1387 WREG32(R_000148_MC_FB_LOCATION, 1388 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1389 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1390 r100_mc_resume(rdev, &save); 1391 } 1392 1393 void r300_clock_startup(struct radeon_device *rdev) 1394 { 1395 u32 tmp; 1396 1397 if (radeon_dynclks != -1 && radeon_dynclks) 1398 radeon_legacy_set_clock_gating(rdev, 1); 1399 /* We need to force on some of the block */ 1400 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1401 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1402 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1403 tmp |= S_00000D_FORCE_VAP(1); 1404 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1405 } 1406 1407 static int r300_startup(struct radeon_device *rdev) 1408 { 1409 int r; 1410 1411 /* set common regs */ 1412 r100_set_common_regs(rdev); 1413 /* program mc */ 1414 r300_mc_program(rdev); 1415 /* Resume clock */ 1416 r300_clock_startup(rdev); 1417 /* Initialize GPU configuration (# pipes, ...) */ 1418 r300_gpu_init(rdev); 1419 /* Initialize GART (initialize after TTM so we can allocate 1420 * memory through TTM but finalize after TTM) */ 1421 if (rdev->flags & RADEON_IS_PCIE) { 1422 r = rv370_pcie_gart_enable(rdev); 1423 if (r) 1424 return r; 1425 } 1426 1427 if (rdev->family == CHIP_R300 || 1428 rdev->family == CHIP_R350 || 1429 rdev->family == CHIP_RV350) 1430 r100_enable_bm(rdev); 1431 1432 if (rdev->flags & RADEON_IS_PCI) { 1433 r = r100_pci_gart_enable(rdev); 1434 if (r) 1435 return r; 1436 } 1437 1438 /* allocate wb buffer */ 1439 r = radeon_wb_init(rdev); 1440 if (r) 1441 return r; 1442 1443 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1444 if (r) { 1445 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1446 return r; 1447 } 1448 1449 /* Enable IRQ */ 1450 if (!rdev->irq.installed) { 1451 r = radeon_irq_kms_init(rdev); 1452 if (r) 1453 return r; 1454 } 1455 1456 r100_irq_set(rdev); 1457 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1458 /* 1M ring buffer */ 1459 r = r100_cp_init(rdev, 1024 * 1024); 1460 if (r) { 1461 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1462 return r; 1463 } 1464 1465 r = radeon_ib_pool_init(rdev); 1466 if (r) { 1467 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1468 return r; 1469 } 1470 1471 return 0; 1472 } 1473 1474 int r300_resume(struct radeon_device *rdev) 1475 { 1476 int r; 1477 1478 /* Make sur GART are not working */ 1479 if (rdev->flags & RADEON_IS_PCIE) 1480 rv370_pcie_gart_disable(rdev); 1481 if (rdev->flags & RADEON_IS_PCI) 1482 r100_pci_gart_disable(rdev); 1483 /* Resume clock before doing reset */ 1484 r300_clock_startup(rdev); 1485 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1486 if (radeon_asic_reset(rdev)) { 1487 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1488 RREG32(R_000E40_RBBM_STATUS), 1489 RREG32(R_0007C0_CP_STAT)); 1490 } 1491 /* post */ 1492 radeon_combios_asic_init(rdev->ddev); 1493 /* Resume clock after posting */ 1494 r300_clock_startup(rdev); 1495 /* Initialize surface registers */ 1496 radeon_surface_init(rdev); 1497 1498 rdev->accel_working = true; 1499 r = r300_startup(rdev); 1500 if (r) { 1501 rdev->accel_working = false; 1502 } 1503 return r; 1504 } 1505 1506 int r300_suspend(struct radeon_device *rdev) 1507 { 1508 radeon_pm_suspend(rdev); 1509 r100_cp_disable(rdev); 1510 radeon_wb_disable(rdev); 1511 r100_irq_disable(rdev); 1512 if (rdev->flags & RADEON_IS_PCIE) 1513 rv370_pcie_gart_disable(rdev); 1514 if (rdev->flags & RADEON_IS_PCI) 1515 r100_pci_gart_disable(rdev); 1516 return 0; 1517 } 1518 1519 void r300_fini(struct radeon_device *rdev) 1520 { 1521 radeon_pm_fini(rdev); 1522 r100_cp_fini(rdev); 1523 radeon_wb_fini(rdev); 1524 radeon_ib_pool_fini(rdev); 1525 radeon_gem_fini(rdev); 1526 if (rdev->flags & RADEON_IS_PCIE) 1527 rv370_pcie_gart_fini(rdev); 1528 if (rdev->flags & RADEON_IS_PCI) 1529 r100_pci_gart_fini(rdev); 1530 radeon_agp_fini(rdev); 1531 radeon_irq_kms_fini(rdev); 1532 radeon_fence_driver_fini(rdev); 1533 radeon_bo_fini(rdev); 1534 radeon_atombios_fini(rdev); 1535 kfree(rdev->bios); 1536 rdev->bios = NULL; 1537 } 1538 1539 int r300_init(struct radeon_device *rdev) 1540 { 1541 int r; 1542 1543 /* Disable VGA */ 1544 r100_vga_render_disable(rdev); 1545 /* Initialize scratch registers */ 1546 radeon_scratch_init(rdev); 1547 /* Initialize surface registers */ 1548 radeon_surface_init(rdev); 1549 /* TODO: disable VGA need to use VGA request */ 1550 /* restore some register to sane defaults */ 1551 r100_restore_sanity(rdev); 1552 /* BIOS*/ 1553 if (!radeon_get_bios(rdev)) { 1554 if (ASIC_IS_AVIVO(rdev)) 1555 return -EINVAL; 1556 } 1557 if (rdev->is_atom_bios) { 1558 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1559 return -EINVAL; 1560 } else { 1561 r = radeon_combios_init(rdev); 1562 if (r) 1563 return r; 1564 } 1565 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1566 if (radeon_asic_reset(rdev)) { 1567 dev_warn(rdev->dev, 1568 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1569 RREG32(R_000E40_RBBM_STATUS), 1570 RREG32(R_0007C0_CP_STAT)); 1571 } 1572 /* check if cards are posted or not */ 1573 if (radeon_boot_test_post_card(rdev) == false) 1574 return -EINVAL; 1575 /* Set asic errata */ 1576 r300_errata(rdev); 1577 /* Initialize clocks */ 1578 radeon_get_clock_info(rdev->ddev); 1579 /* initialize AGP */ 1580 if (rdev->flags & RADEON_IS_AGP) { 1581 r = radeon_agp_init(rdev); 1582 if (r) { 1583 radeon_agp_disable(rdev); 1584 } 1585 } 1586 /* initialize memory controller */ 1587 r300_mc_init(rdev); 1588 /* Fence driver */ 1589 r = radeon_fence_driver_init(rdev); 1590 if (r) 1591 return r; 1592 /* Memory manager */ 1593 r = radeon_bo_init(rdev); 1594 if (r) 1595 return r; 1596 if (rdev->flags & RADEON_IS_PCIE) { 1597 r = rv370_pcie_gart_init(rdev); 1598 if (r) 1599 return r; 1600 } 1601 if (rdev->flags & RADEON_IS_PCI) { 1602 r = r100_pci_gart_init(rdev); 1603 if (r) 1604 return r; 1605 } 1606 r300_set_reg_safe(rdev); 1607 1608 /* Initialize power management */ 1609 radeon_pm_init(rdev); 1610 1611 rdev->accel_working = true; 1612 r = r300_startup(rdev); 1613 if (r) { 1614 /* Something went wrong with the accel init, so stop accel */ 1615 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1616 r100_cp_fini(rdev); 1617 radeon_wb_fini(rdev); 1618 radeon_ib_pool_fini(rdev); 1619 radeon_irq_kms_fini(rdev); 1620 if (rdev->flags & RADEON_IS_PCIE) 1621 rv370_pcie_gart_fini(rdev); 1622 if (rdev->flags & RADEON_IS_PCI) 1623 r100_pci_gart_fini(rdev); 1624 radeon_agp_fini(rdev); 1625 rdev->accel_working = false; 1626 } 1627 return 0; 1628 } 1629
Indexes created Sun Sep 21 16:09:51 GMT 2025