1 /* $NetBSD: radeon_r420.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_r420.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $"); 33 34 #include <linux/pci.h> 35 #include <linux/seq_file.h> 36 #include <linux/slab.h> 37 38 #include <drm/drm_debugfs.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_file.h> 41 42 #include "atom.h" 43 #include "r100d.h" 44 #include "r420_reg_safe.h" 45 #include "r420d.h" 46 #include "radeon.h" 47 #include "radeon_asic.h" 48 #include "radeon_reg.h" 49 50 void r420_pm_init_profile(struct radeon_device *rdev) 51 { 52 /* default */ 53 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 54 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 55 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 56 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 57 /* low sh */ 58 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 59 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 60 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 61 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 62 /* mid sh */ 63 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 64 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 65 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 66 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 67 /* high sh */ 68 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 69 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 70 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 71 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 72 /* low mh */ 73 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 74 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 75 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 76 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 77 /* mid mh */ 78 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 79 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 80 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 81 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 82 /* high mh */ 83 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 84 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 85 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 86 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 87 } 88 89 static void r420_set_reg_safe(struct radeon_device *rdev) 90 { 91 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 92 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 93 } 94 95 void r420_pipes_init(struct radeon_device *rdev) 96 { 97 unsigned tmp; 98 unsigned gb_pipe_select; 99 unsigned num_pipes; 100 101 /* GA_ENHANCE workaround TCL deadlock issue */ 102 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 103 (1 << 2) | (1 << 3)); 104 /* add idle wait as per freedesktop.org bug 24041 */ 105 if (r100_gui_wait_for_idle(rdev)) { 106 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 107 } 108 /* get max number of pipes */ 109 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 110 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 111 112 /* SE chips have 1 pipe */ 113 if ((rdev->pdev->device == 0x5e4c) || 114 (rdev->pdev->device == 0x5e4f)) 115 num_pipes = 1; 116 117 rdev->num_gb_pipes = num_pipes; 118 tmp = 0; 119 switch (num_pipes) { 120 default: 121 /* force to 1 pipe */ 122 num_pipes = 1; 123 /* fall through */ 124 case 1: 125 tmp = (0 << 1); 126 break; 127 case 2: 128 tmp = (3 << 1); 129 break; 130 case 3: 131 tmp = (6 << 1); 132 break; 133 case 4: 134 tmp = (7 << 1); 135 break; 136 } 137 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 138 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 139 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 140 WREG32(R300_GB_TILE_CONFIG, tmp); 141 if (r100_gui_wait_for_idle(rdev)) { 142 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 143 } 144 145 tmp = RREG32(R300_DST_PIPE_CONFIG); 146 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 147 148 WREG32(R300_RB2D_DSTCACHE_MODE, 149 RREG32(R300_RB2D_DSTCACHE_MODE) | 150 R300_DC_AUTOFLUSH_ENABLE | 151 R300_DC_DC_DISABLE_IGNORE_PE); 152 153 if (r100_gui_wait_for_idle(rdev)) { 154 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 155 } 156 157 if (rdev->family == CHIP_RV530) { 158 tmp = RREG32(RV530_GB_PIPE_SELECT2); 159 if ((tmp & 3) == 3) 160 rdev->num_z_pipes = 2; 161 else 162 rdev->num_z_pipes = 1; 163 } else 164 rdev->num_z_pipes = 1; 165 166 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 167 rdev->num_gb_pipes, rdev->num_z_pipes); 168 } 169 170 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 171 { 172 unsigned long flags; 173 u32 r; 174 175 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 176 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 177 r = RREG32(R_0001FC_MC_IND_DATA); 178 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 179 return r; 180 } 181 182 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 183 { 184 unsigned long flags; 185 186 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 187 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 188 S_0001F8_MC_IND_WR_EN(1)); 189 WREG32(R_0001FC_MC_IND_DATA, v); 190 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 191 } 192 193 static void r420_debugfs(struct radeon_device *rdev) 194 { 195 if (r100_debugfs_rbbm_init(rdev)) { 196 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 197 } 198 if (r420_debugfs_pipes_info_init(rdev)) { 199 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 200 } 201 } 202 203 static void r420_clock_resume(struct radeon_device *rdev) 204 { 205 u32 sclk_cntl; 206 207 if (radeon_dynclks != -1 && radeon_dynclks) 208 radeon_atom_set_clock_gating(rdev, 1); 209 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 210 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 211 if (rdev->family == CHIP_R420) 212 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 213 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 214 } 215 216 static void r420_cp_errata_init(struct radeon_device *rdev) 217 { 218 int r; 219 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 220 221 /* RV410 and R420 can lock up if CP DMA to host memory happens 222 * while the 2D engine is busy. 223 * 224 * The proper workaround is to queue a RESYNC at the beginning 225 * of the CP init, apparently. 226 */ 227 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 228 r = radeon_ring_lock(rdev, ring, 8); 229 WARN_ON(r); 230 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 231 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 232 radeon_ring_write(ring, 0xDEADBEEF); 233 radeon_ring_unlock_commit(rdev, ring, false); 234 } 235 236 static void r420_cp_errata_fini(struct radeon_device *rdev) 237 { 238 int r; 239 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 240 241 /* Catch the RESYNC we dispatched all the way back, 242 * at the very beginning of the CP init. 243 */ 244 r = radeon_ring_lock(rdev, ring, 8); 245 WARN_ON(r); 246 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 247 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 248 radeon_ring_unlock_commit(rdev, ring, false); 249 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 250 } 251 252 static int r420_startup(struct radeon_device *rdev) 253 { 254 int r; 255 256 /* set common regs */ 257 r100_set_common_regs(rdev); 258 /* program mc */ 259 r300_mc_program(rdev); 260 /* Resume clock */ 261 r420_clock_resume(rdev); 262 /* Initialize GART (initialize after TTM so we can allocate 263 * memory through TTM but finalize after TTM) */ 264 if (rdev->flags & RADEON_IS_PCIE) { 265 r = rv370_pcie_gart_enable(rdev); 266 if (r) 267 return r; 268 } 269 if (rdev->flags & RADEON_IS_PCI) { 270 r = r100_pci_gart_enable(rdev); 271 if (r) 272 return r; 273 } 274 r420_pipes_init(rdev); 275 276 /* allocate wb buffer */ 277 r = radeon_wb_init(rdev); 278 if (r) 279 return r; 280 281 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 282 if (r) { 283 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 284 return r; 285 } 286 287 /* Enable IRQ */ 288 if (!rdev->irq.installed) { 289 r = radeon_irq_kms_init(rdev); 290 if (r) 291 return r; 292 } 293 294 r100_irq_set(rdev); 295 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 296 /* 1M ring buffer */ 297 r = r100_cp_init(rdev, 1024 * 1024); 298 if (r) { 299 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 300 return r; 301 } 302 r420_cp_errata_init(rdev); 303 304 r = radeon_ib_pool_init(rdev); 305 if (r) { 306 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 307 return r; 308 } 309 310 return 0; 311 } 312 313 int r420_resume(struct radeon_device *rdev) 314 { 315 int r; 316 317 /* Make sur GART are not working */ 318 if (rdev->flags & RADEON_IS_PCIE) 319 rv370_pcie_gart_disable(rdev); 320 if (rdev->flags & RADEON_IS_PCI) 321 r100_pci_gart_disable(rdev); 322 /* Resume clock before doing reset */ 323 r420_clock_resume(rdev); 324 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 325 if (radeon_asic_reset(rdev)) { 326 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 327 RREG32(R_000E40_RBBM_STATUS), 328 RREG32(R_0007C0_CP_STAT)); 329 } 330 /* check if cards are posted or not */ 331 if (rdev->is_atom_bios) { 332 atom_asic_init(rdev->mode_info.atom_context); 333 } else { 334 radeon_combios_asic_init(rdev->ddev); 335 } 336 /* Resume clock after posting */ 337 r420_clock_resume(rdev); 338 /* Initialize surface registers */ 339 radeon_surface_init(rdev); 340 341 rdev->accel_working = true; 342 r = r420_startup(rdev); 343 if (r) { 344 rdev->accel_working = false; 345 } 346 return r; 347 } 348 349 int r420_suspend(struct radeon_device *rdev) 350 { 351 radeon_pm_suspend(rdev); 352 r420_cp_errata_fini(rdev); 353 r100_cp_disable(rdev); 354 radeon_wb_disable(rdev); 355 r100_irq_disable(rdev); 356 if (rdev->flags & RADEON_IS_PCIE) 357 rv370_pcie_gart_disable(rdev); 358 if (rdev->flags & RADEON_IS_PCI) 359 r100_pci_gart_disable(rdev); 360 return 0; 361 } 362 363 void r420_fini(struct radeon_device *rdev) 364 { 365 radeon_pm_fini(rdev); 366 r100_cp_fini(rdev); 367 radeon_wb_fini(rdev); 368 radeon_ib_pool_fini(rdev); 369 radeon_gem_fini(rdev); 370 if (rdev->flags & RADEON_IS_PCIE) 371 rv370_pcie_gart_fini(rdev); 372 if (rdev->flags & RADEON_IS_PCI) 373 r100_pci_gart_fini(rdev); 374 radeon_agp_fini(rdev); 375 radeon_irq_kms_fini(rdev); 376 radeon_fence_driver_fini(rdev); 377 radeon_bo_fini(rdev); 378 if (rdev->is_atom_bios) { 379 radeon_atombios_fini(rdev); 380 } else { 381 radeon_combios_fini(rdev); 382 } 383 kfree(rdev->bios); 384 rdev->bios = NULL; 385 } 386 387 int r420_init(struct radeon_device *rdev) 388 { 389 int r; 390 391 /* Initialize scratch registers */ 392 radeon_scratch_init(rdev); 393 /* Initialize surface registers */ 394 radeon_surface_init(rdev); 395 /* TODO: disable VGA need to use VGA request */ 396 /* restore some register to sane defaults */ 397 r100_restore_sanity(rdev); 398 /* BIOS*/ 399 if (!radeon_get_bios(rdev)) { 400 if (ASIC_IS_AVIVO(rdev)) 401 return -EINVAL; 402 } 403 if (rdev->is_atom_bios) { 404 r = radeon_atombios_init(rdev); 405 if (r) { 406 return r; 407 } 408 } else { 409 r = radeon_combios_init(rdev); 410 if (r) { 411 return r; 412 } 413 } 414 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 415 if (radeon_asic_reset(rdev)) { 416 dev_warn(rdev->dev, 417 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 418 RREG32(R_000E40_RBBM_STATUS), 419 RREG32(R_0007C0_CP_STAT)); 420 } 421 /* check if cards are posted or not */ 422 if (radeon_boot_test_post_card(rdev) == false) 423 return -EINVAL; 424 425 /* Initialize clocks */ 426 radeon_get_clock_info(rdev->ddev); 427 /* initialize AGP */ 428 if (rdev->flags & RADEON_IS_AGP) { 429 r = radeon_agp_init(rdev); 430 if (r) { 431 radeon_agp_disable(rdev); 432 } 433 } 434 /* initialize memory controller */ 435 r300_mc_init(rdev); 436 r420_debugfs(rdev); 437 /* Fence driver */ 438 r = radeon_fence_driver_init(rdev); 439 if (r) { 440 return r; 441 } 442 /* Memory manager */ 443 r = radeon_bo_init(rdev); 444 if (r) { 445 return r; 446 } 447 if (rdev->family == CHIP_R420) 448 r100_enable_bm(rdev); 449 450 if (rdev->flags & RADEON_IS_PCIE) { 451 r = rv370_pcie_gart_init(rdev); 452 if (r) 453 return r; 454 } 455 if (rdev->flags & RADEON_IS_PCI) { 456 r = r100_pci_gart_init(rdev); 457 if (r) 458 return r; 459 } 460 r420_set_reg_safe(rdev); 461 462 /* Initialize power management */ 463 radeon_pm_init(rdev); 464 465 rdev->accel_working = true; 466 r = r420_startup(rdev); 467 if (r) { 468 /* Somethings want wront with the accel init stop accel */ 469 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 470 r100_cp_fini(rdev); 471 radeon_wb_fini(rdev); 472 radeon_ib_pool_fini(rdev); 473 radeon_irq_kms_fini(rdev); 474 if (rdev->flags & RADEON_IS_PCIE) 475 rv370_pcie_gart_fini(rdev); 476 if (rdev->flags & RADEON_IS_PCI) 477 r100_pci_gart_fini(rdev); 478 radeon_agp_fini(rdev); 479 rdev->accel_working = false; 480 } 481 return 0; 482 } 483 484 /* 485 * Debugfs info 486 */ 487 #if defined(CONFIG_DEBUG_FS) 488 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 489 { 490 struct drm_info_node *node = (struct drm_info_node *) m->private; 491 struct drm_device *dev = node->minor->dev; 492 struct radeon_device *rdev = dev->dev_private; 493 uint32_t tmp; 494 495 tmp = RREG32(R400_GB_PIPE_SELECT); 496 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 497 tmp = RREG32(R300_GB_TILE_CONFIG); 498 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 499 tmp = RREG32(R300_DST_PIPE_CONFIG); 500 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 501 return 0; 502 } 503 504 static struct drm_info_list r420_pipes_info_list[] = { 505 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 506 }; 507 #endif 508 509 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 510 { 511 #if defined(CONFIG_DEBUG_FS) 512 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 513 #else 514 return 0; 515 #endif 516 } 517
Indexes created Sat Sep 20 22:09:52 GMT 2025