1 /* $NetBSD: reg.h,v 1.13 2019/04/16 12:25:17 skrll Exp $ */ 2 3 /* $OpenBSD: reg.h,v 1.7 2000/06/15 17:00:37 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1998-2004 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 /* 31 * Copyright (c) 1990,1994 The University of Utah and 32 * the Computer Systems Laboratory at the University of Utah (CSL). 33 * All rights reserved. 34 * 35 * Permission to use, copy, modify and distribute this software is hereby 36 * granted provided that (1) source code retains these copyright, permission, 37 * and disclaimer notices, and (2) redistributions including binaries 38 * reproduce the notices in supporting documentation, and (3) all advertising 39 * materials mentioning features or use of this software display the following 40 * acknowledgement: ``This product includes software developed by the 41 * Computer Systems Laboratory at the University of Utah.'' 42 * 43 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 44 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 45 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * CSL requests users of this software to return to csl-dist (at) cs.utah.edu any 48 * improvements that they make and grant CSL redistribution rights. 49 * 50 * Utah $Hdr: regs.h 1.6 94/12/14$ 51 * Author: Bob Wheeler, University of Utah CSL 52 */ 53 54 #ifndef _HPPA_REG_H_ 55 #define _HPPA_REG_H_ 56 57 /* 58 * constants for registers for use with the following routines: 59 * 60 * void mtctl(reg, value) - move to control register 61 * int mfctl(reg) - move from control register 62 * int mtsp(sreg, value) - move to space register 63 * int mfsr(sreg) - move from space register 64 */ 65 66 #define CR_RCTR 0 67 #define CR_PIDR1 8 68 #define CR_PIDR2 9 69 #define CR_CCR 10 70 #define CR_SAR 11 71 #define CR_PIDR3 12 72 #define CR_PIDR4 13 73 #define CR_IVA 14 74 #define CR_EIEM 15 75 #define CR_ITMR 16 76 #define CR_PCSQ 17 77 #define CR_PCOQ 18 78 #define CR_IIR 19 79 #define CR_ISR 20 80 #define CR_IOR 21 81 #define CR_IPSW 22 82 #define CR_EIRR 23 83 84 /* Temporary control registers */ 85 #ifdef MULTIPROCESSOR 86 #define CR_CURCPU 24 /* tr0: curcpu */ 87 #else 88 #define CR_CURLWP 24 /* tr0: curlwp */ 89 #endif 90 #define CR_VTOP 25 /* tr1: virt to phys table address */ 91 #define CR_TR2 26 /* tr2: temporary */ 92 #define CR_TLS 27 /* tr3: thread local storage pointer */ 93 #define CR_HVTP 28 /* tr4: faulted HVT slot ptr on LC cpus */ 94 #define CR_TR5 29 /* tr5: emu / TLB_STATS_{PRE,AFT} */ 95 #define CR_FPPADDR 30 /* tr6: paddr of FP regs of curlwp */ 96 #define CR_TR7 31 /* tr7: trap temporary register */ 97 98 /* 99 * Diagnostic registers and bit positions 100 */ 101 #define DR_CPUCFG 0 102 103 #define DR0_PCXS_DHPMC 10 /* r/c D-cache error flag */ 104 #define DR0_PCXS_ILPMC 14 /* r/c I-cache error flag */ 105 #define DR0_PCXS_EQWSTO 16 /* r/w enable quad-word stores */ 106 #define DR0_PCXS_IHE 18 /* r/w I-cache sid hash enable */ 107 #define DR0_PCXS_DOMAIN 19 108 #define DR0_PCXS_DHE 20 /* r/w D-cache sid hash enable */ 109 110 #define DR0_PCXT_DHPMC 10 /* r/c L1 D-cache error flag */ 111 #define DR0_PCXT_ILPMC 14 /* r/c L1 I-cache error flag */ 112 #define DR0_PCXT_IHE 18 /* r/w I-cache sid hash enable */ 113 #define DR0_PCXT_DHE 20 /* r/w D-cache sid hash enable */ 114 115 /* Bits in CPU Diagnose Register 0 */ 116 #define DR0_PCXL_L2IHPMC 6 /* r/c L2 I-cache error flag */ 117 #define DR0_PCXL_L2IHPMC_DIS 7 /* r/w L2 I-cache hpmc disable mask */ 118 #define DR0_PCXL_L2DHPMC 8 /* r/c L2 D-cache error flag */ 119 #define DR0_PCXL_L2DHPMC_DIS 9 /* r/w L2 D-cache hpmc disable mask */ 120 #define DR0_PCXL_L1IHPMC 10 /* r/c L1 I-cache error flag */ 121 #define DR0_PCXL_L1IHPMC_DIS 11 /* r/w L1 I-cache hpmc disable mask */ 122 #define DR0_PCXL_L2PARERR 15 /* r/c L2 Cache parity error (4 bit) */ 123 #define DR0_PCXL_STORE0 16 /* r/w scratch space */ 124 #define DR0_PCXL_PFMASK 17 /* r/w power-fail trap mask */ 125 #define DR0_PCXL_STORE1 18 /* r/w scratch */ 126 #define DR0_PCXL_FASTMODE 19 /* r 0-fast, 1-slow */ 127 #define DR0_PCXL_ISTRM_EN 20 /* r/w I-cache streaming enable */ 128 #define DR0_PCXL_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */ 129 #define DR0_PCXL_ENDIAN 23 /* r/w little endian traps */ 130 #define DR0_PCXL_SOU_EN 24 /* r/w stall-on-use on dc misses */ 131 #define DR0_PCXL_SHINT_EN 25 /* r/w no-fill on miss store hints */ 132 #define DR0_PCXL_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */ 133 #define DR0_PCXL_L2DHASH_EN 27 /* r/w L2 D-cache hash enable */ 134 #define DR0_PCXL_L2IHASH_EN 28 /* r/w L2 I-cache hash enable */ 135 #define DR0_PCXL_L1ICACHE_EN 29 /* r/w L1 I-cache enable */ 136 #define DR0_PCXL_HIT 30 /* r Diag cache read hit indication */ 137 #define DR0_PCXL_PARERR 31 /* r Diag cache read parity error */ 138 139 /* Bits in CPU Diagnose Register 25 */ 140 #define DR25_PCXL_POWFAIL 31 /* r set to 0 by HW on PWR fail */ 141 142 #define DR0_PCXL2_L1DHPMC 8 /* r/c L1 D-cache error flag */ 143 #define DR0_PCXL2_L1DHPMC_DIS 9 /* r/w L1 D-cache hpmc disable */ 144 #define DR0_PCXL2_L2DHPMC 10 /* r/c L1 I-cache error flag */ 145 #define DR0_PCXL2_L2DHPMC_DIS 11 /* r/w L1 I-cache hpmc disable */ 146 #define DR0_PCXL2_SCRATCH 12 /* r/w scratch register */ 147 #define DR0_PCXL2_ACCEL_IO 13 /* /w enable accel IO writes */ 148 #define DR0_PCXL2_STORE0 16 /* r/w scratch space */ 149 #define DR0_PCXL2_PFMASK 17 /* r/w power-fail trap mask */ 150 #define DR0_PCXL2_STORE1 18 /* r/w scratch */ 151 #define DR0_PCXL2_DCSAFE 19 /* r/w serialize all data cache hangs */ 152 #define DR0_PCXL2_ISTRM_EN 20 /* r/w I-cache streaming enable */ 153 #define DR0_PCXL2_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */ 154 #define DR0_PCXL2_ENDIAN 23 /* r/w little endian traps */ 155 #define DR0_PCXL2_SOU_EN 24 /* r/w stall-on-use on dc misses */ 156 #define DR0_PCXL2_SHINT_EN 25 /* r/w no-fill on miss store hints */ 157 #define DR0_PCXL2_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */ 158 #define DR0_PCXL2_LMIN_EN 27 /* r/w minor ill insn traps on LIH */ 159 #define DR0_PCXL2_RMIN_EN 28 /* r/w major ill insn traps on RIH */ 160 #define DR0_PCXL2_L1CACHE_EN 29 /* r/w L1 I-cache enable */ 161 162 #define DR_DTLB 8 163 164 #define DR_ITLB 9 165 166 #define DR0_PCXL2_HTLB_ADDR 24 /* page address of the htlb */ 167 #define DR0_PCXL2_HTLB_CFG 25 /* htlb config */ 168 #define DR0_PCXL2_HTLB_P 0 /* r latches power fail signal */ 169 #define DR0_PCXL2_HTLB_MASK 19 /* w 12bit mask of the hash */ 170 #define DR0_PCXL2_HTLB_FP 26 /* r/w 3bit FP delay */ 171 #define DR0_PCXL2_HTLB_I 28 /* r/w disable ITLB htlb lookup */ 172 #define DR0_PCXL2_HTLB_U 29 /* r/w set cr28 only if tag nomatch */ 173 #define DR0_PCXL2_HTLB_N 30 /* r/w set cr28 from w3 or w7 (0) */ 174 #define DR0_PCXL2_HTLB_D 31 /* r/w disable DTLB htlb lookup */ 175 176 #define DR_ITLB_SIZE_1 24 177 #define DR_ITLB_SIZE_0 25 178 179 #define DR_DTLB_SIZE_1 26 180 #define DR_DTLB_SIZE_0 27 181 182 #define CCR_MASK 0xff 183 184 #define HPPA_NREGS (32) 185 #define HPPA_NFPREGS (33) /* 33rd is used for r0 in fpemul */ 186 187 #ifndef __ASSEMBLER__ 188 189 struct reg { 190 uint32_t r_regs[HPPA_NREGS]; /* r0 is psw */ 191 192 uint32_t r_sar; 193 194 uint32_t r_pcsqh; 195 uint32_t r_pcsqt; 196 uint32_t r_pcoqh; 197 uint32_t r_pcoqt; 198 199 uint32_t r_sr0; 200 uint32_t r_sr1; 201 uint32_t r_sr2; 202 uint32_t r_sr3; 203 uint32_t r_sr4; 204 uint32_t r_sr5; /* !mcontext */ 205 uint32_t r_sr6; /* !mcontext */ 206 uint32_t r_sr7; /* !mcontext */ 207 208 uint32_t r_cr26; 209 uint32_t r_cr27; 210 }; 211 212 struct fpreg { 213 uint64_t fpr_regs[HPPA_NFPREGS]; 214 }; 215 #endif /* !__ASSEMBLER__ */ 216 217 #endif /* _HPPA_REG_H_ */ 218
Indexes created Sat Sep 20 22:09:52 GMT 2025