1 /* $NetBSD: radeon_atombios_crtc.c,v 1.3 2021/12/19 11:08:32 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_atombios_crtc.c,v 1.3 2021/12/19 11:08:32 riastradh Exp $"); 31 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_fb_helper.h> 34 #include <drm/drm_fixed.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_vblank.h> 37 #include <drm/radeon_drm.h> 38 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "atom.h" 42 #include "atom-bits.h" 43 44 static void atombios_overscan_setup(struct drm_crtc *crtc, 45 struct drm_display_mode *mode, 46 struct drm_display_mode *adjusted_mode) 47 { 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 51 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 52 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 53 int a1, a2; 54 55 memset(&args, 0, sizeof(args)); 56 57 args.ucCRTC = radeon_crtc->crtc_id; 58 59 switch (radeon_crtc->rmx_type) { 60 case RMX_CENTER: 61 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 62 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 63 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 64 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 65 break; 66 case RMX_ASPECT: 67 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 68 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 69 70 if (a1 > a2) { 71 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 72 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 73 } else if (a2 > a1) { 74 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 75 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 76 } 77 break; 78 case RMX_FULL: 79 default: 80 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 81 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 82 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 83 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 84 break; 85 } 86 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 87 } 88 89 static void atombios_scaler_setup(struct drm_crtc *crtc) 90 { 91 struct drm_device *dev = crtc->dev; 92 struct radeon_device *rdev = dev->dev_private; 93 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 94 ENABLE_SCALER_PS_ALLOCATION args; 95 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 96 struct radeon_encoder *radeon_encoder = 97 to_radeon_encoder(radeon_crtc->encoder); 98 /* fixme - fill in enc_priv for atom dac */ 99 enum radeon_tv_std tv_std = TV_STD_NTSC; 100 bool is_tv = false, is_cv = false; 101 102 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 103 return; 104 105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 107 tv_std = tv_dac->tv_std; 108 is_tv = true; 109 } 110 111 memset(&args, 0, sizeof(args)); 112 113 args.ucScaler = radeon_crtc->crtc_id; 114 115 if (is_tv) { 116 switch (tv_std) { 117 case TV_STD_NTSC: 118 default: 119 args.ucTVStandard = ATOM_TV_NTSC; 120 break; 121 case TV_STD_PAL: 122 args.ucTVStandard = ATOM_TV_PAL; 123 break; 124 case TV_STD_PAL_M: 125 args.ucTVStandard = ATOM_TV_PALM; 126 break; 127 case TV_STD_PAL_60: 128 args.ucTVStandard = ATOM_TV_PAL60; 129 break; 130 case TV_STD_NTSC_J: 131 args.ucTVStandard = ATOM_TV_NTSCJ; 132 break; 133 case TV_STD_SCART_PAL: 134 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 135 break; 136 case TV_STD_SECAM: 137 args.ucTVStandard = ATOM_TV_SECAM; 138 break; 139 case TV_STD_PAL_CN: 140 args.ucTVStandard = ATOM_TV_PALCN; 141 break; 142 } 143 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 144 } else if (is_cv) { 145 args.ucTVStandard = ATOM_TV_CV; 146 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 147 } else { 148 switch (radeon_crtc->rmx_type) { 149 case RMX_FULL: 150 args.ucEnable = ATOM_SCALER_EXPANSION; 151 break; 152 case RMX_CENTER: 153 args.ucEnable = ATOM_SCALER_CENTER; 154 break; 155 case RMX_ASPECT: 156 args.ucEnable = ATOM_SCALER_EXPANSION; 157 break; 158 default: 159 if (ASIC_IS_AVIVO(rdev)) 160 args.ucEnable = ATOM_SCALER_DISABLE; 161 else 162 args.ucEnable = ATOM_SCALER_CENTER; 163 break; 164 } 165 } 166 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 167 if ((is_tv || is_cv) 168 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 169 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 170 } 171 } 172 173 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 174 { 175 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 176 struct drm_device *dev = crtc->dev; 177 struct radeon_device *rdev = dev->dev_private; 178 int index = 179 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 180 ENABLE_CRTC_PS_ALLOCATION args; 181 182 memset(&args, 0, sizeof(args)); 183 184 args.ucCRTC = radeon_crtc->crtc_id; 185 args.ucEnable = lock; 186 187 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 188 } 189 190 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 191 { 192 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 193 struct drm_device *dev = crtc->dev; 194 struct radeon_device *rdev = dev->dev_private; 195 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 196 ENABLE_CRTC_PS_ALLOCATION args; 197 198 memset(&args, 0, sizeof(args)); 199 200 args.ucCRTC = radeon_crtc->crtc_id; 201 args.ucEnable = state; 202 203 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 204 } 205 206 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 207 { 208 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 209 struct drm_device *dev = crtc->dev; 210 struct radeon_device *rdev = dev->dev_private; 211 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 212 ENABLE_CRTC_PS_ALLOCATION args; 213 214 memset(&args, 0, sizeof(args)); 215 216 args.ucCRTC = radeon_crtc->crtc_id; 217 args.ucEnable = state; 218 219 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 220 } 221 222 static const u32 vga_control_regs[6] = 223 { 224 AVIVO_D1VGA_CONTROL, 225 AVIVO_D2VGA_CONTROL, 226 EVERGREEN_D3VGA_CONTROL, 227 EVERGREEN_D4VGA_CONTROL, 228 EVERGREEN_D5VGA_CONTROL, 229 EVERGREEN_D6VGA_CONTROL, 230 }; 231 232 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 233 { 234 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 235 struct drm_device *dev = crtc->dev; 236 struct radeon_device *rdev = dev->dev_private; 237 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 238 BLANK_CRTC_PS_ALLOCATION args; 239 u32 vga_control = 0; 240 241 memset(&args, 0, sizeof(args)); 242 243 if (ASIC_IS_DCE8(rdev)) { 244 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); 245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); 246 } 247 248 args.ucCRTC = radeon_crtc->crtc_id; 249 args.ucBlanking = state; 250 251 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 252 253 if (ASIC_IS_DCE8(rdev)) 254 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); 255 } 256 257 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 258 { 259 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 260 struct drm_device *dev = crtc->dev; 261 struct radeon_device *rdev = dev->dev_private; 262 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 263 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 264 265 memset(&args, 0, sizeof(args)); 266 267 args.ucDispPipeId = radeon_crtc->crtc_id; 268 args.ucEnable = state; 269 270 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 271 } 272 273 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 274 { 275 struct drm_device *dev = crtc->dev; 276 struct radeon_device *rdev = dev->dev_private; 277 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 278 279 switch (mode) { 280 case DRM_MODE_DPMS_ON: 281 radeon_crtc->enabled = true; 282 atombios_enable_crtc(crtc, ATOM_ENABLE); 283 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 284 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 285 atombios_blank_crtc(crtc, ATOM_DISABLE); 286 if (dev->num_crtcs > radeon_crtc->crtc_id) 287 drm_crtc_vblank_on(crtc); 288 radeon_crtc_load_lut(crtc); 289 break; 290 case DRM_MODE_DPMS_STANDBY: 291 case DRM_MODE_DPMS_SUSPEND: 292 case DRM_MODE_DPMS_OFF: 293 if (dev->num_crtcs > radeon_crtc->crtc_id) 294 drm_crtc_vblank_off(crtc); 295 if (radeon_crtc->enabled) 296 atombios_blank_crtc(crtc, ATOM_ENABLE); 297 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 298 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 299 atombios_enable_crtc(crtc, ATOM_DISABLE); 300 radeon_crtc->enabled = false; 301 break; 302 } 303 /* adjust pm to dpms */ 304 radeon_pm_compute_clocks(rdev); 305 } 306 307 static void 308 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 309 struct drm_display_mode *mode) 310 { 311 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 312 struct drm_device *dev = crtc->dev; 313 struct radeon_device *rdev = dev->dev_private; 314 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 315 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 316 u16 misc = 0; 317 318 memset(&args, 0, sizeof(args)); 319 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 320 args.usH_Blanking_Time = 321 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 322 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 323 args.usV_Blanking_Time = 324 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 325 args.usH_SyncOffset = 326 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 327 args.usH_SyncWidth = 328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 329 args.usV_SyncOffset = 330 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 331 args.usV_SyncWidth = 332 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 333 args.ucH_Border = radeon_crtc->h_border; 334 args.ucV_Border = radeon_crtc->v_border; 335 336 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 337 misc |= ATOM_VSYNC_POLARITY; 338 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 339 misc |= ATOM_HSYNC_POLARITY; 340 if (mode->flags & DRM_MODE_FLAG_CSYNC) 341 misc |= ATOM_COMPOSITESYNC; 342 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 343 misc |= ATOM_INTERLACE; 344 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 345 misc |= ATOM_DOUBLE_CLOCK_MODE; 346 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 347 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 348 349 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 350 args.ucCRTC = radeon_crtc->crtc_id; 351 352 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 353 } 354 355 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 356 struct drm_display_mode *mode) 357 { 358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 359 struct drm_device *dev = crtc->dev; 360 struct radeon_device *rdev = dev->dev_private; 361 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 362 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 363 u16 misc = 0; 364 365 memset(&args, 0, sizeof(args)); 366 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 367 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 368 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 369 args.usH_SyncWidth = 370 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 371 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 372 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 373 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 374 args.usV_SyncWidth = 375 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 376 377 args.ucOverscanRight = radeon_crtc->h_border; 378 args.ucOverscanLeft = radeon_crtc->h_border; 379 args.ucOverscanBottom = radeon_crtc->v_border; 380 args.ucOverscanTop = radeon_crtc->v_border; 381 382 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 383 misc |= ATOM_VSYNC_POLARITY; 384 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 385 misc |= ATOM_HSYNC_POLARITY; 386 if (mode->flags & DRM_MODE_FLAG_CSYNC) 387 misc |= ATOM_COMPOSITESYNC; 388 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 389 misc |= ATOM_INTERLACE; 390 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 391 misc |= ATOM_DOUBLE_CLOCK_MODE; 392 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 393 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 394 395 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 396 args.ucCRTC = radeon_crtc->crtc_id; 397 398 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 399 } 400 401 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 402 { 403 u32 ss_cntl; 404 405 if (ASIC_IS_DCE4(rdev)) { 406 switch (pll_id) { 407 case ATOM_PPLL1: 408 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 409 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 410 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 411 break; 412 case ATOM_PPLL2: 413 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 414 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 415 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 416 break; 417 case ATOM_DCPLL: 418 case ATOM_PPLL_INVALID: 419 return; 420 } 421 } else if (ASIC_IS_AVIVO(rdev)) { 422 switch (pll_id) { 423 case ATOM_PPLL1: 424 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 425 ss_cntl &= ~1; 426 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 427 break; 428 case ATOM_PPLL2: 429 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 430 ss_cntl &= ~1; 431 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 432 break; 433 case ATOM_DCPLL: 434 case ATOM_PPLL_INVALID: 435 return; 436 } 437 } 438 } 439 440 441 union atom_enable_ss { 442 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 443 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 444 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 445 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 446 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 447 }; 448 449 static void atombios_crtc_program_ss(struct radeon_device *rdev, 450 int enable, 451 int pll_id, 452 int crtc_id, 453 struct radeon_atom_ss *ss) 454 { 455 unsigned i; 456 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 457 union atom_enable_ss args; 458 459 if (enable) { 460 /* Don't mess with SS if percentage is 0 or external ss. 461 * SS is already disabled previously, and disabling it 462 * again can cause display problems if the pll is already 463 * programmed. 464 */ 465 if (ss->percentage == 0) 466 return; 467 if (ss->type & ATOM_EXTERNAL_SS_MASK) 468 return; 469 } else { 470 for (i = 0; i < rdev->num_crtc; i++) { 471 if (rdev->mode_info.crtcs[i] && 472 rdev->mode_info.crtcs[i]->enabled && 473 i != crtc_id && 474 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 475 /* one other crtc is using this pll don't turn 476 * off spread spectrum as it might turn off 477 * display on active crtc 478 */ 479 return; 480 } 481 } 482 } 483 484 memset(&args, 0, sizeof(args)); 485 486 if (ASIC_IS_DCE5(rdev)) { 487 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 488 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 489 switch (pll_id) { 490 case ATOM_PPLL1: 491 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 492 break; 493 case ATOM_PPLL2: 494 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 495 break; 496 case ATOM_DCPLL: 497 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 498 break; 499 case ATOM_PPLL_INVALID: 500 return; 501 } 502 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 503 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 504 args.v3.ucEnable = enable; 505 } else if (ASIC_IS_DCE4(rdev)) { 506 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 507 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 508 switch (pll_id) { 509 case ATOM_PPLL1: 510 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 511 break; 512 case ATOM_PPLL2: 513 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 514 break; 515 case ATOM_DCPLL: 516 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 517 break; 518 case ATOM_PPLL_INVALID: 519 return; 520 } 521 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 522 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 523 args.v2.ucEnable = enable; 524 } else if (ASIC_IS_DCE3(rdev)) { 525 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 526 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 527 args.v1.ucSpreadSpectrumStep = ss->step; 528 args.v1.ucSpreadSpectrumDelay = ss->delay; 529 args.v1.ucSpreadSpectrumRange = ss->range; 530 args.v1.ucPpll = pll_id; 531 args.v1.ucEnable = enable; 532 } else if (ASIC_IS_AVIVO(rdev)) { 533 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 534 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 535 atombios_disable_ss(rdev, pll_id); 536 return; 537 } 538 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 539 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 540 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 541 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 542 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 543 args.lvds_ss_2.ucEnable = enable; 544 } else { 545 if (enable == ATOM_DISABLE) { 546 atombios_disable_ss(rdev, pll_id); 547 return; 548 } 549 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 550 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 551 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 552 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 553 args.lvds_ss.ucEnable = enable; 554 } 555 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 556 } 557 558 union adjust_pixel_clock { 559 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 560 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 561 }; 562 563 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 564 struct drm_display_mode *mode) 565 { 566 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 567 struct drm_device *dev = crtc->dev; 568 struct radeon_device *rdev = dev->dev_private; 569 struct drm_encoder *encoder = radeon_crtc->encoder; 570 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 571 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 572 u32 adjusted_clock = mode->clock; 573 int encoder_mode = atombios_get_encoder_mode(encoder); 574 u32 dp_clock = mode->clock; 575 u32 clock = mode->clock; 576 int bpc = radeon_crtc->bpc; 577 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 578 579 /* reset the pll flags */ 580 radeon_crtc->pll_flags = 0; 581 582 if (ASIC_IS_AVIVO(rdev)) { 583 if ((rdev->family == CHIP_RS600) || 584 (rdev->family == CHIP_RS690) || 585 (rdev->family == CHIP_RS740)) 586 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 587 RADEON_PLL_PREFER_CLOSEST_LOWER); 588 589 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 590 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 591 else 592 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 593 594 if (rdev->family < CHIP_RV770) 595 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 596 /* use frac fb div on APUs */ 597 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 598 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 599 /* use frac fb div on RS780/RS880 */ 600 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 601 && !radeon_crtc->ss_enabled) 602 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 603 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 604 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 605 } else { 606 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 607 608 if (mode->clock > 200000) /* range limits??? */ 609 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 610 else 611 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 612 } 613 614 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 615 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 616 if (connector) { 617 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 618 struct radeon_connector_atom_dig *dig_connector = 619 radeon_connector->con_priv; 620 621 dp_clock = dig_connector->dp_clock; 622 } 623 } 624 625 if (radeon_encoder->is_mst_encoder) { 626 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; 627 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; 628 629 dp_clock = dig_connector->dp_clock; 630 } 631 632 /* use recommended ref_div for ss */ 633 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 634 if (radeon_crtc->ss_enabled) { 635 if (radeon_crtc->ss.refdiv) { 636 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 637 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 638 if (ASIC_IS_AVIVO(rdev) && 639 rdev->family != CHIP_RS780 && 640 rdev->family != CHIP_RS880) 641 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 642 } 643 } 644 } 645 646 if (ASIC_IS_AVIVO(rdev)) { 647 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 648 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 649 adjusted_clock = mode->clock * 2; 650 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 651 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 652 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 653 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 654 } else { 655 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 656 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 657 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 658 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 659 } 660 661 /* adjust pll for deep color modes */ 662 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 663 switch (bpc) { 664 case 8: 665 default: 666 break; 667 case 10: 668 clock = (clock * 5) / 4; 669 break; 670 case 12: 671 clock = (clock * 3) / 2; 672 break; 673 case 16: 674 clock = clock * 2; 675 break; 676 } 677 } 678 679 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 680 * accordingly based on the encoder/transmitter to work around 681 * special hw requirements. 682 */ 683 if (ASIC_IS_DCE3(rdev)) { 684 union adjust_pixel_clock args; 685 u8 frev, crev; 686 int index; 687 688 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 689 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 690 &crev)) 691 return adjusted_clock; 692 693 memset(&args, 0, sizeof(args)); 694 695 switch (frev) { 696 case 1: 697 switch (crev) { 698 case 1: 699 case 2: 700 args.v1.usPixelClock = cpu_to_le16(clock / 10); 701 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 702 args.v1.ucEncodeMode = encoder_mode; 703 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 704 args.v1.ucConfig |= 705 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 706 707 atom_execute_table(rdev->mode_info.atom_context, 708 index, (uint32_t *)&args); 709 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 710 break; 711 case 3: 712 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); 713 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 714 args.v3.sInput.ucEncodeMode = encoder_mode; 715 args.v3.sInput.ucDispPllConfig = 0; 716 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 717 args.v3.sInput.ucDispPllConfig |= 718 DISPPLL_CONFIG_SS_ENABLE; 719 if (ENCODER_MODE_IS_DP(encoder_mode)) { 720 args.v3.sInput.ucDispPllConfig |= 721 DISPPLL_CONFIG_COHERENT_MODE; 722 /* 16200 or 27000 */ 723 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 724 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 725 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 726 if (dig->coherent_mode) 727 args.v3.sInput.ucDispPllConfig |= 728 DISPPLL_CONFIG_COHERENT_MODE; 729 if (is_duallink) 730 args.v3.sInput.ucDispPllConfig |= 731 DISPPLL_CONFIG_DUAL_LINK; 732 } 733 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 734 ENCODER_OBJECT_ID_NONE) 735 args.v3.sInput.ucExtTransmitterID = 736 radeon_encoder_get_dp_bridge_encoder_id(encoder); 737 else 738 args.v3.sInput.ucExtTransmitterID = 0; 739 740 atom_execute_table(rdev->mode_info.atom_context, 741 index, (uint32_t *)&args); 742 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 743 if (args.v3.sOutput.ucRefDiv) { 744 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 745 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 746 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 747 } 748 if (args.v3.sOutput.ucPostDiv) { 749 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 750 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 751 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 752 } 753 break; 754 default: 755 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 756 return adjusted_clock; 757 } 758 break; 759 default: 760 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 761 return adjusted_clock; 762 } 763 } 764 return adjusted_clock; 765 } 766 767 union set_pixel_clock { 768 SET_PIXEL_CLOCK_PS_ALLOCATION base; 769 PIXEL_CLOCK_PARAMETERS v1; 770 PIXEL_CLOCK_PARAMETERS_V2 v2; 771 PIXEL_CLOCK_PARAMETERS_V3 v3; 772 PIXEL_CLOCK_PARAMETERS_V5 v5; 773 PIXEL_CLOCK_PARAMETERS_V6 v6; 774 }; 775 776 /* on DCE5, make sure the voltage is high enough to support the 777 * required disp clk. 778 */ 779 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 780 u32 dispclk) 781 { 782 u8 frev, crev; 783 int index; 784 union set_pixel_clock args; 785 786 memset(&args, 0, sizeof(args)); 787 788 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 789 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 790 &crev)) 791 return; 792 793 switch (frev) { 794 case 1: 795 switch (crev) { 796 case 5: 797 /* if the default dcpll clock is specified, 798 * SetPixelClock provides the dividers 799 */ 800 args.v5.ucCRTC = ATOM_CRTC_INVALID; 801 args.v5.usPixelClock = cpu_to_le16(dispclk); 802 args.v5.ucPpll = ATOM_DCPLL; 803 break; 804 case 6: 805 /* if the default dcpll clock is specified, 806 * SetPixelClock provides the dividers 807 */ 808 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 809 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 810 args.v6.ucPpll = ATOM_EXT_PLL1; 811 else if (ASIC_IS_DCE6(rdev)) 812 args.v6.ucPpll = ATOM_PPLL0; 813 else 814 args.v6.ucPpll = ATOM_DCPLL; 815 break; 816 default: 817 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 818 return; 819 } 820 break; 821 default: 822 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 823 return; 824 } 825 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 826 } 827 828 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 829 u32 crtc_id, 830 int pll_id, 831 u32 encoder_mode, 832 u32 encoder_id, 833 u32 clock, 834 u32 ref_div, 835 u32 fb_div, 836 u32 frac_fb_div, 837 u32 post_div, 838 int bpc, 839 bool ss_enabled, 840 struct radeon_atom_ss *ss) 841 { 842 struct drm_device *dev = crtc->dev; 843 struct radeon_device *rdev = dev->dev_private; 844 u8 frev, crev; 845 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 846 union set_pixel_clock args; 847 848 memset(&args, 0, sizeof(args)); 849 850 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 851 &crev)) 852 return; 853 854 switch (frev) { 855 case 1: 856 switch (crev) { 857 case 1: 858 if (clock == ATOM_DISABLE) 859 return; 860 args.v1.usPixelClock = cpu_to_le16(clock / 10); 861 args.v1.usRefDiv = cpu_to_le16(ref_div); 862 args.v1.usFbDiv = cpu_to_le16(fb_div); 863 args.v1.ucFracFbDiv = frac_fb_div; 864 args.v1.ucPostDiv = post_div; 865 args.v1.ucPpll = pll_id; 866 args.v1.ucCRTC = crtc_id; 867 args.v1.ucRefDivSrc = 1; 868 break; 869 case 2: 870 args.v2.usPixelClock = cpu_to_le16(clock / 10); 871 args.v2.usRefDiv = cpu_to_le16(ref_div); 872 args.v2.usFbDiv = cpu_to_le16(fb_div); 873 args.v2.ucFracFbDiv = frac_fb_div; 874 args.v2.ucPostDiv = post_div; 875 args.v2.ucPpll = pll_id; 876 args.v2.ucCRTC = crtc_id; 877 args.v2.ucRefDivSrc = 1; 878 break; 879 case 3: 880 args.v3.usPixelClock = cpu_to_le16(clock / 10); 881 args.v3.usRefDiv = cpu_to_le16(ref_div); 882 args.v3.usFbDiv = cpu_to_le16(fb_div); 883 args.v3.ucFracFbDiv = frac_fb_div; 884 args.v3.ucPostDiv = post_div; 885 args.v3.ucPpll = pll_id; 886 if (crtc_id == ATOM_CRTC2) 887 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 888 else 889 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 890 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 891 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 892 args.v3.ucTransmitterId = encoder_id; 893 args.v3.ucEncoderMode = encoder_mode; 894 break; 895 case 5: 896 args.v5.ucCRTC = crtc_id; 897 args.v5.usPixelClock = cpu_to_le16(clock / 10); 898 args.v5.ucRefDiv = ref_div; 899 args.v5.usFbDiv = cpu_to_le16(fb_div); 900 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 901 args.v5.ucPostDiv = post_div; 902 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 903 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 904 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 905 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 906 switch (bpc) { 907 case 8: 908 default: 909 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 910 break; 911 case 10: 912 /* yes this is correct, the atom define is wrong */ 913 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; 914 break; 915 case 12: 916 /* yes this is correct, the atom define is wrong */ 917 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 918 break; 919 } 920 } 921 args.v5.ucTransmitterID = encoder_id; 922 args.v5.ucEncoderMode = encoder_mode; 923 args.v5.ucPpll = pll_id; 924 break; 925 case 6: 926 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 927 args.v6.ucRefDiv = ref_div; 928 args.v6.usFbDiv = cpu_to_le16(fb_div); 929 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 930 args.v6.ucPostDiv = post_div; 931 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 932 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 933 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 934 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 935 switch (bpc) { 936 case 8: 937 default: 938 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 939 break; 940 case 10: 941 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; 942 break; 943 case 12: 944 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; 945 break; 946 case 16: 947 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 948 break; 949 } 950 } 951 args.v6.ucTransmitterID = encoder_id; 952 args.v6.ucEncoderMode = encoder_mode; 953 args.v6.ucPpll = pll_id; 954 break; 955 default: 956 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 957 return; 958 } 959 break; 960 default: 961 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 962 return; 963 } 964 965 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 966 } 967 968 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 969 { 970 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 971 struct drm_device *dev = crtc->dev; 972 struct radeon_device *rdev = dev->dev_private; 973 struct radeon_encoder *radeon_encoder = 974 to_radeon_encoder(radeon_crtc->encoder); 975 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 976 977 radeon_crtc->bpc = 8; 978 radeon_crtc->ss_enabled = false; 979 980 if (radeon_encoder->is_mst_encoder) { 981 radeon_dp_mst_prepare_pll(crtc, mode); 982 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 983 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 984 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 985 struct drm_connector *connector = 986 radeon_get_connector_for_encoder(radeon_crtc->encoder); 987 struct radeon_connector *radeon_connector = 988 to_radeon_connector(connector); 989 struct radeon_connector_atom_dig *dig_connector = 990 radeon_connector->con_priv; 991 int dp_clock; 992 993 /* Assign mode clock for hdmi deep color max clock limit check */ 994 radeon_connector->pixelclock_for_modeset = mode->clock; 995 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 996 997 switch (encoder_mode) { 998 case ATOM_ENCODER_MODE_DP_MST: 999 case ATOM_ENCODER_MODE_DP: 1000 /* DP/eDP */ 1001 dp_clock = dig_connector->dp_clock / 10; 1002 if (ASIC_IS_DCE4(rdev)) 1003 radeon_crtc->ss_enabled = 1004 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 1005 ASIC_INTERNAL_SS_ON_DP, 1006 dp_clock); 1007 else { 1008 if (dp_clock == 16200) { 1009 radeon_crtc->ss_enabled = 1010 radeon_atombios_get_ppll_ss_info(rdev, 1011 &radeon_crtc->ss, 1012 ATOM_DP_SS_ID2); 1013 if (!radeon_crtc->ss_enabled) 1014 radeon_crtc->ss_enabled = 1015 radeon_atombios_get_ppll_ss_info(rdev, 1016 &radeon_crtc->ss, 1017 ATOM_DP_SS_ID1); 1018 } else { 1019 radeon_crtc->ss_enabled = 1020 radeon_atombios_get_ppll_ss_info(rdev, 1021 &radeon_crtc->ss, 1022 ATOM_DP_SS_ID1); 1023 } 1024 /* disable spread spectrum on DCE3 DP */ 1025 radeon_crtc->ss_enabled = false; 1026 } 1027 break; 1028 case ATOM_ENCODER_MODE_LVDS: 1029 if (ASIC_IS_DCE4(rdev)) 1030 radeon_crtc->ss_enabled = 1031 radeon_atombios_get_asic_ss_info(rdev, 1032 &radeon_crtc->ss, 1033 dig->lcd_ss_id, 1034 mode->clock / 10); 1035 else 1036 radeon_crtc->ss_enabled = 1037 radeon_atombios_get_ppll_ss_info(rdev, 1038 &radeon_crtc->ss, 1039 dig->lcd_ss_id); 1040 break; 1041 case ATOM_ENCODER_MODE_DVI: 1042 if (ASIC_IS_DCE4(rdev)) 1043 radeon_crtc->ss_enabled = 1044 radeon_atombios_get_asic_ss_info(rdev, 1045 &radeon_crtc->ss, 1046 ASIC_INTERNAL_SS_ON_TMDS, 1047 mode->clock / 10); 1048 break; 1049 case ATOM_ENCODER_MODE_HDMI: 1050 if (ASIC_IS_DCE4(rdev)) 1051 radeon_crtc->ss_enabled = 1052 radeon_atombios_get_asic_ss_info(rdev, 1053 &radeon_crtc->ss, 1054 ASIC_INTERNAL_SS_ON_HDMI, 1055 mode->clock / 10); 1056 break; 1057 default: 1058 break; 1059 } 1060 } 1061 1062 /* adjust pixel clock as needed */ 1063 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 1064 1065 return true; 1066 } 1067 1068 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 1069 { 1070 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1071 struct drm_device *dev = crtc->dev; 1072 struct radeon_device *rdev = dev->dev_private; 1073 struct radeon_encoder *radeon_encoder = 1074 to_radeon_encoder(radeon_crtc->encoder); 1075 u32 pll_clock = mode->clock; 1076 u32 clock = mode->clock; 1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 1078 struct radeon_pll *pll; 1079 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1080 1081 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ 1082 if (ASIC_IS_DCE5(rdev) && 1083 (encoder_mode == ATOM_ENCODER_MODE_HDMI) && 1084 (radeon_crtc->bpc > 8)) 1085 clock = radeon_crtc->adjusted_clock; 1086 1087 switch (radeon_crtc->pll_id) { 1088 case ATOM_PPLL1: 1089 pll = &rdev->clock.p1pll; 1090 break; 1091 case ATOM_PPLL2: 1092 pll = &rdev->clock.p2pll; 1093 break; 1094 case ATOM_DCPLL: 1095 case ATOM_PPLL_INVALID: 1096 default: 1097 pll = &rdev->clock.dcpll; 1098 break; 1099 } 1100 1101 /* update pll params */ 1102 pll->flags = radeon_crtc->pll_flags; 1103 pll->reference_div = radeon_crtc->pll_reference_div; 1104 pll->post_div = radeon_crtc->pll_post_div; 1105 1106 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1107 /* TV seems to prefer the legacy algo on some boards */ 1108 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1109 &fb_div, &frac_fb_div, &ref_div, &post_div); 1110 else if (ASIC_IS_AVIVO(rdev)) 1111 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1112 &fb_div, &frac_fb_div, &ref_div, &post_div); 1113 else 1114 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1115 &fb_div, &frac_fb_div, &ref_div, &post_div); 1116 1117 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1118 radeon_crtc->crtc_id, &radeon_crtc->ss); 1119 1120 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1121 encoder_mode, radeon_encoder->encoder_id, clock, 1122 ref_div, fb_div, frac_fb_div, post_div, 1123 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1124 1125 if (radeon_crtc->ss_enabled) { 1126 /* calculate ss amount and step size */ 1127 if (ASIC_IS_DCE4(rdev)) { 1128 u32 step_size; 1129 u32 amount = (((fb_div * 10) + frac_fb_div) * 1130 (u32)radeon_crtc->ss.percentage) / 1131 (100 * (u32)radeon_crtc->ss.percentage_divider); 1132 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1133 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1134 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1135 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1136 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1137 (125 * 25 * pll->reference_freq / 100); 1138 else 1139 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1140 (125 * 25 * pll->reference_freq / 100); 1141 radeon_crtc->ss.step = step_size; 1142 } 1143 1144 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1145 radeon_crtc->crtc_id, &radeon_crtc->ss); 1146 } 1147 } 1148 1149 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1150 struct drm_framebuffer *fb, 1151 int x, int y, int atomic) 1152 { 1153 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1154 struct drm_device *dev = crtc->dev; 1155 struct radeon_device *rdev = dev->dev_private; 1156 struct drm_framebuffer *target_fb; 1157 struct drm_gem_object *obj; 1158 struct radeon_bo *rbo; 1159 uint64_t fb_location; 1160 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1161 unsigned bankw, bankh, mtaspect, tile_split; 1162 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1163 u32 tmp, viewport_w, viewport_h; 1164 int r; 1165 bool bypass_lut = false; 1166 struct drm_format_name_buf format_name; 1167 1168 /* no fb bound */ 1169 if (!atomic && !crtc->primary->fb) { 1170 DRM_DEBUG_KMS("No FB bound\n"); 1171 return 0; 1172 } 1173 1174 if (atomic) 1175 target_fb = fb; 1176 else 1177 target_fb = crtc->primary->fb; 1178 1179 /* If atomic, assume fb object is pinned & idle & fenced and 1180 * just update base pointers 1181 */ 1182 obj = target_fb->obj[0]; 1183 rbo = gem_to_radeon_bo(obj); 1184 1185 if (atomic) { 1186 BUG_ON(rbo->pin_count == 0); 1187 fb_location = radeon_bo_gpu_offset(rbo); 1188 tiling_flags = 0; 1189 } else { 1190 r = radeon_bo_reserve(rbo, false); 1191 if (unlikely(r != 0)) 1192 return r; 1193 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1194 if (unlikely(r != 0)) { 1195 radeon_bo_unreserve(rbo); 1196 return -EINVAL; 1197 } 1198 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1199 radeon_bo_unreserve(rbo); 1200 } 1201 1202 switch (target_fb->format->format) { 1203 case DRM_FORMAT_C8: 1204 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1205 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1206 break; 1207 case DRM_FORMAT_XRGB4444: 1208 case DRM_FORMAT_ARGB4444: 1209 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1210 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1211 #ifdef __BIG_ENDIAN 1212 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1213 #endif 1214 break; 1215 case DRM_FORMAT_XRGB1555: 1216 case DRM_FORMAT_ARGB1555: 1217 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1218 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1219 #ifdef __BIG_ENDIAN 1220 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1221 #endif 1222 break; 1223 case DRM_FORMAT_BGRX5551: 1224 case DRM_FORMAT_BGRA5551: 1225 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1226 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1227 #ifdef __BIG_ENDIAN 1228 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1229 #endif 1230 break; 1231 case DRM_FORMAT_RGB565: 1232 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1233 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1234 #ifdef __BIG_ENDIAN 1235 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1236 #endif 1237 break; 1238 case DRM_FORMAT_XRGB8888: 1239 case DRM_FORMAT_ARGB8888: 1240 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1241 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1242 #ifdef __BIG_ENDIAN 1243 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1244 #endif 1245 break; 1246 case DRM_FORMAT_XRGB2101010: 1247 case DRM_FORMAT_ARGB2101010: 1248 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1249 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1250 #ifdef __BIG_ENDIAN 1251 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1252 #endif 1253 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1254 bypass_lut = true; 1255 break; 1256 case DRM_FORMAT_BGRX1010102: 1257 case DRM_FORMAT_BGRA1010102: 1258 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1259 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1260 #ifdef __BIG_ENDIAN 1261 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1262 #endif 1263 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1264 bypass_lut = true; 1265 break; 1266 case DRM_FORMAT_XBGR8888: 1267 case DRM_FORMAT_ABGR8888: 1268 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1269 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1270 fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) | 1271 EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R)); 1272 #ifdef __BIG_ENDIAN 1273 fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1274 #endif 1275 break; 1276 default: 1277 DRM_ERROR("Unsupported screen format %s\n", 1278 drm_get_format_name(target_fb->format->format, &format_name)); 1279 return -EINVAL; 1280 } 1281 1282 if (tiling_flags & RADEON_TILING_MACRO) { 1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1284 1285 /* Set NUM_BANKS. */ 1286 if (rdev->family >= CHIP_TAHITI) { 1287 unsigned index, num_banks; 1288 1289 if (rdev->family >= CHIP_BONAIRE) { 1290 unsigned tileb, tile_split_bytes; 1291 1292 /* Calculate the macrotile mode index. */ 1293 tile_split_bytes = 64 << tile_split; 1294 tileb = 8 * 8 * target_fb->format->cpp[0]; 1295 tileb = min(tile_split_bytes, tileb); 1296 1297 for (index = 0; tileb > 64; index++) 1298 tileb >>= 1; 1299 1300 if (index >= 16) { 1301 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1302 target_fb->format->cpp[0] * 8, 1303 tile_split); 1304 return -EINVAL; 1305 } 1306 1307 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1308 } else { 1309 switch (target_fb->format->cpp[0] * 8) { 1310 case 8: 1311 index = 10; 1312 break; 1313 case 16: 1314 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; 1315 break; 1316 default: 1317 case 32: 1318 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; 1319 break; 1320 } 1321 1322 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1323 } 1324 1325 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1326 } else { 1327 /* NI and older. */ 1328 if (rdev->family >= CHIP_CAYMAN) 1329 tmp = rdev->config.cayman.tile_config; 1330 else 1331 tmp = rdev->config.evergreen.tile_config; 1332 1333 switch ((tmp & 0xf0) >> 4) { 1334 case 0: /* 4 banks */ 1335 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1336 break; 1337 case 1: /* 8 banks */ 1338 default: 1339 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1340 break; 1341 case 2: /* 16 banks */ 1342 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1343 break; 1344 } 1345 } 1346 1347 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1348 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1349 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1350 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1351 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1352 if (rdev->family >= CHIP_BONAIRE) { 1353 /* XXX need to know more about the surface tiling mode */ 1354 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); 1355 } 1356 } else if (tiling_flags & RADEON_TILING_MICRO) 1357 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1358 1359 if (rdev->family >= CHIP_BONAIRE) { 1360 /* Read the pipe config from the 2D TILED SCANOUT mode. 1361 * It should be the same for the other modes too, but not all 1362 * modes set the pipe config field. */ 1363 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; 1364 1365 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); 1366 } else if ((rdev->family == CHIP_TAHITI) || 1367 (rdev->family == CHIP_PITCAIRN)) 1368 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1369 else if ((rdev->family == CHIP_VERDE) || 1370 (rdev->family == CHIP_OLAND) || 1371 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ 1372 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1373 1374 switch (radeon_crtc->crtc_id) { 1375 case 0: 1376 WREG32(AVIVO_D1VGA_CONTROL, 0); 1377 break; 1378 case 1: 1379 WREG32(AVIVO_D2VGA_CONTROL, 0); 1380 break; 1381 case 2: 1382 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1383 break; 1384 case 3: 1385 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1386 break; 1387 case 4: 1388 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1389 break; 1390 case 5: 1391 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1392 break; 1393 default: 1394 break; 1395 } 1396 1397 /* Make sure surface address is updated at vertical blank rather than 1398 * horizontal blank 1399 */ 1400 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); 1401 1402 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1403 upper_32_bits(fb_location)); 1404 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1405 upper_32_bits(fb_location)); 1406 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1407 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1408 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1409 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1410 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1411 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1412 1413 /* 1414 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1415 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1416 * retain the full precision throughout the pipeline. 1417 */ 1418 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, 1419 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1420 ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1421 1422 if (bypass_lut) 1423 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1424 1425 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1426 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1427 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1428 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1429 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1430 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1431 1432 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 1433 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1434 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1435 1436 if (rdev->family >= CHIP_BONAIRE) 1437 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1438 target_fb->height); 1439 else 1440 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1441 target_fb->height); 1442 x &= ~3; 1443 y &= ~1; 1444 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1445 (x << 16) | y); 1446 viewport_w = crtc->mode.hdisplay; 1447 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1448 if ((rdev->family >= CHIP_BONAIRE) && 1449 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) 1450 viewport_h *= 2; 1451 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1452 (viewport_w << 16) | viewport_h); 1453 1454 /* set pageflip to happen anywhere in vblank interval */ 1455 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1456 1457 if (!atomic && fb && fb != crtc->primary->fb) { 1458 rbo = gem_to_radeon_bo(fb->obj[0]); 1459 r = radeon_bo_reserve(rbo, false); 1460 if (unlikely(r != 0)) 1461 return r; 1462 radeon_bo_unpin(rbo); 1463 radeon_bo_unreserve(rbo); 1464 } 1465 1466 /* Bytes per pixel may have changed */ 1467 radeon_bandwidth_update(rdev); 1468 1469 return 0; 1470 } 1471 1472 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1473 struct drm_framebuffer *fb, 1474 int x, int y, int atomic) 1475 { 1476 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1477 struct drm_device *dev = crtc->dev; 1478 struct radeon_device *rdev = dev->dev_private; 1479 struct drm_gem_object *obj; 1480 struct radeon_bo *rbo; 1481 struct drm_framebuffer *target_fb; 1482 uint64_t fb_location; 1483 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1484 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1485 u32 viewport_w, viewport_h; 1486 int r; 1487 bool bypass_lut = false; 1488 struct drm_format_name_buf format_name; 1489 1490 /* no fb bound */ 1491 if (!atomic && !crtc->primary->fb) { 1492 DRM_DEBUG_KMS("No FB bound\n"); 1493 return 0; 1494 } 1495 1496 if (atomic) 1497 target_fb = fb; 1498 else 1499 target_fb = crtc->primary->fb; 1500 1501 obj = target_fb->obj[0]; 1502 rbo = gem_to_radeon_bo(obj); 1503 1504 /* If atomic, assume fb object is pinned & idle & fenced and 1505 * just update base pointers 1506 */ 1507 if (atomic) { 1508 BUG_ON(rbo->pin_count == 0); 1509 fb_location = radeon_bo_gpu_offset(rbo); 1510 tiling_flags = 0; 1511 } else { 1512 r = radeon_bo_reserve(rbo, false); 1513 if (unlikely(r != 0)) 1514 return r; 1515 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1516 if (unlikely(r != 0)) { 1517 radeon_bo_unreserve(rbo); 1518 return -EINVAL; 1519 } 1520 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1521 radeon_bo_unreserve(rbo); 1522 } 1523 1524 switch (target_fb->format->format) { 1525 case DRM_FORMAT_C8: 1526 fb_format = 1527 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1528 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1529 break; 1530 case DRM_FORMAT_XRGB4444: 1531 case DRM_FORMAT_ARGB4444: 1532 fb_format = 1533 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1534 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; 1535 #ifdef __BIG_ENDIAN 1536 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1537 #endif 1538 break; 1539 case DRM_FORMAT_XRGB1555: 1540 fb_format = 1541 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1542 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1543 #ifdef __BIG_ENDIAN 1544 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1545 #endif 1546 break; 1547 case DRM_FORMAT_RGB565: 1548 fb_format = 1549 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1550 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1551 #ifdef __BIG_ENDIAN 1552 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1553 #endif 1554 break; 1555 case DRM_FORMAT_XRGB8888: 1556 case DRM_FORMAT_ARGB8888: 1557 fb_format = 1558 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1559 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1560 #ifdef __BIG_ENDIAN 1561 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1562 #endif 1563 break; 1564 case DRM_FORMAT_XRGB2101010: 1565 case DRM_FORMAT_ARGB2101010: 1566 fb_format = 1567 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1568 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; 1569 #ifdef __BIG_ENDIAN 1570 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1571 #endif 1572 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1573 bypass_lut = true; 1574 break; 1575 case DRM_FORMAT_XBGR8888: 1576 case DRM_FORMAT_ABGR8888: 1577 fb_format = 1578 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1579 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1580 if (rdev->family >= CHIP_R600) 1581 fb_swap = 1582 (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) | 1583 R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R)); 1584 else /* DCE1 (R5xx) */ 1585 fb_format |= AVIVO_D1GRPH_SWAP_RB; 1586 #ifdef __BIG_ENDIAN 1587 fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT; 1588 #endif 1589 break; 1590 default: 1591 DRM_ERROR("Unsupported screen format %s\n", 1592 drm_get_format_name(target_fb->format->format, &format_name)); 1593 return -EINVAL; 1594 } 1595 1596 if (rdev->family >= CHIP_R600) { 1597 if (tiling_flags & RADEON_TILING_MACRO) 1598 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1599 else if (tiling_flags & RADEON_TILING_MICRO) 1600 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1601 } else { 1602 if (tiling_flags & RADEON_TILING_MACRO) 1603 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1604 1605 if (tiling_flags & RADEON_TILING_MICRO) 1606 fb_format |= AVIVO_D1GRPH_TILED; 1607 } 1608 1609 if (radeon_crtc->crtc_id == 0) 1610 WREG32(AVIVO_D1VGA_CONTROL, 0); 1611 else 1612 WREG32(AVIVO_D2VGA_CONTROL, 0); 1613 1614 /* Make sure surface address is update at vertical blank rather than 1615 * horizontal blank 1616 */ 1617 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); 1618 1619 if (rdev->family >= CHIP_RV770) { 1620 if (radeon_crtc->crtc_id) { 1621 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1622 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1623 } else { 1624 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1625 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1626 } 1627 } 1628 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1629 (u32) fb_location); 1630 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1631 radeon_crtc->crtc_offset, (u32) fb_location); 1632 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1633 if (rdev->family >= CHIP_R600) 1634 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1635 1636 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ 1637 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, 1638 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); 1639 1640 if (bypass_lut) 1641 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1642 1643 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1644 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1645 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1646 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1647 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1648 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1649 1650 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 1651 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1652 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1653 1654 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1655 target_fb->height); 1656 x &= ~3; 1657 y &= ~1; 1658 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1659 (x << 16) | y); 1660 viewport_w = crtc->mode.hdisplay; 1661 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1662 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1663 (viewport_w << 16) | viewport_h); 1664 1665 /* set pageflip to happen only at start of vblank interval (front porch) */ 1666 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1667 1668 if (!atomic && fb && fb != crtc->primary->fb) { 1669 rbo = gem_to_radeon_bo(fb->obj[0]); 1670 r = radeon_bo_reserve(rbo, false); 1671 if (unlikely(r != 0)) 1672 return r; 1673 radeon_bo_unpin(rbo); 1674 radeon_bo_unreserve(rbo); 1675 } 1676 1677 /* Bytes per pixel may have changed */ 1678 radeon_bandwidth_update(rdev); 1679 1680 return 0; 1681 } 1682 1683 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1684 struct drm_framebuffer *old_fb) 1685 { 1686 struct drm_device *dev = crtc->dev; 1687 struct radeon_device *rdev = dev->dev_private; 1688 1689 if (ASIC_IS_DCE4(rdev)) 1690 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1691 else if (ASIC_IS_AVIVO(rdev)) 1692 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1693 else 1694 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1695 } 1696 1697 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1698 struct drm_framebuffer *fb, 1699 int x, int y, enum mode_set_atomic state) 1700 { 1701 struct drm_device *dev = crtc->dev; 1702 struct radeon_device *rdev = dev->dev_private; 1703 1704 if (ASIC_IS_DCE4(rdev)) 1705 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1706 else if (ASIC_IS_AVIVO(rdev)) 1707 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1708 else 1709 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1710 } 1711 1712 /* properly set additional regs when using atombios */ 1713 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1714 { 1715 struct drm_device *dev = crtc->dev; 1716 struct radeon_device *rdev = dev->dev_private; 1717 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1718 u32 disp_merge_cntl; 1719 1720 switch (radeon_crtc->crtc_id) { 1721 case 0: 1722 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1723 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1724 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1725 break; 1726 case 1: 1727 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1728 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1729 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1730 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1731 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1732 break; 1733 } 1734 } 1735 1736 /** 1737 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1738 * 1739 * @crtc: drm crtc 1740 * 1741 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1742 */ 1743 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1744 { 1745 struct drm_device *dev = crtc->dev; 1746 struct drm_crtc *test_crtc; 1747 struct radeon_crtc *test_radeon_crtc; 1748 u32 pll_in_use = 0; 1749 1750 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1751 if (crtc == test_crtc) 1752 continue; 1753 1754 test_radeon_crtc = to_radeon_crtc(test_crtc); 1755 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1756 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1757 } 1758 return pll_in_use; 1759 } 1760 1761 /** 1762 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1763 * 1764 * @crtc: drm crtc 1765 * 1766 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1767 * also in DP mode. For DP, a single PPLL can be used for all DP 1768 * crtcs/encoders. 1769 */ 1770 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1771 { 1772 struct drm_device *dev = crtc->dev; 1773 struct radeon_device *rdev = dev->dev_private; 1774 struct drm_crtc *test_crtc; 1775 struct radeon_crtc *test_radeon_crtc; 1776 1777 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1778 if (crtc == test_crtc) 1779 continue; 1780 test_radeon_crtc = to_radeon_crtc(test_crtc); 1781 if (test_radeon_crtc->encoder && 1782 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1783 /* PPLL2 is exclusive to UNIPHYA on DCE61 */ 1784 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && 1785 test_radeon_crtc->pll_id == ATOM_PPLL2) 1786 continue; 1787 /* for DP use the same PLL for all */ 1788 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1789 return test_radeon_crtc->pll_id; 1790 } 1791 } 1792 return ATOM_PPLL_INVALID; 1793 } 1794 1795 /** 1796 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1797 * 1798 * @crtc: drm crtc 1799 * @encoder: drm encoder 1800 * 1801 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1802 * be shared (i.e., same clock). 1803 */ 1804 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1805 { 1806 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1807 struct drm_device *dev = crtc->dev; 1808 struct radeon_device *rdev = dev->dev_private; 1809 struct drm_crtc *test_crtc; 1810 struct radeon_crtc *test_radeon_crtc; 1811 u32 adjusted_clock, test_adjusted_clock; 1812 1813 adjusted_clock = radeon_crtc->adjusted_clock; 1814 1815 if (adjusted_clock == 0) 1816 return ATOM_PPLL_INVALID; 1817 1818 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1819 if (crtc == test_crtc) 1820 continue; 1821 test_radeon_crtc = to_radeon_crtc(test_crtc); 1822 if (test_radeon_crtc->encoder && 1823 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1824 /* PPLL2 is exclusive to UNIPHYA on DCE61 */ 1825 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && 1826 test_radeon_crtc->pll_id == ATOM_PPLL2) 1827 continue; 1828 /* check if we are already driving this connector with another crtc */ 1829 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1830 /* if we are, return that pll */ 1831 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1832 return test_radeon_crtc->pll_id; 1833 } 1834 /* for non-DP check the clock */ 1835 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1836 if ((crtc->mode.clock == test_crtc->mode.clock) && 1837 (adjusted_clock == test_adjusted_clock) && 1838 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1839 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1840 return test_radeon_crtc->pll_id; 1841 } 1842 } 1843 return ATOM_PPLL_INVALID; 1844 } 1845 1846 /** 1847 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1848 * 1849 * @crtc: drm crtc 1850 * 1851 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1852 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1853 * monitors a dedicated PPLL must be used. If a particular board has 1854 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1855 * as there is no need to program the PLL itself. If we are not able to 1856 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1857 * avoid messing up an existing monitor. 1858 * 1859 * Asic specific PLL information 1860 * 1861 * DCE 8.x 1862 * KB/KV 1863 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 1864 * CI 1865 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1866 * 1867 * DCE 6.1 1868 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1869 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1870 * 1871 * DCE 6.0 1872 * - PPLL0 is available to all UNIPHY (DP only) 1873 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1874 * 1875 * DCE 5.0 1876 * - DCPLL is available to all UNIPHY (DP only) 1877 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1878 * 1879 * DCE 3.0/4.0/4.1 1880 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1881 * 1882 */ 1883 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1884 { 1885 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1886 struct drm_device *dev = crtc->dev; 1887 struct radeon_device *rdev = dev->dev_private; 1888 struct radeon_encoder *radeon_encoder = 1889 to_radeon_encoder(radeon_crtc->encoder); 1890 u32 pll_in_use; 1891 int pll; 1892 1893 if (ASIC_IS_DCE8(rdev)) { 1894 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1895 if (rdev->clock.dp_extclk) 1896 /* skip PPLL programming if using ext clock */ 1897 return ATOM_PPLL_INVALID; 1898 else { 1899 /* use the same PPLL for all DP monitors */ 1900 pll = radeon_get_shared_dp_ppll(crtc); 1901 if (pll != ATOM_PPLL_INVALID) 1902 return pll; 1903 } 1904 } else { 1905 /* use the same PPLL for all monitors with the same clock */ 1906 pll = radeon_get_shared_nondp_ppll(crtc); 1907 if (pll != ATOM_PPLL_INVALID) 1908 return pll; 1909 } 1910 /* otherwise, pick one of the plls */ 1911 if ((rdev->family == CHIP_KABINI) || 1912 (rdev->family == CHIP_MULLINS)) { 1913 /* KB/ML has PPLL1 and PPLL2 */ 1914 pll_in_use = radeon_get_pll_use_mask(crtc); 1915 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1916 return ATOM_PPLL2; 1917 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1918 return ATOM_PPLL1; 1919 DRM_ERROR("unable to allocate a PPLL\n"); 1920 return ATOM_PPLL_INVALID; 1921 } else { 1922 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 1923 pll_in_use = radeon_get_pll_use_mask(crtc); 1924 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1925 return ATOM_PPLL2; 1926 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1927 return ATOM_PPLL1; 1928 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1929 return ATOM_PPLL0; 1930 DRM_ERROR("unable to allocate a PPLL\n"); 1931 return ATOM_PPLL_INVALID; 1932 } 1933 } else if (ASIC_IS_DCE61(rdev)) { 1934 struct radeon_encoder_atom_dig *dig = 1935 radeon_encoder->enc_priv; 1936 1937 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1938 (dig->linkb == false)) 1939 /* UNIPHY A uses PPLL2 */ 1940 return ATOM_PPLL2; 1941 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1942 /* UNIPHY B/C/D/E/F */ 1943 if (rdev->clock.dp_extclk) 1944 /* skip PPLL programming if using ext clock */ 1945 return ATOM_PPLL_INVALID; 1946 else { 1947 /* use the same PPLL for all DP monitors */ 1948 pll = radeon_get_shared_dp_ppll(crtc); 1949 if (pll != ATOM_PPLL_INVALID) 1950 return pll; 1951 } 1952 } else { 1953 /* use the same PPLL for all monitors with the same clock */ 1954 pll = radeon_get_shared_nondp_ppll(crtc); 1955 if (pll != ATOM_PPLL_INVALID) 1956 return pll; 1957 } 1958 /* UNIPHY B/C/D/E/F */ 1959 pll_in_use = radeon_get_pll_use_mask(crtc); 1960 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1961 return ATOM_PPLL0; 1962 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1963 return ATOM_PPLL1; 1964 DRM_ERROR("unable to allocate a PPLL\n"); 1965 return ATOM_PPLL_INVALID; 1966 } else if (ASIC_IS_DCE41(rdev)) { 1967 /* Don't share PLLs on DCE4.1 chips */ 1968 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1969 if (rdev->clock.dp_extclk) 1970 /* skip PPLL programming if using ext clock */ 1971 return ATOM_PPLL_INVALID; 1972 } 1973 pll_in_use = radeon_get_pll_use_mask(crtc); 1974 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1975 return ATOM_PPLL1; 1976 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1977 return ATOM_PPLL2; 1978 DRM_ERROR("unable to allocate a PPLL\n"); 1979 return ATOM_PPLL_INVALID; 1980 } else if (ASIC_IS_DCE4(rdev)) { 1981 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1982 * depending on the asic: 1983 * DCE4: PPLL or ext clock 1984 * DCE5: PPLL, DCPLL, or ext clock 1985 * DCE6: PPLL, PPLL0, or ext clock 1986 * 1987 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1988 * PPLL/DCPLL programming and only program the DP DTO for the 1989 * crtc virtual pixel clock. 1990 */ 1991 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1992 if (rdev->clock.dp_extclk) 1993 /* skip PPLL programming if using ext clock */ 1994 return ATOM_PPLL_INVALID; 1995 else if (ASIC_IS_DCE6(rdev)) 1996 /* use PPLL0 for all DP */ 1997 return ATOM_PPLL0; 1998 else if (ASIC_IS_DCE5(rdev)) 1999 /* use DCPLL for all DP */ 2000 return ATOM_DCPLL; 2001 else { 2002 /* use the same PPLL for all DP monitors */ 2003 pll = radeon_get_shared_dp_ppll(crtc); 2004 if (pll != ATOM_PPLL_INVALID) 2005 return pll; 2006 } 2007 } else { 2008 /* use the same PPLL for all monitors with the same clock */ 2009 pll = radeon_get_shared_nondp_ppll(crtc); 2010 if (pll != ATOM_PPLL_INVALID) 2011 return pll; 2012 } 2013 /* all other cases */ 2014 pll_in_use = radeon_get_pll_use_mask(crtc); 2015 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2016 return ATOM_PPLL1; 2017 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2018 return ATOM_PPLL2; 2019 DRM_ERROR("unable to allocate a PPLL\n"); 2020 return ATOM_PPLL_INVALID; 2021 } else { 2022 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 2023 /* some atombios (observed in some DCE2/DCE3) code have a bug, 2024 * the matching btw pll and crtc is done through 2025 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 2026 * pll (1 or 2) to select which register to write. ie if using 2027 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 2028 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 2029 * choose which value to write. Which is reverse order from 2030 * register logic. So only case that works is when pllid is 2031 * same as crtcid or when both pll and crtc are enabled and 2032 * both use same clock. 2033 * 2034 * So just return crtc id as if crtc and pll were hard linked 2035 * together even if they aren't 2036 */ 2037 return radeon_crtc->crtc_id; 2038 } 2039 } 2040 2041 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 2042 { 2043 /* always set DCPLL */ 2044 if (ASIC_IS_DCE6(rdev)) 2045 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2046 else if (ASIC_IS_DCE4(rdev)) { 2047 struct radeon_atom_ss ss; 2048 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 2049 ASIC_INTERNAL_SS_ON_DCPLL, 2050 rdev->clock.default_dispclk); 2051 if (ss_enabled) 2052 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 2053 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 2054 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2055 if (ss_enabled) 2056 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 2057 } 2058 2059 } 2060 2061 int atombios_crtc_mode_set(struct drm_crtc *crtc, 2062 struct drm_display_mode *mode, 2063 struct drm_display_mode *adjusted_mode, 2064 int x, int y, struct drm_framebuffer *old_fb) 2065 { 2066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2067 struct drm_device *dev = crtc->dev; 2068 struct radeon_device *rdev = dev->dev_private; 2069 struct radeon_encoder *radeon_encoder = 2070 to_radeon_encoder(radeon_crtc->encoder); 2071 bool is_tvcv = false; 2072 2073 if (radeon_encoder->active_device & 2074 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2075 is_tvcv = true; 2076 2077 if (!radeon_crtc->adjusted_clock) 2078 return -EINVAL; 2079 2080 atombios_crtc_set_pll(crtc, adjusted_mode); 2081 2082 if (ASIC_IS_DCE4(rdev)) 2083 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2084 else if (ASIC_IS_AVIVO(rdev)) { 2085 if (is_tvcv) 2086 atombios_crtc_set_timing(crtc, adjusted_mode); 2087 else 2088 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2089 } else { 2090 atombios_crtc_set_timing(crtc, adjusted_mode); 2091 if (radeon_crtc->crtc_id == 0) 2092 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2093 radeon_legacy_atom_fixup(crtc); 2094 } 2095 atombios_crtc_set_base(crtc, x, y, old_fb); 2096 atombios_overscan_setup(crtc, mode, adjusted_mode); 2097 atombios_scaler_setup(crtc); 2098 radeon_cursor_reset(crtc); 2099 /* update the hw version fpr dpm */ 2100 radeon_crtc->hw_mode = *adjusted_mode; 2101 2102 return 0; 2103 } 2104 2105 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 2106 const struct drm_display_mode *mode, 2107 struct drm_display_mode *adjusted_mode) 2108 { 2109 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2110 struct drm_device *dev = crtc->dev; 2111 struct drm_encoder *encoder; 2112 2113 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 2114 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2115 if (encoder->crtc == crtc) { 2116 radeon_crtc->encoder = encoder; 2117 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 2118 break; 2119 } 2120 } 2121 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 2122 radeon_crtc->encoder = NULL; 2123 radeon_crtc->connector = NULL; 2124 return false; 2125 } 2126 if (radeon_crtc->encoder) { 2127 struct radeon_encoder *radeon_encoder = 2128 to_radeon_encoder(radeon_crtc->encoder); 2129 2130 radeon_crtc->output_csc = radeon_encoder->output_csc; 2131 } 2132 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2133 return false; 2134 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2135 return false; 2136 /* pick pll */ 2137 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 2138 /* if we can't get a PPLL for a non-DP encoder, fail */ 2139 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 2140 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 2141 return false; 2142 2143 return true; 2144 } 2145 2146 static void atombios_crtc_prepare(struct drm_crtc *crtc) 2147 { 2148 struct drm_device *dev = crtc->dev; 2149 struct radeon_device *rdev = dev->dev_private; 2150 2151 /* disable crtc pair power gating before programming */ 2152 if (ASIC_IS_DCE6(rdev)) 2153 atombios_powergate_crtc(crtc, ATOM_DISABLE); 2154 2155 atombios_lock_crtc(crtc, ATOM_ENABLE); 2156 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2157 } 2158 2159 static void atombios_crtc_commit(struct drm_crtc *crtc) 2160 { 2161 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2162 atombios_lock_crtc(crtc, ATOM_DISABLE); 2163 } 2164 2165 static void atombios_crtc_disable(struct drm_crtc *crtc) 2166 { 2167 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2168 struct drm_device *dev = crtc->dev; 2169 struct radeon_device *rdev = dev->dev_private; 2170 struct radeon_atom_ss ss; 2171 int i; 2172 2173 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2174 if (crtc->primary->fb) { 2175 int r; 2176 struct radeon_bo *rbo; 2177 2178 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); 2179 r = radeon_bo_reserve(rbo, false); 2180 if (unlikely(r)) 2181 DRM_ERROR("failed to reserve rbo before unpin\n"); 2182 else { 2183 radeon_bo_unpin(rbo); 2184 radeon_bo_unreserve(rbo); 2185 } 2186 } 2187 /* disable the GRPH */ 2188 if (ASIC_IS_DCE4(rdev)) 2189 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2190 else if (ASIC_IS_AVIVO(rdev)) 2191 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2192 2193 if (ASIC_IS_DCE6(rdev)) 2194 atombios_powergate_crtc(crtc, ATOM_ENABLE); 2195 2196 for (i = 0; i < rdev->num_crtc; i++) { 2197 if (rdev->mode_info.crtcs[i] && 2198 rdev->mode_info.crtcs[i]->enabled && 2199 i != radeon_crtc->crtc_id && 2200 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 2201 /* one other crtc is using this pll don't turn 2202 * off the pll 2203 */ 2204 goto done; 2205 } 2206 } 2207 2208 switch (radeon_crtc->pll_id) { 2209 case ATOM_PPLL1: 2210 case ATOM_PPLL2: 2211 /* disable the ppll */ 2212 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2213 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2214 break; 2215 case ATOM_PPLL0: 2216 /* disable the ppll */ 2217 if ((rdev->family == CHIP_ARUBA) || 2218 (rdev->family == CHIP_KAVERI) || 2219 (rdev->family == CHIP_BONAIRE) || 2220 (rdev->family == CHIP_HAWAII)) 2221 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2222 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2223 break; 2224 default: 2225 break; 2226 } 2227 done: 2228 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2229 radeon_crtc->adjusted_clock = 0; 2230 radeon_crtc->encoder = NULL; 2231 radeon_crtc->connector = NULL; 2232 } 2233 2234 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 2235 .dpms = atombios_crtc_dpms, 2236 .mode_fixup = atombios_crtc_mode_fixup, 2237 .mode_set = atombios_crtc_mode_set, 2238 .mode_set_base = atombios_crtc_set_base, 2239 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 2240 .prepare = atombios_crtc_prepare, 2241 .commit = atombios_crtc_commit, 2242 .disable = atombios_crtc_disable, 2243 }; 2244 2245 void radeon_atombios_init_crtc(struct drm_device *dev, 2246 struct radeon_crtc *radeon_crtc) 2247 { 2248 struct radeon_device *rdev = dev->dev_private; 2249 2250 if (ASIC_IS_DCE4(rdev)) { 2251 switch (radeon_crtc->crtc_id) { 2252 case 0: 2253 default: 2254 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 2255 break; 2256 case 1: 2257 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 2258 break; 2259 case 2: 2260 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 2261 break; 2262 case 3: 2263 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 2264 break; 2265 case 4: 2266 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 2267 break; 2268 case 5: 2269 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 2270 break; 2271 } 2272 } else { 2273 if (radeon_crtc->crtc_id == 1) 2274 radeon_crtc->crtc_offset = 2275 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 2276 else 2277 radeon_crtc->crtc_offset = 0; 2278 } 2279 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2280 radeon_crtc->adjusted_clock = 0; 2281 radeon_crtc->encoder = NULL; 2282 radeon_crtc->connector = NULL; 2283 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 2284 } 2285
Indexes created Sat Sep 20 22:09:52 GMT 2025